JPS6399574A - memory device - Google Patents
memory deviceInfo
- Publication number
- JPS6399574A JPS6399574A JP61245685A JP24568586A JPS6399574A JP S6399574 A JPS6399574 A JP S6399574A JP 61245685 A JP61245685 A JP 61245685A JP 24568586 A JP24568586 A JP 24568586A JP S6399574 A JPS6399574 A JP S6399574A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- memory device
- sidewall
- selection gate
- selection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005530 etching Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 101150114751 SEM1 gene Proteins 0.000 description 1
- LPQOADBMXVRBNX-UHFFFAOYSA-N ac1ldcw0 Chemical compound Cl.C1CN(C)CCN1C1=C(F)C=C2C(=O)C(C(O)=O)=CN3CCSC1=C32 LPQOADBMXVRBNX-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、メモリ装置、特にＭＮＯ８又はＭＯＮＯ８構
造を有する不揮発性メモリ装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device, particularly a nonvolatile memory device having an MNO8 or MONO8 structure.
本発明は、ＭＮＯ８又はＭＯＮＯ８構造を有するメモリ
装置において、選択ゲートを制御ゲートの側壁部に絶縁
膜を介してサイドウオールとし【形成することにより、
製造工程の簡略化を図ることができるようにしたもので
ある。The present invention provides a memory device having an MNO8 or MONO8 structure, in which the selection gate is formed as a sidewall on the sidewall of the control gate with an insulating film interposed therebetween.
This makes it possible to simplify the manufacturing process.
従来のＭＮＯ８構造を有するメモリ装置（例えばＢＥＦ
ＲＯＭ）の場合、信頼性の点から制御部（記憶部）トラ
ンジスタと選択部トランジスタを１組とした２トランジ
スタで１メモリセルが構成されていた。しかし、このよ
うな２トランジスタ１セル構造による場合、高集積化が
困難であるため、第３図に示すように、１トランジスタ
にＭＮＯ８構造の制御ゲート（力と選択ゲート（８）を
形成し、更にソース領域（Ｌ２と制御ゲート（７）を分
離するだめの分離ゲー）（ｌＳ）を設けることによりメ
モリセルを構成した所謂トライゲート型のメモリ装置が
提案されている。第３図において、（１）はＮ形Ｓｔ基
板、（２）はＰ形つェル、（１３はドレイン領域、（３
）はトンネル領域となる薄い酸化膜、（４）は８ｉＮ膜
である。A memory device with a conventional MNO8 structure (e.g. BEF
In the case of a ROM (ROM), one memory cell is composed of two transistors, a set of a control section (storage section) transistor and a selection section transistor, from the viewpoint of reliability. However, with such a two-transistor one-cell structure, it is difficult to achieve high integration, so as shown in FIG. A so-called tri-gate type memory device has been proposed in which the memory cell is configured by further providing a source region (isolation gate for separating L2 and control gate (7)) (lS).In FIG. 1) is an N-type St substrate, (2) is a P-type well, (13 is a drain region, (3)
) is a thin oxide film that becomes a tunnel region, and (4) is an 8iN film.
上述した従来のトライゲート型のＭＮＯ８構造を有する
メモリ装置によれば、製造工程におい【選択ゲート（８
）をセル７アライ／メントで形成することができず、多
数のマスクを使用して形成していた。このため、１）マ
スクのずれにより選択ゲートのゲート長が変る。 Ｉ
Ｉ）マスクの合せマージンが必要であるため、高集積化
が困難である、１ｉｔ）必要なマスクの枚数が多くなり
、製造コストが嵩む、などの問題点があった。According to the memory device having the conventional tri-gate type MNO8 structure described above, [selection gate (8
) could not be formed by cell 7 alignment/ment, and many masks were used to form it. Therefore, 1) the gate length of the selection gate changes due to the mask shift. I
There were problems such as: I) It is difficult to achieve high integration because a mask alignment margin is required; and 1) The number of required masks increases, increasing manufacturing costs.
本発明は、上記問題点を解決することができるメモリ装
置を提供するものである。The present invention provides a memory device that can solve the above problems.
本発明は、牛導体基板（１）に形成されたソース領域α
３とドレイン領域α３間上に絶縁膜（３）を介して制御
ゲート（７）と選択ゲート（８）か形成されたメモリ装
置において、選択ゲ−）（８）を、制御ゲー）（７）ｉ
１１１１層ｌｌ）に絶縁膜（３）を介して形成し、且つ
この選択ゲート（８）を異方性エツチングによるサイド
ウオールａυとして形成することを特徴とする。The present invention provides a source region α formed on a conductor substrate (1).
In a memory device in which a control gate (7) and a selection gate (8) are formed between the drain region α3 and the drain region α3 via an insulating film (3), the selection gate (8) and the control gate (7) are formed. i
It is characterized in that it is formed on the 1111 layer ll) with an insulating film (3) interposed therebetween, and that the selection gate (8) is formed as a sidewall aυ by anisotropic etching.
本発明によれば、選択ゲート（８）を制御ゲート（７）
の側壁部任〔に異方性エツチングによるサイドウオール
現象を利用して形成するため、セルフアラインメントと
なり、従来のようなマスクの使用か不要となる。According to the invention, the selection gate (8) is replaced by the control gate (7).
Since the sidewall is formed by utilizing the sidewall phenomenon caused by anisotropic etching, it is self-aligned and does not require the use of a conventional mask.
図面を参照して本発明の１実施例をその製法例と併せて
説明する。An embodiment of the present invention will be described together with an example of its manufacturing method with reference to the drawings.
先ず、第１図Ａに示すように、Ｎ形Ｓｉ基板（１）にＰ
形つェル（２）を形成した後、この上にトンネル領域と
なる薄いゲート酸化膜（３）、ゲー）ＳｉＮ膜（４）及
び制御ゲート（７）となる多結晶Ｓｌ（又はポリサイド
）層（５）をＣＶＤで積層形成する。なお、ＭＯＮＯＳ
（Ｍｅ ｔ ａ １０ｘｉｄｅ Ｎ１ｔｒｉｄｅ ０
ｘｉｄｅ Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ）構造の場合に
は、８ｉＮ膜（４）の上に５ｔＯ２膜を形成する。First, as shown in FIG. 1A, P is applied to the N-type Si substrate (1).
After forming a shaped well (2), a thin gate oxide film (3) which will become a tunnel region, a SiN film (4) and a polycrystalline Sl (or polycide) layer which will become a control gate (7) are formed on this. (5) is laminated by CVD. In addition, MONOS
(Meta 10xide N1tride 0
In the case of the xide Sem1 conductor structure, a 5tO2 film is formed on the 8iN film (4).
次に第１図Ｂに示すように、ホトリソグラフィにより制
御（記憶）ゲート（７）を形成すべき部分の多結晶８１
層（５）上にホトレジスト（６）を形成し、エツチング
を施して制御ゲート（７）を選択的に形成する。Next, as shown in FIG. 1B, a polycrystalline 81 in a portion where a control (storage) gate (7) is to be formed is formed by photolithography.
A photoresist (6) is formed on the layer (5) and etched to selectively form the control gate (7).
次に第１図Ｃに示すように、制御ゲート（７）の多結晶
Ｓｉを熱酸化して酸化膜（３）を形成する。Next, as shown in FIG. 1C, the polycrystalline Si of the control gate (7) is thermally oxidized to form an oxide film (3).
次に第１図りに示すように、選択ゲート（８）を形成す
るための多結晶Ｓｉ層（９）を形成する。Next, as shown in the first diagram, a polycrystalline Si layer (9) for forming a selection gate (8) is formed.
次に第１図Ｅに示すよ５に、多結晶Ｓｉ層（９）に対し
てＲＩＥ （反応性イオンエツチング）による異方性エ
ツチングを施すことにより、制御ゲート（７）の側壁部
（１１）に酸化膜（３）を介して多結晶Ｓｉのサイドウ
オーＡ／αυを形成し、このサイドウオールαυを選択
ゲート（８）とする。なお、この制御ゲート（力の両側
に形成された選択ゲート（８）のいずれか一方を従来例
と同様に分離ゲートとして使用しても良い。Next, as shown in FIG. 1E, by anisotropically etching the polycrystalline Si layer (9) by RIE (reactive ion etching), the sidewall portion (11) of the control gate (7) is removed. A sidewall A/αυ of polycrystalline Si is formed through an oxide film (3), and this sidewall αυ is used as a selection gate (8). Note that either one of the control gates (the selection gates (8) formed on both sides of the force) may be used as a separation gate as in the conventional example.
最後に、第１図Ｆに示すように、ｓ ｔｏ２より成る絶
縁膜（３）の形成とＮ形の不純物である例えばＡｓ”の
イオン注入を行ってソース領域（１３とドレイ／領域口
３を形成する。このソース領域（１ｚとドレイ／領域口
ふの形成は、サイドウオールａυである選択ゲート（８
）によってセルフアラインメントで形成できる。Finally, as shown in FIG. The source region (1z) and the drain/region opening are formed by forming the selection gate (8) which is the sidewall aυ.
) can be formed by self-alignment.
また、サイドウオールＵυの選択ゲート（８）は次のよ
うにして形成することができる。Further, the selection gate (8) of the sidewall Uυ can be formed as follows.
第２図Ａに示すように、ゲート長りを規制し、ウェット
エツチングの際に多結晶８ｉより成る選択ゲート（８）
とのエツチング比が異る材料（例えば、５ｉ０２．レジ
スト等）でいわばダミ一層Ｉを形成した後、第１図りと
同様に全面に多結晶Ｓｔ層を形成し、ＲＩＢによる異方
性エツチングを施してダＺ 一層Ｉの両側に多結晶Ｓｉ
のサイドウオールａυを形成し、このサイドウオールα
υを選択ゲート（８）とする。As shown in FIG. 2A, the selection gate (8) made of polycrystalline 8i is used to regulate the gate length and is used during wet etching.
After forming a so-called dummy layer I with a material (for example, 5i02.resist, etc.) having a different etching ratio from the etching ratio, a polycrystalline St layer is formed on the entire surface as in the first diagram, and anisotropic etching is performed using RIB. Polycrystalline Si on both sides of the single layer I
form a sidewall aυ, and this sidewall α
Let υ be a selection gate (8).
次に第２図Ｂに示すように、ウェットエツチングを施し
てダミ一層Ｉを選択的に除去する。Next, as shown in FIG. 2B, wet etching is performed to selectively remove the dummy layer I.
次に第２図Ｃに示すように、酸化膜（３）と８ｉＮ膜（
４）を形成した後、多結晶Ｓｌより成る制御ゲート（７
）をホトリソグラフィで形成する。最後に、Ｎ形の不純
物である例えばＡｓ のイオン注入を行ってソース領
域（ｌｚとドＶイン領域Ｑ９を形成する。Next, as shown in FIG. 2C, the oxide film (3) and the 8iN film (
4), a control gate (7) made of polycrystalline Sl is formed.
) is formed by photolithography. Finally, N-type impurities such as As are ion-implanted to form a source region (lz) and a doped V-in region Q9.
本発明によれば、選択ゲートを制御ゲートの側壁部にサ
イドウオールとして形成するため、セルフアラインメン
トによる形成が可能になる。これによって、マスクずれ
等の影響がなくなり、高集積化を図ることができる。ま
た、従来構造に係るトライゲートｌ顕ＯＳ（又はＭＯＮ
Ｏ８）メモリ装置の場合、ゲートの形成のために３．４
枚のマスクを必要としていたが、本メモリ装置によれば
１．２枚のマスクで形成することができる。According to the present invention, since the selection gate is formed as a sidewall on the side wall portion of the control gate, it is possible to form the selection gate by self-alignment. This eliminates the influence of mask misalignment, etc., and allows higher integration. In addition, a tri-gate OS (or MON) according to the conventional structure
O8) For memory devices, 3.4 for gate formation
However, according to the present memory device, the memory device can be formed using 1.2 masks.
第１図は本実施例の製法例の工程図、第２図は他の製法
例の工程図、第３図は従来例の断面図である。
（１）はＮ形８ｉ基板、（２）はＰ形つェル、（３）は
酸化膜、（７）は制御ゲー）、（８）は選択ゲート、α
υはサイドウオール、α２はソース領域、０国はドレイ
ン領域である。FIG. 1 is a process diagram of a manufacturing method example of this embodiment, FIG. 2 is a process diagram of another manufacturing method example, and FIG. 3 is a sectional view of a conventional example. (1) is N type 8i substrate, (2) is P type well, (3) is oxide film, (7) is control gate), (8) is selection gate, α
υ is a sidewall, α2 is a source region, and country 0 is a drain region.
Claims (1)
上に絶縁膜を介して制御ゲートと選択ゲートが形成され
たメモリ装置において、 上記選択ゲートは、上記制御ゲート側壁部に絶縁膜を介
して形成され、且つ該選択ゲートは、異方性エッチング
により形成されたサイドウォールであることを特徴とす
るメモリ装置。[Claims] In a memory device in which a control gate and a selection gate are formed between a source region and a drain region formed on a semiconductor substrate with an insulating film interposed therebetween, the selection gate is insulated on a side wall of the control gate. 1. A memory device formed through a film, wherein the selection gate is a sidewall formed by anisotropic etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61245685A JPS6399574A (en) | 1986-10-16 | 1986-10-16 | memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61245685A JPS6399574A (en) | 1986-10-16 | 1986-10-16 | memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6399574A true JPS6399574A (en) | 1988-04-30 |
Family
ID=17137289
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61245685A Pending JPS6399574A (en) | 1986-10-16 | 1986-10-16 | memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6399574A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6563728B2 (en) * | 2000-06-12 | 2003-05-13 | Sony Corporation | Semiconductor memory device and method for operation thereof |
| JP2005086205A (en) * | 2003-09-09 | 2005-03-31 | Samsung Electronics Co Ltd | Split gate type memory device and manufacturing method thereof |
| JP2005086209A (en) * | 2003-09-09 | 2005-03-31 | Samsung Electronics Co Ltd | Local SONOS type memory device and manufacturing method thereof |
| JP2008028410A (en) * | 2007-08-27 | 2008-02-07 | Renesas Technology Corp | Method of manufacturing semiconductor device |
-
1986
- 1986-10-16 JP JP61245685A patent/JPS6399574A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6563728B2 (en) * | 2000-06-12 | 2003-05-13 | Sony Corporation | Semiconductor memory device and method for operation thereof |
| JP2005086205A (en) * | 2003-09-09 | 2005-03-31 | Samsung Electronics Co Ltd | Split gate type memory device and manufacturing method thereof |
| JP2005086209A (en) * | 2003-09-09 | 2005-03-31 | Samsung Electronics Co Ltd | Local SONOS type memory device and manufacturing method thereof |
| JP2008028410A (en) * | 2007-08-27 | 2008-02-07 | Renesas Technology Corp | Method of manufacturing semiconductor device |
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