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JPS6395727A - Gate driving circuit for igbt - Google Patents

Gate driving circuit for igbt

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Publication number
JPS6395727A
JPS6395727A JP61241407A JP24140786A JPS6395727A JP S6395727 A JPS6395727 A JP S6395727A JP 61241407 A JP61241407 A JP 61241407A JP 24140786 A JP24140786 A JP 24140786A JP S6395727 A JPS6395727 A JP S6395727A
Authority
JP
Japan
Prior art keywords
igbt
voltage
emitter
gate
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61241407A
Other languages
Japanese (ja)
Inventor
Michio Iwabori
道雄 岩堀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP61241407A priority Critical patent/JPS6395727A/en
Publication of JPS6395727A publication Critical patent/JPS6395727A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To increase the dv/dt rating by short-circuiting a latchup preventing resistor when a gete-emitter, voltage is below a prescribed value when an IGBT (Insulated Gate Bipolar Mode Transistor) is turned off. CONSTITUTION:A transistor (TR) 9a is turned on when the condition of E-Ez>=EGE exists, where E is the power supply voltage, Ez is a Zener voltage of a Zener diode 8 and EGE is a voltage of the IGBT 1 between a gate and emitter. Then a TR 9b is turned on and the latchup preventing resistor 2 is short-circuitted. Thus, even if a voltage with a large dv/dt is applied to the collector-emitter of the IGBT1, the gate-emitter voltage rise is suppressed and malfunction such as mis-turning-on or the like is prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、スイッチング用半導体素子の一種であるI
GBT (In5ulated Gate Bipol
ar modeTranslstor )素子のゲート
駆動回路、特にオフ動作中の誤動作を防止することが可
能なゲート駆動回路に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an I
GBT (In5lated Gate Bipol)
The present invention relates to a gate drive circuit for a (translator) device, and particularly to a gate drive circuit that can prevent malfunctions during off-operation.

〔従来の技術〕[Conventional technology]

IGBT素子はバイポーラトランジスタの有する高討圧
、大容量化が容易であると云う長所と、パワーMO8F
ETの有する高速なスイッチングが可能でドライブも容
易であると云う長所とを併せもつ新しいデバイスとして
最近注目されているもので、IGT、C0MFET 、
GEMFETtたはB I FETなどの商品名で各社
がそれぞれ製品化している。
IGBT elements have the advantages of bipolar transistors, such as high voltage and easy to increase capacity, and power MO8F.
Recently, it has been attracting attention as a new device that combines the advantages of ET, such as high-speed switching and easy drive, such as IGT, C0MFET,
Each company has commercialized the product under a trade name such as GEMFET or B I FET.

第4図にその等何回路を示す。すなわちjGBTはPN
P )ランジスタ11およびNPN)ランジスタ12 
ト、コ0NPN )ランジスタ12に並列接続されたM
OSFET (Nチャンネル)13と、NPN トラン
ジスタ12のベース・エミッタ間を短絡する短絡抵抗1
4とからなり、トランジスタ11.12で構成されるサ
イリスタ回路を内蔵している点が特徴である。なお、第
4A図にI GBTの回路記号を示す。
Figure 4 shows such circuits. That is, jGBT is PN
P) transistor 11 and NPN) transistor 12
M connected in parallel to transistor 12
A short-circuit resistor 1 that shorts between the base and emitter of the OSFET (N-channel) 13 and the NPN transistor 12
It is characterized by having a built-in thyristor circuit made up of transistors 11 and 12. Note that the circuit symbol of the IGBT is shown in FIG. 4A.

ところで、か\るIGBTX子は上述の如きサイリスタ
回路がターンオンし、その結果IGBTがターンオフで
きなくなると云う、いわゆるラッチアップ現象が生じ、
これはターンオン時よりもターンオフ時に生じ易いこと
が指摘されている。このラッチアップ現象はIGBT素
子の破壊に直結するので、この現象が生じないようにす
ることが必要である。
By the way, in such an IGBTX device, the thyristor circuit as described above turns on, and as a result, the IGBT cannot be turned off, which is a so-called latch-up phenomenon.
It has been pointed out that this occurs more easily at turn-off than at turn-on. Since this latch-up phenomenon is directly linked to destruction of the IGBT element, it is necessary to prevent this phenomenon from occurring.

一方、このようなIGBTのターンオフ時のラッチアッ
プ現象を抑止する方法の1つとして、従来、IGBT内
のMOSFET部のターンオフを遅くする方法が知られ
ている。これは、MOSFET部とPNP トランジス
タとを略同時にターンオフさせることにより、PNP)
ランジスタの電流急増を抑止して、ラッチアップ現象を
生じ難くするものである。
On the other hand, as one method for suppressing such a latch-up phenomenon at turn-off of an IGBT, a method is conventionally known that delays turn-off of a MOSFET section in an IGBT. This is achieved by turning off the MOSFET section and the PNP transistor almost simultaneously.
This suppresses the rapid increase in current in the transistor, making it difficult for latch-up phenomena to occur.

第5図ないし第7図はいずれもか\る原理にもとづくベ
ース駆動回路の従来例を示す回路である。
FIGS. 5 through 7 all show conventional examples of base drive circuits based on this principle.

第5図において、1はIGBT、  2はラッチアップ
防止用抵抗、3はオン用スイッチ、4はオフ用スイッチ
、5はIGBT駆動用の直流電源である。
In FIG. 5, 1 is an IGBT, 2 is a latch-up prevention resistor, 3 is an on switch, 4 is an off switch, and 5 is a DC power source for driving the IGBT.

これは、スイッチ3を閉じ、スイッチ4は開放すること
によってIGBT 1をターンオンさせる一方、スイッ
チ3を開放し、スイッチ4を閉じてターンオフさせるも
ので、ターンオフ時のゲート電荷の放電を抵抗2にて遅
らせることによりラッチアップ現象を抑制する。
This turns on the IGBT 1 by closing the switch 3 and opening the switch 4, and turns it off by opening the switch 3 and closing the switch 4. At the time of turn-off, the gate charge is discharged by the resistor 2. This delay suppresses the latch-up phenomenon.

第6図はラッチアップ防止用抵抗2とダイオード6の並
列回路をIGBT 1のゲートに直列に接続し、ターン
オンはダイオード6を介して行なうようにしたもので、
その他は第5図と同様である。
In FIG. 6, a parallel circuit of a latch-up prevention resistor 2 and a diode 6 is connected in series to the gate of the IGBT 1, and turn-on is performed via the diode 6.
Other details are the same as in FIG.

第7図は直流電源を5m、5bの正、負2系統とし、タ
ーンオン時とターンオフ時とで互いに逆極性の電圧を与
えるよりにしたものである。
In FIG. 7, the DC power supply has two positive and negative systems of 5 m and 5 b, and voltages of opposite polarity are applied at turn-on and turn-off.

〔発明が解決しよりとする問題点〕[Problems that the invention is supposed to solve]

しかしながら、上記第5 、6r!Aに示す回路ではI
GBTのコレクタ・エミッタ間に大きなdv/dt (
電圧上昇率)をもつ電圧が印加されると、新たに挿入さ
れるラッチアップ防止用抵抗によってゲート・エミッタ
間電圧が上昇し、IGBTがターンオンするおそれがあ
る。そのため、dマ/dt耐量が小さく制限され、これ
が大きくならないように運転しなければならないと云う
制約が生じる。
However, the fifth, 6r! In the circuit shown in A, I
There is a large dv/dt between the collector and emitter of GBT (
When a voltage with a voltage increase rate (voltage increase rate) is applied, the gate-emitter voltage increases due to the newly inserted latch-up prevention resistor, which may cause the IGBT to turn on. Therefore, the dma/dt tolerance is limited to a small value, and there is a constraint that the operation must be performed so that the dma/dt tolerance does not become large.

一方、上記第7図に示す回路では2つの電源が必要とな
り、大型化しコストアップになると云う問題がある。
On the other hand, the circuit shown in FIG. 7 requires two power supplies, resulting in an increase in size and cost.

したがって、この発明は1つの電源で、しかもdv/d
t耐量を大きくとることができるゲート駆動回路を提供
することを目的とする。
Therefore, this invention uses one power source and dv/d
It is an object of the present invention to provide a gate drive circuit that can have a large t tolerance.

〔問題点を解決するための手段〕[Means for solving problems]

IGBTのゲート・エミッタ間電圧を監視し、ターンオ
フ時にこの電圧が所定値以下になったときラッチアップ
用抵抗を短絡する制御回路を設ける。
A control circuit is provided that monitors the voltage between the gate and emitter of the IGBT and short-circuits the latch-up resistor when this voltage falls below a predetermined value during turn-off.

〔作用〕[Effect]

上記制御回路により、ターンオフ時にdv/dtの大き
な電圧がコレクタ・エミッタ間に印加されても、そのゲ
ート・エミッタ間の電圧が上昇しないようにし、dv/
dt耐量を大きくする。
The above control circuit prevents the voltage between the gate and emitter from rising even if a large voltage of dv/dt is applied between the collector and emitter at turn-off, and prevents the voltage between the gate and emitter from increasing.
Increase dt tolerance.

〔実施例〕〔Example〕

第1図はこの発明の実施例を示す回路図である0これは
第5図に示す回路に抵抗7、ツェナーダイオード8、P
NP トランジスタ9龜およびNPN トランジスタ9
bを付加して構成される。
FIG. 1 is a circuit diagram showing an embodiment of the present invention. This is a circuit diagram shown in FIG.
NP transistor 9 and NPN transistor 9
It is constructed by adding b.

いま、電源電圧をE1ツェナーダイオードのツェナー電
圧をEz、IGBTIのゲート・エミッタ間電圧をEo
ltとすると、トランジスタ9aはE −EZ≧EGI なる条件が成立したときオンと々る。これによ九トラン
ジスタ9bもオンとなり、ラッチアップ防止用抵抗2が
短絡される。このため、IGBTIのコレクタ・エミッ
タ間にdv/dtの大きな電圧が印加されても、ゲート
・エミッタ間の電圧上昇は抑制され、誤まってターンオ
ンする等の誤動作が防止される。
Now, the power supply voltage is E1, the Zener voltage of the Zener diode is Ez, and the gate-emitter voltage of IGBTI is Eo.
lt, the transistor 9a turns on when the condition E-EZ≧EGI is satisfied. As a result, the ninth transistor 9b is also turned on, and the latch-up prevention resistor 2 is short-circuited. Therefore, even if a large voltage dv/dt is applied between the collector and emitter of the IGBTI, the voltage rise between the gate and emitter is suppressed, and malfunctions such as erroneous turn-on are prevented.

第2図はこの発明の他の実施例を示す回路図である。こ
れは第6図と対応し、その動作原理は第1図と全く同様
なので詳細は省略する。
FIG. 2 is a circuit diagram showing another embodiment of the invention. This corresponds to FIG. 6, and its operating principle is exactly the same as that in FIG. 1, so details will be omitted.

第3図はこの発明のさらに他の実施例を示す回路図であ
る。これは、第2図のPNP )ランジスタ9aのかわ
シにPチャンネルMO8FET 10mを、またトラン
ジスタ9bのかわpKNチャンネルMO8FET 10
bを用いたものであるが、これも動作原理は第1図と全
く同様なので詳細は省略する。
FIG. 3 is a circuit diagram showing still another embodiment of the present invention. This is a PNP transistor 9a in Fig. 2. A P-channel MO8FET 10m is placed in place of the transistor 9a, and a pKN-channel MO8FET 10m is placed in place of the transistor 9b.
The operating principle is exactly the same as that in FIG. 1, so the details will be omitted.

〔発明の効果〕〔Effect of the invention〕

この発明によれば、IGBTのターンオフ時にそのゲー
ト・エミッタ間電圧が所定値以下になったら、ラッチア
ップ防止用抵抗を短絡するようKしたので、コレクタ・
エミッタ間にdv/dtの大きな電圧が印加されても誤
動作するおそれが少なくなp1シ九がってdv/dt 
it量を従来のものより大きくすることが可能となる利
点がもたらされる。
According to this invention, when the gate-emitter voltage of the IGBT falls below a predetermined value when the IGBT is turned off, the latch-up prevention resistor is short-circuited.
There is less risk of malfunction even if a large voltage of dv/dt is applied between the emitters.
The advantage is that the amount of IT can be made larger than that of the conventional method.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の実施例を示す回路図、第2図はこの
発明の他の実施例を示す回路図、第3図はこの発明のさ
らに他の実施例を示す回路図、第4図はIGBTを示す
等価回路図、第4A図はI GBTを示す回路記号図、
第5図ないし第7図はいずれもIGBT用ベース駆動回
路の従来例を示す回路図である。 符号説明 1・・・IGBT、  2・・・ラッチアップ防止用抵
抗、3゜4・・・スイッチ、s、sa、sb・・・直流
電源、6・・・ダイオード、7・・・抵抗、9m、11
・・・PNP )ランジスタ、9b、12・・・NPN
)?ンジスタ、10m・・・PチャンネルMO8IT、
 10b 、 13・・・NチャンネルMO8FET、
  14・・・短絡抵抗。 代理人 弁理士 並 木 昭 夫 代理人 弁理士 松 崎   清 第1図 第2図 第3図
FIG. 1 is a circuit diagram showing an embodiment of this invention, FIG. 2 is a circuit diagram showing another embodiment of this invention, FIG. 3 is a circuit diagram showing still another embodiment of this invention, and FIG. 4 is a circuit diagram showing another embodiment of this invention. is an equivalent circuit diagram showing an IGBT, FIG. 4A is a circuit symbol diagram showing an IGBT,
5 to 7 are circuit diagrams showing conventional examples of base drive circuits for IGBTs. Code explanation 1... IGBT, 2... Resistor for latch-up prevention, 3゜4... Switch, s, sa, sb... DC power supply, 6... Diode, 7... Resistor, 9m , 11
...PNP) transistor, 9b, 12...NPN
)? 10m...P channel MO8IT,
10b, 13...N channel MO8FET,
14...Short circuit resistance. Agent Patent Attorney Akio Namiki Agent Patent Attorney Kiyoshi Matsuzaki Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】 IGBTのターンオンまたはターンオフを行ない、ター
ンオフは少なくとも抵抗を介して行なうことによりラッ
チアップを防止するIGBTのゲート駆動回路において
、 該IGBTのゲート・エミッタ間電圧を監視しターンオ
フ時に該電圧が所定値以下になつたとき前記抵抗を短絡
する制御回路を設けてなることを特徴とするIGBTの
ゲート駆動回路。
[Claims] In an IGBT gate drive circuit that turns on or turns off an IGBT and prevents latch-up by performing turn-off via at least a resistor, the gate drive circuit monitors the gate-emitter voltage of the IGBT and detects the voltage at the time of turn-off. A gate drive circuit for an IGBT, comprising a control circuit that short-circuits the resistor when the voltage falls below a predetermined value.
JP61241407A 1986-10-13 1986-10-13 Gate driving circuit for igbt Pending JPS6395727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61241407A JPS6395727A (en) 1986-10-13 1986-10-13 Gate driving circuit for igbt

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61241407A JPS6395727A (en) 1986-10-13 1986-10-13 Gate driving circuit for igbt

Publications (1)

Publication Number Publication Date
JPS6395727A true JPS6395727A (en) 1988-04-26

Family

ID=17073826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61241407A Pending JPS6395727A (en) 1986-10-13 1986-10-13 Gate driving circuit for igbt

Country Status (1)

Country Link
JP (1) JPS6395727A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4839686A (en) * 1987-07-10 1989-06-13 Minolta Camera Kabushiki Kaisha Flash device
US5877646A (en) * 1996-03-20 1999-03-02 Abb Research Ltd Method for the turn-on regulation of an IGBT and apparatus for carrying out the method
US6009281A (en) * 1987-07-10 1999-12-28 Minolta Co., Ltd. Flash device
CN102801289A (en) * 2011-05-26 2012-11-28 三菱电机株式会社 Semicondcutor element driving circuit and semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4839686A (en) * 1987-07-10 1989-06-13 Minolta Camera Kabushiki Kaisha Flash device
US4951081A (en) * 1987-07-10 1990-08-21 Minolta Camera Kabushiki Kaisha Flash device
US5313247A (en) * 1987-07-10 1994-05-17 Minolta Camera Kabushiki Kaisha Flash device
US6009281A (en) * 1987-07-10 1999-12-28 Minolta Co., Ltd. Flash device
US5877646A (en) * 1996-03-20 1999-03-02 Abb Research Ltd Method for the turn-on regulation of an IGBT and apparatus for carrying out the method
CN102801289A (en) * 2011-05-26 2012-11-28 三菱电机株式会社 Semicondcutor element driving circuit and semiconductor device

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