JPS6395620A - Forming method for ohmic electrode - Google Patents
Forming method for ohmic electrodeInfo
- Publication number
- JPS6395620A JPS6395620A JP24168186A JP24168186A JPS6395620A JP S6395620 A JPS6395620 A JP S6395620A JP 24168186 A JP24168186 A JP 24168186A JP 24168186 A JP24168186 A JP 24168186A JP S6395620 A JPS6395620 A JP S6395620A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- photoresist
- alloy layer
- ohmic electrode
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、化合物半導体のオーミック電極形成法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for forming an ohmic electrode of a compound semiconductor.
第2図は従来のオーミック電極形成法を説明するための
断面図である。第2図において、1は半° 絶縁性の
砒化ガリウム(以下、rGaAsJという)基板、2は
能動層、3は写真製版で形成したホトレジスト、4はA
uGe層、5はNi層、6はAu層、7は熱処理後形成
された合金層である。FIG. 2 is a cross-sectional view for explaining a conventional ohmic electrode forming method. In Fig. 2, 1 is a semi-insulating gallium arsenide (hereinafter referred to as rGaAsJ) substrate, 2 is an active layer, 3 is a photoresist formed by photolithography, and 4 is an A
5 is a Ni layer, 6 is an Au layer, and 7 is an alloy layer formed after heat treatment.
次に、オーミック電極の形成法について第2図を用いて
説明する。Next, a method for forming an ohmic electrode will be explained using FIG. 2.
まずGaAs基板1上に能動層2を形成し、さらに写真
製版を施し、オーミック電極形成用のホトレジスト3を
形成する(第2図(a))。First, an active layer 2 is formed on a GaAs substrate 1, and then photolithography is applied to form a photoresist 3 for forming an ohmic electrode (FIG. 2(a)).
次に蒸着法を用いて、Au08層4.Ni層5、 Au
層6を連続的に形成する(第2図(b))。Next, using a vapor deposition method, an Au08 layer 4. Ni layer 5, Au
Layer 6 is formed continuously (FIG. 2(b)).
次にアセトンに浸漬し、レジストを除去することによっ
て、不必要な金属およびホトレジストを除去し、所望の
パターンを形成する(第2図(C))。Next, unnecessary metal and photoresist are removed by immersing in acetone and removing the resist, thereby forming a desired pattern (FIG. 2(C)).
次に、還元性雰囲気たとえばN2中または不活性ガス雰
囲気たとえばN2中で、たとえば360°C〜450°
c、 1分〜3分の熱処理を施し、合金層7を形成し
、オーミック電極を得る(第2図(d))。Next, in a reducing atmosphere such as N2 or in an inert gas atmosphere such as N2, for example at 360°C to 450°C.
c. Heat treatment is performed for 1 to 3 minutes to form an alloy layer 7 and obtain an ohmic electrode (FIG. 2(d)).
・ 〔発明が解決しようとする問題点〕従来のオーミッ
ク電極形成法は以上のように構成されているので、熱処
理によって合金化反応が進む際に最表面の金にまで影客
が及び、表面が荒れたり、ボールアップが発生したりし
て、後工程の写真製版におけるマスク化やマスクずれ、
あるいはプロセス完了後の外観不良の要因になるなどの
問題があった。・ [Problem to be solved by the invention] Since the conventional ohmic electrode forming method is configured as described above, when the alloying reaction progresses through heat treatment, the outermost gold is affected, and the surface becomes Roughness or ball-up may occur, resulting in masking or mask misalignment during post-process photolithography.
Alternatively, there is a problem that it becomes a cause of poor appearance after the process is completed.
本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、表面荒れ、ボールアップの発生
なく平坦な表面を得ることができると共に、良好なオー
ミック特性を得ることができるオーミック電極形成法を
提供することにある。The present invention has been made in view of these points, and its purpose is to be able to obtain a flat surface without surface roughness or ball-up, and to obtain good ohmic characteristics. An object of the present invention is to provide a method for forming an ohmic electrode.
このような目的を達成するために本発明は、オーミック
電極を形成する工程において、能動層を有するGaAs
基板上にNiGe合金を蒸着する工程と、360℃〜4
50℃の熱処理を還元性雰囲気又は不活性雰囲気で行な
って合金層を形成する工程と、合金層の上にAuを蒸着
する工程とを含むようにしたものである。In order to achieve such an object, the present invention uses GaAs having an active layer in the process of forming an ohmic electrode.
Step of vapor depositing NiGe alloy on the substrate and 360℃~4
This method includes a step of forming an alloy layer by performing heat treatment at 50° C. in a reducing atmosphere or an inert atmosphere, and a step of vapor depositing Au on the alloy layer.
本発明においては、最上層のAu層における表面荒れが
防止され、良好なオーミック電極が形成される。In the present invention, surface roughness in the uppermost Au layer is prevented, and a good ohmic electrode is formed.
第1図は、本発明に係わるオーミック電極形成法の一実
施例を説明するための断面図である。第1図において、
1は半絶縁性GaAs基板、2は能動層、3は写真製版
で形成した第1回目のホトレジスト(以下「第1ホトレ
ジスト」という)、4は蒸着で形成したNiGe層、5
は熱処理の合金層、6は第2回目のホトレジスト(以下
「第2ホトレジスト」という)、7は蒸着で形成したA
U層である。FIG. 1 is a cross-sectional view for explaining one embodiment of the ohmic electrode forming method according to the present invention. In Figure 1,
1 is a semi-insulating GaAs substrate, 2 is an active layer, 3 is a first photoresist formed by photolithography (hereinafter referred to as "first photoresist"), 4 is a NiGe layer formed by vapor deposition, 5
6 is the heat-treated alloy layer, 6 is the second photoresist (hereinafter referred to as "second photoresist"), and 7 is A formed by vapor deposition.
This is the U layer.
次に、本方法について第1図を用いて説明する。Next, this method will be explained using FIG. 1.
半絶縁性GaAs基板1に能動層2を形成後、写真製版
を行ない、第1ホトレジスト3を形成する(第1図(a
))。After forming an active layer 2 on a semi-insulating GaAs substrate 1, photolithography is performed to form a first photoresist 3 (see FIG. 1(a)).
)).
次に、蒸着法を用いてNiGe合金層4を蒸着する(第
1図(b))。Next, a NiGe alloy layer 4 is deposited using a vapor deposition method (FIG. 1(b)).
次に、アセトンに浸漬し、第1ホトレジスト3を溶解す
ることにより、不必要なパターンを除去し、所望のパタ
ーンを形成する(第1図(C))。Next, by dipping in acetone and dissolving the first photoresist 3, unnecessary patterns are removed and a desired pattern is formed (FIG. 1(C)).
次に、還元性雰囲気たとえばH2中または不活性ガス雰
囲気たとえばN2中で、たとえば360℃〜450℃の
熱処理を施し、合金層5を形成する(第1図(d))。Next, heat treatment is performed at, for example, 360 DEG C. to 450 DEG C. in a reducing atmosphere such as H2 or an inert gas atmosphere such as N2 to form the alloy layer 5 (FIG. 1(d)).
次に、第2ホトレジスト6を合金層5上以外に形成する
(第1図(e))。Next, a second photoresist 6 is formed on areas other than the alloy layer 5 (FIG. 1(e)).
次に、蒸着法を用いて、Au層7を合金層5上に蒸着す
る(第1図(f))。Next, an Au layer 7 is deposited on the alloy layer 5 using a vapor deposition method (FIG. 1(f)).
次に、アセトンに浸漬し、第2ホトレジスト6を除去す
ることによって、不必要なパターンを除去し、所望のオ
ーミック電極を得る(第1図(g6)。Next, unnecessary patterns are removed by immersing in acetone and removing the second photoresist 6, thereby obtaining a desired ohmic electrode (FIG. 1 (g6)).
上記の実施例では、基板1として半絶縁性GaAs基板
について説明したが、エビ層を用いたGaAs基板でも
よく、同様の効果を奏する。In the above embodiment, a semi-insulating GaAs substrate was used as the substrate 1, but a GaAs substrate using a shrimp layer may also be used, and the same effect can be obtained.
以上説明したように本発明は、合金化処理した後にAu
層を別に形成することにより、最上層のAu5の表面の
荒れを防止でき、ボールアップの発生を防止できるので
、良好なオーミック特性を得ることができると共に、後
工程の写真製版に悪影客を及ぼすことがなく、大幅な歩
留まり向上を図ることができる効果がある。As explained above, in the present invention, after alloying treatment, Au
By forming the layers separately, it is possible to prevent the surface of the top layer of Au5 from becoming rough and prevent ball-up from occurring, so it is possible to obtain good ohmic characteristics and to avoid negative effects in the photolithography process in the subsequent process. This has the effect of significantly improving yield without causing any adverse effects.
第1図は本発明に係わるオーミック電極形成法の一実施
例を説明するための断面図、第2図は従来のオーミック
電極形成法を説明するための断面図である。
■・・・GaAs基板、2・・・能動層、3・・・第1
ホトレジスト、4・・・NiGe層、5・・・合金層、
6・・・第2ホトレジスト、7・・・Au層。FIG. 1 is a sectional view for explaining an embodiment of the ohmic electrode forming method according to the present invention, and FIG. 2 is a sectional view for explaining a conventional ohmic electrode forming method. ■...GaAs substrate, 2...active layer, 3...first
Photoresist, 4... NiGe layer, 5... Alloy layer,
6... Second photoresist, 7... Au layer.
Claims (1)
る工程と、360℃〜450℃の熱処理を還元性雰囲気
又は不活性雰囲気で行なって合金層を形成する工程と、
前記合金層の上にAuを蒸着する工程とを含むことを特
徴とするオーミック電極形成法。a step of vapor depositing a NiGe alloy on a GaAs substrate having an active layer; a step of performing heat treatment at 360° C. to 450° C. in a reducing atmosphere or an inert atmosphere to form an alloy layer;
An ohmic electrode forming method comprising the step of vapor depositing Au on the alloy layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24168186A JPS6395620A (en) | 1986-10-09 | 1986-10-09 | Forming method for ohmic electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24168186A JPS6395620A (en) | 1986-10-09 | 1986-10-09 | Forming method for ohmic electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6395620A true JPS6395620A (en) | 1988-04-26 |
Family
ID=17077935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24168186A Pending JPS6395620A (en) | 1986-10-09 | 1986-10-09 | Forming method for ohmic electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6395620A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5387548A (en) * | 1992-06-22 | 1995-02-07 | Motorola, Inc. | Method of forming an etched ohmic contact |
| US5444016A (en) * | 1993-06-25 | 1995-08-22 | Abrokwah; Jonathan K. | Method of making ohmic contacts to a complementary III-V semiconductor device |
| US5606184A (en) * | 1995-05-04 | 1997-02-25 | Motorola, Inc. | Heterostructure field effect device having refractory ohmic contact directly on channel layer and method for making |
-
1986
- 1986-10-09 JP JP24168186A patent/JPS6395620A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5387548A (en) * | 1992-06-22 | 1995-02-07 | Motorola, Inc. | Method of forming an etched ohmic contact |
| US5444016A (en) * | 1993-06-25 | 1995-08-22 | Abrokwah; Jonathan K. | Method of making ohmic contacts to a complementary III-V semiconductor device |
| US5606184A (en) * | 1995-05-04 | 1997-02-25 | Motorola, Inc. | Heterostructure field effect device having refractory ohmic contact directly on channel layer and method for making |
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