JPS6395548A - Memory control system - Google Patents

Abstract

PURPOSE:To omit a bank register by providing an address space bank memory different from an address space of a CPU and transferring data to a main memory via a direct memory access DMA function. CONSTITUTION:When the contents of a bank memory 20 are transferred to a main memory 40 by a DMA, a DMA controller 42 transmits a signal BR through a control line 34e to request use of a bus of a processor 10. The processor 10 accepts the signal BR and opens a bus to transmit a signal BA to a control line 34d and to inform the controller 42 that the bus is opened. The controller 42 receives the signal BA and transmits a signal BG to a control line 34f to show the use of the bus. A decoder 58 is enabled by the signal BA; while a decoder 60 and buffers 54 and 56 are enabled by the signal BG respectively. Under such conditions, the data can be transferred between the memory 40 and the memory 20 by the controller 42. Thus a bank register can be omitted.

Description

[Detailed Description of the Invention] [Summary] A bank memory without a bank register is realized by providing a bank memory with an address space different from the address space of the CPU and moving data to the main memory using the DMAIQ function.

[Industrial application field]

The present invention relates to a memory control method for a computer system including bank memory.

[Conventional technology]

An 8-bit microcomputer is generally equipped with a memory capacity of about 64 mm, but if it is desired to further increase the capacity, the memory must be switched. Figure 4 shows a typical example, where 10 is a processor, 12.14, 16.18 are 6
The memory (RAM) has a capacity of 4. These memories are called bank memories, have the same address space, and are connected to processor 10 by a common address and data bus 34. When the processor 10 outputs a certain address to the bus 34 and accesses the memory, the address is commonly given to the memories 12, 14, 16, and 18, but only the selected memory operates to perform writing/reading.

Memory selection is done by memory selector 30 and bank register 32
This is done by

That is, when the processor 10 sets data "1" to the memory selector 30 through the bus 34, the memory selector 3
0 outputs an H (high) level signal, and the AND gate 22
, 24, 26. Open 28. Further, when the processor 10 outputs a signal specifying the memory to be selected to the bus 34 (in this example, there are 4 memories, 2-bit data), the bank register 32 receives and decodes this signal, and the memory 1
produces an output that selects one of 2, 14, . For example, if the processor 10 outputs data to select the memory 12, the bank register 32 will be
An H level is output to the top line, and an L (low) level is output to the other lines. As a result, only the AND gate 22 produces an H level output, which becomes an enable or select signal for the memory 12. . If the processor's memory access is a memory read, memory 12 reads data at the address indicated by the address signal on bus 34 and sends it to processor 10 via bus 34. The same applies when other memories are selected.

According to this bank memory method, even though the processor has 64 address spaces, the actual address space is equal to the number of bank memories.
In this example, it is expanded four times.

[Problem that the invention seeks to solve]

However, this conventional bank memory method requires a bank register 32 for selecting a bank memory. You can also select the memory chip (Memory 12.1
4. . . . may be a memory card or a single memory card, etc.), so the addresses will be the same, and if different address spaces are allowed, the circuit will become complicated. .

The present invention aims to improve these points and provide a bank memory system that does not require bank registers and may have different memory spaces.

[Means for solving problems]

As shown in FIG. 1, the present invention includes a microprocessor 0, a main memory 40 accessible by the processor,
In a memory control method for a computer system including a bank memory 20, when a processor IO accesses the bank memory 20, a direct memory access (
DMA) causes the controller 42 to transfer the contents of the bank memory 20 to the main memory 40, which is accessed by the processor 10.

[Effect]

In this way, the processor can access the bank memory by accessing the main memory, and there is no need for bank registers.

The area of main memory to which the contents of bank memory are transferred must be part of main memory, and the contents of bank memory to be transferred to main memory must also be part of the total contents of bank memory (and any part of bank memory The processor 10 instructs the DMA controller 42 where in the main memory the contents of the portion should be moved.

In this system, there is no dW in which the address space of the processor and the address space of each bank memory are the same, and the address space of the bank memory 20 only needs to be within the address space of the DMA control device 42.

Processors operate on various programs, and some programs often require certain data and other programs often require other data, so when the program to be run changes, the data needed by the program to be run next is stored in the bank memory. It is preferable to move the information to the main memory and allow the processor to access the main memory.

〔Example〕

FIG. 2 shows an embodiment of the invention. microprocessor 1
01 Main memory 40. Address data bus (including control lines) 3 connecting bank memory 20 and DMA control device 42
4 is inserted with a triste amplifier 44 and 46, which are controlled by the output of an exclusive or game (exclusive or game) 50. 5
2 is an inverter, so the buffers 44 and 46 have opposite controls. 48 is a direction register, and this output is D.
It becomes an input to the gate 50 together with the control output R/W of the MA ilJ control device 42. Since the gate 50 is an exclusive OR gate, when data "1" is set in the direction register 48, "1" and "0" of the signal R/W are inverted, and data "0" is set in the direction register 48. and “1” of signal R/W
”, “0” is output as is.

In this configuration, the processor 10 is connected to the bank memory 20
When attempting to read, give a read command "1" to the direction register 48, give the necessary parameters to the DMA control device 42 (data indicating which part of the bank memory should be transferred to which part of the main memory, etc.), to start. D
The MA control device 42 sets the signal R/W to 1" or 0", and "O" indicates a write mode and "1" indicates a read mode. Since the exclusive OR gate 50 inverts the signal R/W when the output of the direction register 48 is "1", it outputs "1" when the write mode, that is, R/W is "0", which turns on the buffer 44 and turns the buffer on. 46 off. From the processor 10 described above to the DMA control device 4
Parameter writing to 2 is performed in this state. When the writing is completed, a read cycle starts, and R/W is "1", the buffer 44 is turned off, and the buffer 46 is turned on.

The DMA control device 42 reads the contents of the bank memory 20 in this state, and then transfers the read data to the main memory 40 when the buffer 44 is turned on and the buffer 46 is turned off in a write cycle. The processor 10 then accesses the main memory 40, reads the required data, and
Write again.

When transferring data from the main memory to the bank memory, the processor 10 provides a write command "0" to the direction register 48 and also provides necessary parameters to the DMA controller 42. The DMA control device 42 receives the parameter when the R/W is "1", reads the content of the main memory 40 according to the parameter, and then writes it to the bank memory 20 when the R/W is "0".

FIG. 3 shows another embodiment of the invention. 10 like last time
is a microprocessor, 20 is a bank memory, 40 is a main memory, 42 is a DMA controller, and 34
a is an address bus, 34b is a data bus, 34c to 34
f is a signal line.

Also, 54.56 is a buffer, 58.60 is a decoder, 6
2 is the or gate.

The contents of the bank memory 20 are transferred to the main memory 4 by DMA.
0, the DMA control device 42 transfers the control line 34
It sends a signal BR through e to request the processor 10 to use the bus. When the processor 10 receives the BR multiplied signal, it releases the bus and connects the control line 34. d to notify the DMA control device 42 that the bus has been released.

When the DMA control device 42 receives the BA double signal, it transmits the control line 34f.
It sends a signal BG to indicate that the bus is to be used. Naori A.

BG is H or L to indicate whether the bus is used or not. The BA double signal disables the decoder 58 (due to the processor opening the bus), and the BG double signal disables the decoder 60 . Buffers 54,56 are enabled. In this state, data transfer between the main memory 40 and the bank memory 20 by the DMA control device 42 becomes possible.

〔Effect of the invention〕

As explained above, according to the present invention, a bank memory system that does not require bank registers can be obtained, and the address space of the bank memory is made different from the address space of the processor,
The advantage of being able to freely decide on addresses is shown here.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIGS. 2 and 3 are block diagrams showing embodiments of the present invention, and FIG. 4 is a block diagram showing a conventional example. In FIG. 1, 10 is a processor, 2o is a bank memory, and 34
is a bus, 40 is a main memory, and 42 is a DMA control device.

Claims (1)

[Claims] In a memory control method for a computer system that includes a processor, a main memory that can be accessed by the processor, and a bank memory, when the processor (10) accesses the bank memory (20), a direct memory access control device (42) is used. A memory control method characterized in that the contents of a bank memory are transferred to a main memory (40), and the main memory is accessed by a processor.