JPS6393648U - - Google Patents
Info
- Publication number
- JPS6393648U JPS6393648U JP18688486U JP18688486U JPS6393648U JP S6393648 U JPS6393648 U JP S6393648U JP 18688486 U JP18688486 U JP 18688486U JP 18688486 U JP18688486 U JP 18688486U JP S6393648 U JPS6393648 U JP S6393648U
- Authority
- JP
- Japan
- Prior art keywords
- resin
- chip
- sealing
- board
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図はこの考案の半導体装置の第１の実施例
を示す断面図、第２図はこの考案の第２の実施例
を示す平面図および断面図、第３図はこの考案の
第３の実施例の断面図、第４図はこの考案の第４
の実施例の断面図、第５図は従来の半導体装置の
断面図、第６図は固体表面における液体のぬれ性
を説明するための図である。
１…回路基板、２…半導体チツプ、３…配線用
ワイヤ、４…封止樹脂、１１…エポキシ系樹脂、
１２…シリコーン樹脂。
FIG. 1 is a sectional view showing a first embodiment of the semiconductor device of this invention, FIG. 2 is a plan view and sectional view showing a second embodiment of this invention, and FIG. 3 is a third embodiment of this invention. The sectional view of the embodiment, FIG. 4, is the fourth embodiment of this invention.
FIG. 5 is a cross-sectional view of a conventional semiconductor device, and FIG. 6 is a diagram for explaining the wettability of a liquid on a solid surface. DESCRIPTION OF SYMBOLS 1... Circuit board, 2... Semiconductor chip, 3... Wiring wire, 4... Sealing resin, 11... Epoxy resin,
12...Silicone resin.
Claims (1)
プ表面の電極を前記基板表面のリードに配線し、
その配線部および前記チツプ部を樹脂で封止する
ようにしたチツプ・オン・ボード型の半導体装置
において、 (a) 樹脂封止領域の基板表面に、封止樹脂の表
面張力が小さくなるような物質を塗布する一方、 (b) 樹脂封止領域外側の非封止領域基板表面に
、封止樹脂の表面張力が大きくなるような物質を
塗布することを特徴とする半導体装置。[Claims for Utility Model Registration] A semiconductor chip is mounted on a circuit board, and electrodes on the surface of the chip are wired to leads on the surface of the board,
In a chip-on-board type semiconductor device in which the wiring portion and the chip portion are sealed with resin, (a) there is a layer on the substrate surface in the resin-sealed region that reduces the surface tension of the sealing resin; (b) A substance that increases the surface tension of the sealing resin is applied to the surface of the substrate in the non-sealing area outside the resin sealing area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18688486U JPS6393648U (en) | 1986-12-05 | 1986-12-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18688486U JPS6393648U (en) | 1986-12-05 | 1986-12-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6393648U true JPS6393648U (en) | 1988-06-17 |
Family
ID=31136851
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18688486U Pending JPS6393648U (en) | 1986-12-05 | 1986-12-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6393648U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03209748A (en) * | 1990-01-11 | 1991-09-12 | Matsushita Electron Corp | Semiconductor device |
-
1986
- 1986-12-05 JP JP18688486U patent/JPS6393648U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03209748A (en) * | 1990-01-11 | 1991-09-12 | Matsushita Electron Corp | Semiconductor device |
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