JPS638955A - Erroneous writing preventing device to nonvolatile memory - Google Patents

Abstract

PURPOSE:To prevent the erroneous writing except the time of the access by executing an electric power source supply to a nonvolatile memory only when the access is executed to the nonvolatile memory. CONSTITUTION:When data are read from a nonvolatile memory 7, a microprocessor (CPU) 15 outputs a pulse to an output port 2P and starts a counter 2 for reading. The counter 2 for the reading, during the time (20musec) until counting-up is executed, makes an OUT terminal into H, turns on a transistor 6 and supplies the electric power source to the nonvolatile memory 7. When writing is executed to the nonvolatile memory 7, the CPU 15 generates the pulse to an output port 3P and starts the counter 2 for the reading and a counter 3 for writing. When a chip selecting signal CE is generated before the counter 2 for the reading executes the counting-up (20musec), a D-FF8 generates '1', the transistor 6 is on up to the counting-up of the counter 3 for the writing (20msec) and the electric power source is supplied.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device for preventing erroneous writing to an electrically rewritable nonvolatile memory.

[Prior art] For microcomputer systems in which a microcomputer performs advanced signal processing and configures the system with an external NRg, noise countermeasures to prevent malfunctions due to ζ noise must be taken into consideration in the design. This is one of the things that should be done.

For this reason, in addition to conventional proactive countermeasures using electromagnetic shielding, we have taken measures that require a lot of know-how, such as devising ways to route wiring on printed wiring boards, in order to prevent the above malfunctions. were being addressed.

In contrast, the present applicant has filed a patent application No. 60-116722.
No. 6, the present invention provides an erroneous write prevention device that resets the microprocessor and stops the entire system when noise is detected by a noise detection means, thereby preventing erroneous writing to a nonvolatile memory or the like.

[Problem that the invention seeks to solve]

Since the conventional erroneous write prevention device is configured as described above, each time noise is detected by the noise detection means, the computer system must be shut down in order to prevent erroneous writing to the nonvolatile memory. There were problems such as all arithmetic processing operations stopping.

This invention was made to solve the above-mentioned problems, and the effects of the above-mentioned external noise are as follows:
Rather than the microprocessor itself, it is the non-volatile memories such as random access memory and E"FROM that are connected to the data write line and memory chip selection line that carry this noise, to prevent the entire system from malfunctioning due to erroneous writes to these. Since this is important, power is supplied to the nonvolatile memory only when accessing it to prevent erroneous writing to the nonvolatile memory due to noise that enters at other times. The purpose of the present invention is to obtain a device for preventing erroneous writing to a static memory.

[Means for solving problems]

A device for preventing erroneous writing to a non-volatile memory according to the present invention includes a switching circuit between a power source and the non-volatile memory, a request for reading and writing data from the non-volatile memory is made from a microprocessor, and the microprocessor Depending on the read output, the switching circuit causes the read counter to output a read signal with a first time width, and depending on the write output, the write counter outputs a write signal with an even longer second time width along with this read signal. If a data write signal and a memory chip selection signal are input while these read signals and write signals are being output, the write signal output control circuit causes the above read signal and write signal to be output for the second time width. The configuration is such that the switching circuit is turned on to allow power to be supplied to the nonvolatile memory.

[Effect]

The switching circuit in this invention is turned on only when there is a read output from the microprocessor, a write output from the microprocessor, a data write signal, and a memory chip selection signal. To reliably prevent erroneous data writing during a period when power is not supplied to other nonvolatile memories.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is, for example, a 50Hz clock generator,
2 is a read counter, 3 is a write counter, 4 is an OR gate, 5 is a buffer amplifier, 6 is a buffer amplifier 5
7 is an electrically rewritable nonvolatile memory that is supplied with a power supply voltage (for example, +5 V) through the transistor 6, 8 is a D-type flip-flop, and 9 is a flip-flop 8. and an AND gate which inputs each output of write counter 3 and inputs the output to OR gate 4; 10.
11 is an OR gate, 12 is a microprocessor, 13 is an inverter, 14 is a negative logic AND gate that receives the data write signal WR and memory chip selection signal CE, and the output of this AND gate 14 is the PR terminal of flip-flop 8. It is now entered into 15 is a microprocessor, 16 is this microprocessor 1
5 is an address bus, and 17 is also a data bus. In this embodiment, the read counter 2 is
When the system starts operating, the CLR terminal receives a clear signal from the output port of the microprocessor 15 to initialize the count value to 0. After that, when the read output is input to the TRIG terminal, it is input to the GK terminal. It starts counting clock pulses, and outputs a pulse with a first time width of about 20 μsec from the OUT terminal. In addition, the write counter 3 receives the clear signal from the output port as CL.
When the write output is received at the R terminal, the count value is initialized to O. After this, when the write output is input to the TRIG terminal, the clock pulse input to the CK terminal is counted, and the second time width is sent to the OUT terminal. A pulse with a width of about 20 Ilsec is sent out. Furthermore, when a low-level signal for presetting is input to the PR terminal, the D-type flip-flop 8 latches the output Q to high level, and when a high-level pulse is input to the CK terminal, the rising edge of the pulse Then, the input level of the D terminal (here, low level) is latched to the output Q. That is, when a pulse is input to the CK terminal, the output Q is latched to a low level. Note that the time required to read from the nonvolatile memory 7 is approximately 10 μsec, and the time required to write is approximately 15 m5 sec, so on this premise, the above-mentioned 1. A second time width is predetermined.

Next, the operation will be explained according to the flowchart in FIG. 2 and the time charts of signals of each part of the circuit in FIGS. 3 and 4.

First, when the computer system starts operating, the microprocessor 15 sends a high-level pulse to the output port IP. As a result, a clear pulse is input to the CLR terminal of the direct read counter 2, and the output is set to 0, and a clear pulse is also input to the CLR terminal of the write counter 3 via the OR gate 10.
The output is set to 0 and each counter 2.3 is initialized (step Is).

Next, the microprocessor 15 executes other processes such as programs stored in a read-only memory (not shown) (step 23).

During this execution, it is checked whether there is a request to access the nonvolatile memory 7 (step 3S).

When there is an access request, it is determined whether the access request is to read data from the nonvolatile memory 7 or to write data to the memory 7 (step 43), and if it is a read request, the microprocessor 15 outputs the output port. Sends a high level pulse to 2P. This pulse is sent to the TRIG of the read counter 2 via the OR gate 11.
The read counter 2 starts counting clock pulses and takes about 20 μs to count up.
During ec, a high level pulse as shown in FIG. 3 is sent to the OUT terminal. This pulse is input to the base of the transistor 6 via the ORKET 4 and the puffer amplifier 5, turning it ON. Therefore, for 20 μsec,
+5cm of the power supply voltage is supplied to the nonvolatile memory 7 (step 5S). Therefore, within this time, the microprocessor 15 notifies the read request with a read signal, and sends a chip select signal C via a decoder (not shown).
A memory chip is selected by E, and data stored at a predetermined address in the nonvolatile memory 7 is read out via the address bus 16 and data bus 17 (step 6S).
. Now, the power to the non-volatile memory 7 is cut off after 20 μsec has elapsed since power was supplied (step ?S).
.

On the other hand, if it is determined in step 4S that the data is to be written to the nonvolatile memory 7, the microprocessor 15 sends a high-level pulse to the output port 3P, and also sends a high-level pulse to the TRIG terminal of the write counter 3. A high level signal is input to the TRIG terminal of the read counter 2 via the OR gate 11, and both counters 2 and 3 start timer operations. In this case, at the rise of the high-level pulse at the OUT terminal of the read counter 2, a high-level pulse is input to the CK terminal of the D-type flip-flop 8, and the output at the Q terminal thereof becomes low level. As a result, the output of the AND gate 9 is set to low level even though the output level of the OUT terminal of the write counter 2 is high level, and the output of the transistor 6 is set to low level even though the output level of the OUT terminal of the write counter 2 is high level. As shown in FIG. 3, the power is turned on for a certain period of time, and power is supplied to the nonvolatile memory 7 (step 83).

On the other hand, as described above, the microprocessor 15 sends an output to the output port 3P, turns on the transistor 6, and supplies power to the nonvolatile memory 7 for 20 μs.
The data write signal WR and chip select signal CE are sent out within ec.

If these two signals WR and CE do not arrive within 20 μsec, the negative logic AND gate 14 sends out a low-level pulse. No pulse is input, and after 20 μsec determined by read counter 2,
The power supply to the nonvolatile memory 7 is cut off.

Next, as shown in FIG. 4, the data write signal WR and chip select signal CE are sent out within the 20 μsec period (step 93).

As a result, the negative logic AND gate 14 becomes 20μ
Step 1O3 to determine whether or not it was output within sec.
), if it is within 20 μsec, the IgBJ AND gate 14 outputs a low level pulse during that time, and the D
This pulse is also input to the PR terminal of the type flip-flop, and its output Q terminal is latched at a high level. Therefore, the AND gate has a write counter output time (20 m) after a low level pulse is input to the PR terminal.
5ec) Output a medium-high level signal, or gate 4
．． A high level signal is input to the base of the transistor 6 via the buffer amplifier 5, and the transistor is turned on for 20 m5ec to supply power to the nonvolatile memory 7. Therefore, during this 20m5ec, the microprocessor 15 writes data to the nonvolatile memory 7 using the address bus 16 and the data bus 17. Then, after 20m5ec has passed, the light counter 3
Since the output returns to low level, the transistor 6 is turned off, and the supply of power to the nonvolatile memory 7 is cut off (step 11S). Note that step 105
If the negative logic AND gate 14 does not output a low level pulse for 20μsec, the 20μsec
When sec has elapsed, the power supply to the nonvolatile memory is cut off (step 12S). Then, after the processing of each step 7S, IIS, and 12S is completed, that is, when the power is cut off, the OR gate 4 outputs a low level signal to
An interrupt is applied to the microprocessor 15 to turn off the power, and the write counter 3 is reset to 0 via the inverter 13 and the OR gate 10 (
Step 13S). It should be noted that the signal states of each part of the circuit for explaining this operation are shown in FIG. 2, FIG. 3, and FIG. 4 in correspondence with each other.

In this way, power is supplied to the nonvolatile memory 7 only when it is really needed by the microprocessor 15, so that erroneous writing can almost certainly be prevented.

In addition, in FIG. 1, OR gate 11. Flip flop8. The AND gate 9 and the negative logic AND gate 14 can be omitted, and in this case, if a write signal is not transmitted to the nonvolatile memory 7 within 20 μsec after power is supplied during data writing, the power is turned off at that point. Only the function that shuts off is lost. Also, in FIG. 1, if the interrupt output circuit of OR gate 4 is omitted,
The step of interrupting the microprocessor 15 (step 13S) after turning off the power to the nonvolatile memory can be eliminated. Further, in FIG. 1, the interrupt output circuit and the OR gate 10. By omitting the inverter 13, it is possible to eliminate the function of resetting the write counter 3 when the OR gate 4 falls from a high level to a low level.

In addition, in the above embodiment, +5V is applied to the nonvolatile memory 7.
However, at this time, due to the time constant of the capacitance of the nonvolatile memory 7 itself, the voltage may not drop in a short time. Therefore, as shown in FIG. 5, an inverter 21. Resistance 22. By connecting a discharge circuit consisting of the transistor 23 between the output side of the OR gate 4 and the emitter of the transistor 6, when the transistor 6 is off, the capacitance is passed through the transistor 23 and grounded. It can be discharged. Furthermore, if the timing control shown in FIGS. 3 and 4 is performed by computer software, the counters 2, 3, flip-flop 8, etc. can be omitted.

〔Effect of the invention〕

As described above, according to the present invention, the switching circuit is closed only when accessing the nonvolatile memory to enable power supply to the nonvolatile memory. In addition to reliably preventing erroneous writing to non-volatile memory due to noise, etc., this also has the effect of effectively preventing erroneous writing to non-volatile memory due to runaway of the microprocessor due to noise.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram showing a device for preventing erroneous writing to a nonvolatile memory according to an embodiment of the present invention, FIG. 2 is a flowchart showing a process for preventing erroneous writing, and FIGS. FIG. 5 is a time chart of the signals of each part of the circuit block when reading and writing to the nonvolatile memory, and FIG. 5 is a capacitance discharge circuit diagram of the nonvolatile memory. 2 is a read counter, 3 is a write counter, 6 is a switching circuit, 7 is a nonvolatile memory, 8 is a flip-flop for the write signal output control circuit, 9 is an AND gate for the write signal output control circuit, and 14 is a negative Logic AND gate, 15 a microprocessor, 16 an address bus, and 17 a data bus. (2 others)

Claims (2)

[Claims] (1) A power supply dedicated to the nonvolatile memory, a switching circuit installed in a power supply circuit that supplies this power to the nonvolatile memory, a microprocessor that requests writing and reading of data to and from the nonvolatile memory, and this microprocessor. A read counter outputs a read signal of a first time width to turn on the switching circuit based on the read output outputted by the microprocessor; A write counter outputs a write signal having a second time width longer than the first time width together with the read signal, and a data write signal and a memory An apparatus for preventing erroneous writing to a nonvolatile memory, comprising: a write signal output control circuit that turns on the switching circuit for a period of the second time width when a chip selection signal is input. (2) The write signal output control circuit includes a D-type flip-flop that latches a high-level output signal when a data write signal and a memory chip selection signal are input, and a D-type flip-flop that latches a high-level output signal when a data write signal and a memory chip selection signal are input. 2. The device for preventing erroneous writing to a nonvolatile memory according to claim 1, further comprising an AND gate that turns on a switching circuit during a period when the output signal .