JPS6388665A - Computer bus system - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

BACKGROUND OF THE INVENTION The present invention relates to computer systems, and more particularly to bus systems used in computer systems. There are computer systems that use bus systems to route signals from a central processing unit to storage or peripheral devices and vice versa. A need exists for a bus system that allows multiple central processing units to communicate with each other and with storage devices, input/output devices, and input/output device controllers. In addition, each of several combinator systems connects several computer systems using a bus system to provide a multi-task-multi-system integrated computer system such that coordination or coordination of networks and tasks is possible. There is a need for such a bus system. OBJECTS OF THE INVENTION The present invention provides for a plurality of central processing units to communicate with each other and with storage devices,
Communication with input/output devices and input/output device controller≠
) relates to a computer bus system L, which allows connection (interface) S. Furthermore, the bus system to which the present invention is directed also provides a multi-task-multi-system integrated computer in which a plurality of computer systems can each be connected using a separate bus system according to the present invention, allowing coordination or harmonization of networks and tasks. Connect Orobus to configure, /
It is a stem. Structure of the Invention The buses according to the invention each have a 32-bit data
2 bits that can transmit a function code, 8 bits of identification information, 5 bits of parity information, 2 bits of acknowledgment code, and 4 bus capture signals. Has a route. EXAMPLES A more complete understanding of the invention may be gained by considering the following detailed description with reference to the accompanying drawings. The same reference symbols are used to represent the elements.The high performance synchronous bus system of the present invention is described below with reference to the Concurrent Computer Corporation.
Rent Computer Corporation)
rModel 328 manufactured by
The description will be made in connection with use with the 01+IPSJ computer system. Furthermore, this computer system will be
This will be referred to as the disclosed embodiment. The bus system of the present invention (hereinafter also simply referred to as S-bus) includes various modules of a computer system, such as a combicoater processing unit (cPIJ), an input/output channel (10 channels), and a storage device or memory. interconnect. In general, the S-bus consists of two separate 32-bit data paths, namely the "outgoing" (TO) path or the T-path.
- abbreviated as bus) and “return (FRQM) route” (F
Messages are transferred between modules via F-paths or F-buses. ,'r-path or T
-The bus is another bus. - From the memory (note + fI) module ``△, (to
) Transfer J address and data. The F-path or F-bus is also connected to the memory module "Irom".
)” Transfer the read data to other modules. ,
The F-path consists of (]) transmission of inter-processor messages, (
2) Direct Input/Output (I 10) Control (In this control, the input/output devices are those that operate directly under the control of the CPU and are under the control of channels, also known as DNA) (3) It is also used to send interrupts to modules other than memory. FIG. 1 is a block diagram of a system using such an S-Bus and the modules interconnected by the S-Bus. The S-bus 10 is F
1 with path 1 and T-path 2. For the purpose of simplifying the explanation, FIG. 1 shows a module using the S-bus system. The overall diagram of the phase M connection between the
The illustration of the bus controller array 11 bus capture (acquisition) circuit is omitted. F-path] and T-path 2 are connected to various modules of the processor system. CPU 102
．． 102n to 102n are connected to the S-Bus IO via a connection 4 that allows bidirectional information transfer between CP II and F-path 1. This bidirectional connection is such that F− path 1 is connected from memory module to CP +1(s)−
・In addition to data transfer, inter-bromonal messages, direct input/output (Ilo) control data transfer, and CPU
This is required for sending interrupts from the module(s) to other modules. Composite memory module explained in detail later

[(cMM
(also abbreviated as )101. 1 oin is F-path 1 and
and connections that allow only unidirectional information transfer via
It is connected to the S-bus 10 by the IA section. ,-noyo
The reason why only the Unitun direction connection is required is as follows.
be. That is, the address and data are sent via T-path 2.
is transferred to the memory module, while the memory module
Data read from the module is sent to other modules via F-path 1.
This is because the input/output (
Ilo) Channel IQs (DMA interface
) is a bidirectional emotion for F-path 1.
unidirectional information for T-route 2.
Connected to S-bus lO by a connection that only allows forwarding of information
module +06 is input/output channel I.
``Compatible'' input/output in a manner similar to Qs connections
Interface for connecting the device cliff to the S-Bus 10
It is a circuit. Here "compatible" inputs/outputs (Il
o) Equipment means the preceding computer system, i.e.
In this example, rModel BgOMPSJ is preceded by
A device that is connected to a computer system. Moji
The module 186 provides bidirectional information transfer for F-path 1.
Enable semi-directional information transfer for T-route 2 with B;
Dry ζ as much as possible. In addition, an S-bus switching circuit (abbreviated as SBS) 11
0 and 210 connect S-bus 10 to S-bus 20.
ing. SBX 110 and SBX 210 are respectively
, an S-bus with connections that allow unidirectional information transfer.
S-bus cables are connected to each route.
107, it is connected to ■. In this way,
The module connected to S-Bus 10 is S-Bus 2.
5 or dialogue with the module that is connected to 0
The j-th means to do so has been realized. The S-Bus's T-R route, Brocessor and I10 channel are used for address and data transfer.
sending the data to the memory module on T-path 2.
Memory operation starts from this point. This is the function of the T-path. Data read from either the F-path or the 7 memory module is also required.
I sent a request to the S processor and the X10 channel.
5F returned via path 1 - path l is 3, process
Also used for communication between the server and the X10 channel.
It will be done. , F-path] and T-path 2 are SO
It is equipped with 1 data line (line), and each data line is 1 bit.
Conveys information about the set. The bit represented by the data line number
As listed in F, one bus data “item
divided into four groups or fields that make up the
That's it. 1) 5-bit function field, 2) 8-bit ID field, 3) 32-bit
4) 5-bit data field, and 4) 5 bit...
This is Teefield. In addition to the 5Q data lines used for information transmission, F-
Path l and T-path 2 each have six capture lines (a
(i゛r3r3 line with two acknowledgment lines)
There is. As will be explained in detail later, the capture line for each route
The route is used to control route capture by the module 41,
and the acknowledgment line is a signal indicating receipt of the data item.
Freund interface between modules by transmitting signals.
used to control traction. 1. On communication between modules connected to the
2:y- uses 3-, /<s in the same way, and is 8 bits.
It is identified by the unit ID number (-). T-route 2
, the unit ID number is requesting
identify the module or calling module. For example, each
A module is itself a requesting unit.
When starting a memory operation to identify that
Place that unit ID number on T-path 2. memory
The module stores the unit h ID number on T-path 2.
latches the ID number in response to read data.
] r - send back. The calling module responds with
When receiving the answer, the unit ID number is recognized. The ID appearing on F-path 1 addresses the incoming module.
Specify the location. Each module uses the ID as its own ID.
Compare with and latch all messages if they match.
do. In the case of open and parallel distance measurement, the above operation in
One exception is simultaneous reporting interrupts. In this case, the caller ID is present on F-path 1. Simultaneous reporting messages are independent of whether the IDs match or not.
is accepted by all processors. However,
However, for other F-route bus data items, the address
Only the specified 111 units will respond.
, Memo 1j is referenced by Mae F: 11 address Lj.
be done. ′! 1j, memory module, 7--le is unino 1
-II) Does not have a number. Each memory mode' x
, 11+ is the modifier interval 1. α location address
Recognize 5゜S”
A module such as a processor can handle 5 bits of bus data items.
Specify the memory operation in the function field of the bus data
memory address in the 32-bit data field of the data item.
Open memory operations via the T-path by
start For data writing, the memory module
The data written to the
Sent to memory module. In case of memory read
The addressed memory module reads
The module running and requesting data via the F-path
send it back to ule. In the disclosed embodiments, from memory
4 differences for reading or writing 1 to 4 words of
Now memory can be read and written in four different ways.
be. 2. Modules such as processors and X10 channels
communicate via direct F-paths. Interprocessor mail
The message can be accessed from any processor or I10 channel.
and three data words from other specified
Transfer to module. This kind of message is (b)
Coordination of processors in multiprocessor systems, (
2) Start of I10 channel operation, and (3) ■21
To schedule and adjust tasks at the completion of 0 operations.
used. 3゜message is a single module such as a processor.
from a module to another module, such as another processor.
It can be sent for inspection. 4. Interrupts must be sent to all processors simultaneously.
can be done. This allows the operating system
can obtain lower priority treatment. Disclosure example
1. In this case, the processor uses all
Receive and respond to simultaneous notifications. In addition, simultaneous notification is F-kei.
No response is confirmed on the road. 5. Prosensor directly accesses I/CM-Yannel
;7, [can perform direct single/output operations]
Ru. 6. The multi-ff1 S-bus has two
SEX circuit, for example SBX 110 and 2 in Figure 1
10 and a system cable connector, such as the one shown in Figure 1.
interconnected using cables 107 to connect large-scale computers.
be able to form a computer system. In that case, the
Joule is a unit that uses real addresses.
Send message to other modules using D number
memory in other computer systems
can be accessed. , SBX is a remote combination
1 - route and
F-Monitor the route. In the T-path, SRX is
, Aya 1/7! (Random access memory)
Selection stored as pins 1-7 in RAM)
respond to the memory address specified. In the case of disclosed embodiments,
64KX 1-bit RAM is 4GB of S-bus
for each 64 byte block in the real address space of
It stores 4 bits. F-Route I: 8 then,
The SBX responds to the selected unit ■D number. disclosure
In the example, these unit ID numbers are H6x4 bits.
It is stored as a bitmap in the RAM of the device. Messages for remote computer systems are
Receipt 3 is confirmed by Cal SBX', - time memorized and far away.
The data is sent to the SBX at intervals. Remote SBX is a remote console
Acquire an appropriate response route to Tanstem and manage it.
Return the ji. A module that is given access to a route on the S-bus.
The module is called "mask", and the request from the mask is
;The module that responds is called a "slave." Each route
The master of T or F has one bus operation cycle during each bus operation cycle.
Bus data items can be sent. The mask is
enable that bus driver when gaining control of the bus
However, when transferring control to another module,
Disable the driver, or make it unusable. bus
Set the operating cycle to be long enough, taking into consideration the following times.
be done. a. Tarock slew (deflection time); b. Propagation delay of control 70 knob (ri rj hook force); C. Bus path drive enable/pull/disable.
Time (data propagation through the driver is from Enable 7/Disable
is also fast), d, bus route propagation and 7 I ring time, and C, bus route reception (+ ¥5 and register center / doorknob).
(f＄Bei)'l-; between. Each module has seven bus ports each receiving messages.
The data item is decoded during the cycle that follows the message with :. transfer
In the middle, logic delays are not allowed. Therefore, each
7. The module is addressed.
(b) If the address is specified, C
becomes a slave, and (2) is addressed
If not, the function code of the bus data item is
If it is “idle”, subsequent operations will not be performed.
No. The slave module handles each received bus data.
Check the parity of the item and select "Idle"
cycle parity is ignored. The slave receives each received bus data item after sending that item.
A reception response is made. In the disclosed embodiment, the received response is
, occurs two cycles after the sending of the bus data item. Immediately
This is done in the cycle after the slave decodes the information.
. In this way, the received response is in pipeline format.
Higher transmission rate! − becomes possible. however,
The mask is a "busy" reception response from the slave.
It is possible to repeat all command messages if
It is equipped with a logic circuit that enables The response line in the disclosed embodiment is an oven (open) collector.
and the acknowledgment signal is sent to all threads.
It is the logical sum of Eve's responses. Usually Yui]''l's slay
If only the block responds but there is a parity error or
In case of inappropriate system configuration, the same
A response to a message may occur. these
If one of the two modules is blocked
can treat error codes as false signals. The information carried by the acknowledgment signal is as follows:
be. AKI AKO Meaning 0 0 No response - idle cycle or module exists
Not present 0 1 Acknowledgment - Slave exists and received item 10 Busy - Slave exists but received item
11 Error - Slave detects parity error The acknowledge line is used to acknowledge reception of a bus data item.
Ginai. Therefore, an “acknowledgement” is a response that performs the requested action.
This does not mean that it can be done. In the disclosed embodiment, the slave sends a "blocked" response.
In this case, the slave's input buffer is full.
It means that. Ensure proper system operation
In order for the server to quickly empty its buffer
When the mask receives a "blocked" response, the nuclear master shall
Must abandon the bus and repeat the entire operation later
. Disclosed Examples may not be unduly confusing or non-competitive.
In order to stop the module, two consecutive "blockages"
When a response is received, the bus is held as is. Memory and other modules are
Only then, i.e. Mask is trying to create a slave.
It should be indicated that it is a "blockage" only if the Therefore, the module can accept all operations
A "positive" response should only be generated if the T-
In both the F-path and the F-path, one bit in the bus data item
The most significant bit of the address bit and function code is
It is set to ``1'' if the cycle is
In case of cycle, it is set to "0". A "failure" response indicates a hardware malfunction. As mentioned earlier, the data in the bus data items, the functions and
A parity bit accompanies the ID field. disclosure
In the example, parity bits are used to
1. Detect errors by changing the modifier. Parity pit is
Masturbation caused by J Riche Nta to slave
It will be done. Bariteich Ding Nkubi Soto passes baritibinoto
A parity error is detected if it differs from . If a slave detects a parity error, then
The rave sends a "failure" response to the mask and the bus device
data items are ignored. All operations on the S-Bus are deferred responses. child
That means Musk releases the bus after the command occurs and responds positively.
means waiting for an answer. If there is an immediate positive response
, Masks must be ordered to confirm that the order has been received.
Can be done. 17 However, the master, e.g.
The time it takes to handle non-responses due to software failures
Must have clear logic. In the disclosed embodiment, the memory operation is 25 microns.
It should be completed within seconds. Longer delays are considered a failure.
be considered. Channel: The response to the /channel I10 command is long.
Indeterminate due to mechanical delays, queuing or human interaction
may be delayed to a limited extent. The software allows you to confidently cut your time.
must be decided and implemented. Overview of Bus Acquisition and Priority The operation of the S-Bus of the present invention is based on the system clock, disclosed
In the embodiment, this is performed in synchronization with a lOMHz clock.
Ru. When a module transfers information using a route
request access to the route and grant the access.
It must be done. In other words, it has to become a mask.
No. Addresses and data are sent to one
or from mask to slave during two or more bus operation cycles.
will be forwarded to Bus assignments occur in parallel with transfers on the S-bus
. The next mask for the route is determined over each bus operation cycle.
determined. The T-route and F-route are the same, but the S-bus route
to be assigned between modules connected to it.
In this respect, they are mutually independent circuits. This circuit is
"Bus capture circuit" and "priority encoder" in each module
It consists of As will be explained later, the priority
Due to the formula, more urgent requests are prioritized over less urgent requests.
priority is given to "Bus capture circuit" and "priority code"
A combination of bus route converter circuits
Acceptable sequences are determined. Disclosure summary 1 Exclusion area direction 9-'L possession L' = atmosphere-1, position
In the backbrain of a system using a prioritized S-bus for
Each slot has a physical location number. Disclosure implementation
In the example, connect to the slot with the lower position number
The module with the highest position number
overrides modules connected to the Therefore,
Slot 0 has the highest priority level. This configuration is
, called positional preference. System using S-bus
When configuring
should be That is, the processor does not wait for the bus.
system performance degradation that would occur if
Should be placed in a low numbered slot to avoid
. 2. When the basic explanation module for location priority method issues a request to acquire a bus route,
The circuit determines the priority of this request as follows. a) High order 1 first: The bus capture circuit accepts the priority request of the lower order.
accept each bass capture request with a higher priority.
Ru. b) Rounto visit priority: Low position Scot 1-
modules, i.e. modules with high positional preference,
Has higher priority than modules in higher position slots
However, each module requests round robin priority.
one bus until all modules access it.
Routes can only be acquired for operating cycles.
. The reason for this priority method is that high-performance processors
monopolizes the bus during periods of high memory usage and has low priority.
The processor at the same time will sleep if it cannot acquire the bus.
It's my first time to put it away. Therefore, round robin priority method
According to
It will be. C) Simple priority: I10 channel usually has low priority
It works. This is because these channels contain data
is temporarily stored, and is usually stored with some delay.
This is because Nalti cannot be imposed. However, long
■ The delay exceeds the buffer capacity of 10 channels.
In that case, the operation will be abandoned. this thing
and, therefore, the resulting data loss.
■ Channel 10 has high priority for bus capture.
Generate a request. Within any priority level, position priority determines which requests come first.
Decide whether to accept it. However, the round lobby
within the module priority level, the capture request will be sent to the connected module.
You can selectively enable access to
Bullied. Bus Capture Circuit FIG. 2 shows a bus capture circuit for the disclosed embodiment. child
circuit in the system for F-path and T-path.
It is set up double. Module bus capture request circuit (
MBARC) 30 is for each module connected to the S-bus.
exists within the joule. MBARC3G has related bus capture
Did the module acquire the bus by generating a request signal?
A follow-up judgment is made as to whether or not. The priority encoding circuit 40 is part of the system backbrain.
Department. This circuit 4o is built into the backbrain.
All modules connected by
response to a bus capture request signal generated by the bus capture request signal. this circuit
4o gives which module access to the route.
Determine whether the access information should be connected to it.
distributed to all modules. A notation signal has a state indicated by its mnemonic that is ``true.''
To represent the complement signal of the signal that sometimes "acts", r-J is
Added as a suffix. Action signal Logic rlJ Logic ".yo non-operation
Logical roJ Logic “】” disclosure implementation
In the example, the signal voltage is assigned a positive true logic level.
It will be done. Logic Voltage level 1--1
2.11.1□, 11, 21. . Logic rQJ Low voltage (0,QV -'0.gV
)Logic “1” Low voltage (2,OV -5,57)
This will be explained with reference to FIG. (a) D-7 lipstick in MBARC30 70
The module 309 is equipped with MBARC3G.
in response to a “set request” signal on conductor 305 from the
generates a bus request signal RQ to request acquisition of a bus route;
. For each path, each module has one bus request signal.
number will be assigned. (b) JK7 rib/70 rib 3 in MBARC30
0g generates capture mask signals MINE and MINE-
do. When MINE is true, the module has
access is granted. The module whose route capture request was accepted
Joule is called a path mask. Each bus operation cycle
There is only one mask for each path during the
MINEJ flip-flop, i.e. flip-flop
30g is the MB of all modules that are not masks.
Must be reset within the ARC. (c) JK-7 lip-flop in MBARC3G
310 is a round robin priority route acquisition signal RREN and
Generates RREN-. (d) D-flip-flop in MBAliCH1
311 is from the module where MBARC30 is located.
In response to the “high) set y” signal on conductor 306,
Generates a previous route capture signal Hi'EN. Each flip-flop mentioned above is connected to the backplane.
[J7 signal 5C]
Triggered by LK. Next, 5CLK is
All modules through the backbrain in a way! ,
: Transferred. MBARC3o shown in Figure 2 has all the above-mentioned priorities.
Please note that the function is used. However, Mozini
Nil does not necessarily override all that is generally available.
There is no need to use the function. For example, high priority bus
For modules that do not require access,
Delete the corresponding circuit system starting with flop 311
I could do that. In each module, (a) MINE is NAND(
(b) MINE- is 1J
applied to AND302, (c) RQ is applied to NAND302
Applied to 304 and AND 3+2-1N
(d) PK'EN is NAND3113 and person'1
applied to D312, (e) RgEN- is AND312
and (f) HPEN is applied to NAND3
04 and AND314. Connected to S-bus
NAND30i304 output of all modules included.
The power is logic in the backbrain of the priority encoding circuit 40
After the sum is taken, each conductor 341-344 receives a signal KEEP.
-1REQ-5RREQ- and HREQ- are generated
. If no module has issued a bus acquisition request
, the signal on the conductor is at a high level and the other one or
indicates that two or more modules are requesting to acquire the bus.
In this case, the signal on the conductor will be at a low level. Disclosed Examples
In this case, KEEP-1IIEQ-1RREQ- and H
REQ- is an open collector signal, and line 34+-
Each of 344 is connected to a "pull-up resistor".
Ru. RREQ-1HREQ-1KEEP- and REQ- are
150 ohm 2% resistor 361.362.3 each
+5v power supply by 51 and 352 respectively (not shown)
It is terminated with These resistors and the connection to the 5v power supply are
, on a card called the S-bus termination card. This termination card is the one that connects to the backplane.
Yes, and will be explained in detail later. The open collector signal is
, is not driven at a level higher than the logic threshold, so
The rise time is determined by the RC time constant of the circuit. 5v
By using a pull-up, an open collector signal can be created.
signal rise time is improved to a level above the logical threshold
. Output from NAND303 in each module, i.e.
Logical combination output of round robin priority request signal RREQ-
is applied to AND3+2 of each module. Each moji
The output from NAND 304 in the module, i.e. the high
The combined output of the priority request signal HREQ- is A of each module.
Applied to ND 312-313. Furthermore, each module
With this in mind, the output from AND 312-3 is N0
Applied to R31S. The output from NOR315 is
Joule bus capture request signal RQn-, where n is
This is the slot number on the backplane. RQo- is applied to the bus allocation position priority circuit 316.
Ru. This circuit 316, in the disclosed embodiment, is
3g1 does not indicate continuous optical encoder and decoder or decoder.
382. Bus capture request signal RQ
n- acts at a low level, and circuit 4 G +, : set
8 is 1000 ohms in the disclosed embodiment.
The pull-up resistor 371 connects the request line of the vacant slot.
The path remains dormant. Therefore, in the disclosed embodiments
, leave unused request lines unconnected.
be able to. The bus capture request signal RQ++ is generated by the circuit shown in FIG.
It is calculated to be equivalent to the following equation. RQn = (RQ book 11PEN) High priority (AND
314) + (RQ*RREN0HREQ-) round
Drobin, but not prohibited (AND313)
+ (RQoRREQ-[REQ-*RREN-) simple
, but not prohibited (LD312) position priority mark
Encoder 316 provides one S-Bus slot for each S-Bus slot.
has an input, namely RQn~, and one output GRn-
. Position priority encoder 316 assigns the highest priority to
Modules whose requests have not yet been implemented
is determined, and the next
Control that allows the path to the module in the cycle
Plan. All other Mogicool “bus route allowed” signals
remains inactive, i.e. at a high level, and therefore
other modules must wait. In Figure 2
As shown, the bus path tolerance for each slot is
” signal GR++- is connected to the corresponding module via conductor 391.
routed back to the bus for the next cycle of bus operation.
indicates whether it has been acquired or not. In the disclosed examples
The number of slots to be used is 22, so the encoder 3g1 has
Three R74F14J priority encoder priority grooves are configured and decoded
The device 382 consists of three r74FI3J decoders.
ing. Furthermore, each RQn- signal is
plus the IK ohm from pull-up resistor 371
Each GR11-
can drive a current of 2On+A at 0.4 volts.
Wear. Additionally, generated by the logical combination from IIAND302,
REQ-aligned NAND Logical conclusion of output of 3112
KEEP- generated by the
to switch the route to another module or
C+tR3' for the module being accessed.
used for. Certain actions require 2 to complete them.
Some require more than one bus operation cycle, so
Access to a route for more than one bus operation cycle
There is a module that needs to hold the status.1. obtain
. For example, some memory reads L7 in the disclosed embodiments
or the write requires two or more operation cycles.
. When a module that consists of a route gains access to a route, the module
Joule is the output from JK-clip flop 303
6 modules that set the signal MINE with
If you want to maintain the route during the running cycle,
The module sets the “additional data” signal on 4 units 382.
L7, this signal is NAND 311st with MINE
Please apply. The output of NAND 301 is
are logically combined in the signal to form the signal KEEP-.
The signal is applied to NAND 321. Requires bus route acquisition
NANo to which the desired RQ and MINE- are applied
The outputs of 302 are logically combined in the backbrain and output as a signal.
The signal REQ- is generated. This signal REQ- is inverted by inverter 320 and KE
Applied to NAND 321 along with EP-. NAN
The signal PASS-, which is the output of
"Allow" signal is applied to NOR 385 along with the "G" signal. PASS- is also sent to NOR06 along with the output of N0R385.
applied. The “Additional Data” signal on conductor 338 is set.
When activated and MINE is set, the module:
The “Bus Path Allowed” signal to other modules is active.
route control regardless of the situation.
will be put on hold. Therefore, in summary, to capture each route of the bus,
The following signals are provided by the module in relation to the backplane.
is generated. Note that the prefix of the signal is T-path or F
- Indicates that the signal is generated for route capture.
vinegar. Bus capture signals TRQa-FRQn - Bus route capture request signals (each module
one signal per route per module)
one signal per path) TKEEP-FKEEP-Buffer for next cycle signal
Bus path maintenance signal Combined output of signals from each module (in the disclosed embodiment, combined output of signals from open collectors) TIiEO-FREQ-Bus path request signal from each module
Combined output of signals from (in the disclosed legend, Yukura output of signals from the open collector) TRREQ-FRi! EQ - Round Robin Request Signal
Combined output from each module (combined output of signals from the oven reflector in the disclosed embodiment) TIIREQ-FliREQ-High priority request signal name module
Step 1: The module is not assigned a bus.
Requesting bus acquisition. MIME has no effect and is therefore equal to '0' and
Old ME- is equal to "1". (a) RQ output from clip 70 tube 309
by setting it to the active state, i.e. to “1”.
A legitimate priority request is generated. Therefore, Ge l-3
The signal REQ- which is the output of 02 is "0, that is, the operating state.
becomes. REQ -RQ*MINE- (b)) Set RQ from flip-flop 309 to "1"
In addition to setting the flip-flop 310
By setting RREN from
A round robin request is generated for the RREO= RQ*RREN (e) RQ from flip-flop 309 is active
In addition to setting a high priority request on the bus
acts on HPEN from flip-flop 311.
It is generated by setting the state. 111iEQ = RQ book HPEN 112EQ has higher priority than RREN,
However, both have higher priority than other "simple" requirements.
There is. These signals are used by modules with low priority.
It works by inhibiting and delaying requests from the tool. When I(REQ becomes active, only high-priority requests are activated.
enabled. When RREN is activated, a simple
requests are disabled. "Round robin" control line
RREN allows processors to share the bus equally.
The processor typically
Request the first operation with REQ and RREN. This gives priority over simple requests. Iku
Some processors have requests that have not yet been fulfilled.
, R until each processor gets one operation.
REN remains active. RREQ is active
The only processor that requests a second cycle in between is REQ.
must be carried out. This is a low priority request.
Ru. When RREQ becomes inactive, all processors
and RREQ can be used. memory module
Now, we use RREQ to share F-paths equally.
do. Processor: 1l for messages and direct input/output
REQ should be used. Step 2: If the module has a bus and the next
If it is desired to hold the bus for all cycles, MINE is set to active state, ie, "1". If the operation requires more than one bus operation cycle,
, the "Additional Data" signal is asserted. Immediately
It is set to "1". KEEP MINE The master of this additional data path, i.e. the module with MINE = 1.
A call is an operation that requires two or more cycles.
Maintain medium KEEP. This allows the bus to be
is prevented from being lost. However, KEEP
, shall not be used to hold the bus for the purpose of continued operation.
No. KEEP is an idle cycle in any operation.
and must be inactive during the last cycle
. 7. Step 3: KEEP handing over the bus to the new mask
In the inactive state, it is equivalent to "0". Is this module
REQ is inactive and equivalent to "O". said
The reason is that RQ is equal to "0" in the inactive state and REQ
This is because = RQ*MINE-. But long
However, some other modules may also request the bus.
Yes, and i! EQ is the REQ signal from all boards.
Since it is a combined output of signals, REQ for this bus cannot be created.
It is equivalent to the active state, that is, "1". Therefore, PASS is
In the active state, it is equivalent to "]J. PASS = KEEP - this REQ so that the bus is lost and M I l?
set to the state. LOSEBUS= PASS*GRn - GRn here
- is equivalent to the non-active state, ie "1". That is to say
, because this module did not issue any bus requests.
, so no bus allocation is done. unless there are other requirements
, it was noted that this module does not lose the bus
stomach. This means that REQ is then inactive, i.e.
0” and therefore PASS is equivalent to “O”.
This is for the purpose of Step 4: Acquisition of the bus PASS is equal to the active state, ie "1". say
It's KEE! ' is inactive and therefore KEEP
This is because - is equivalent to "1". REQ is the action state
is equivalent to rlJ, so PASS is in the active state,
That is, it is equivalent to "1". In addition, GRn- has a mode of action
state, ie, "0". This is because the bus is
Can it be given to a unit or module?
It is et al. GETBUS = P person SS * GRn GETBUS is flipped so that MINE is in active state.
Set the flop 308 and clip 70
Set 310 so that RREN is active. Overview of Open Collector Bus Signals In the disclosed embodiment, each of the two bus paths has six
Uses an open collector signal. Four of these beliefs
One number is used for capture control and two are used for acknowledgment.
It will be done. Each capture control signal requests a bus route.
is driven by each module. Each module
The outputs from are OR-combined. That is, the signal is
If the output of that board is active, it will be at a low level.
Becomes active state. The acknowledge signal is typically sent by the slave.
is driven only. However, due to parity errors or improper configuration,
It is possible that some modules respond immediately. 4 as constant response signals TAKI, TAKO, FAKI, FAK
O and capture control signal KEEPSFKEEP, TRE
Q and I'R1: The line transmitting Q is
5 at 150 ohms with the S-Bus termination card on the
It is terminated with v. When standing with a 5V pull amplifier
The interval is improved to exceed a logical threshold. faircha
ILDO Camera and Impedance Corporation
Digital Product Division (hereinafter referred to as
r74F available from Fairchild (abbreviated as Fairchild)
A typical logic threshold for a J logic device is, for example:
It is 1.6■. These lines have a bus impedance
It is not necessary to match exactly to 0, 0 by the diode,
Negative overshoot with clamp to 6v (not shown)
is reduced. Bus capture signals TRREQ, FRREQSTHREQ and
In order to achieve a high-speed rise, 1
A 20 ohm 6 2% pull-up resistor is used.
. Additionally, a priority encoder 316 and a “Fairchild 7
4F64J For driving input to NOR gate 315
is fast enough to overcome the extra delay introduced by
“Fairchild 71F3” is used to drive these signals.
8J Buff Agate is required. Figure 3 shows the S-bus
Termination car for backplane 29 and T-path 2
A portion of the card 50 is shown. The input and output signals to the backbrain 29 are as follows:
It is collectively indicated by the number 1717. For convenience of explanation,
The module installed in front O of block brain 29
We will focus on the modes of the rules. backplane
The 32 bins on 29 contain 32 T-path data signals T
:lI:00 is input. All bottles are shown in Figure 3.
It is typically represented by the bin Sol. T-route 2
Bin 5 G + +: On the backplane 29 to be connected
The 32 lines are represented by line 601 in Figure 3.
is represented by &'1M6H.
Each of the 32 lines was terminated with a 150 ohm resistor.
All resistors are shown in Figure 3.
A resistor 651 is representatively shown. The resistor 651 is
, the +3 volt power supply provided on the termination card 50 (Fig.
(not shown). Similarly, the T-path signal
TFN4:O,, TID7:O and TPAR4:050
are input into the pins represented by pins 502-504, respectively.
Connect T-path 2 to bins 502-504
Each of the lines 602-604, respectively,
It is. Each line represented by lines 602-604 is
150 ohm resistor represented by resistor 652-68
These resistors are each terminated by +3
Volt power supply (not shown). Additionally, six oven lifter signals TAKI:01TK
EEP-, TREQ-1TRREQ- and THREQ-
are respectively in the bins represented by bins 5O5-509.
Applied as an input signal. T-r road 2 to bin 505
The lines on the bank plane 29 that connect to each of the to 509
The roads are represented by lines 605 to 6hi9, respectively. Each of the lines 605-609 is connected to a respective resistor 655.
-659 made by a 150 ohm resistor.
It has been cut off. Each of resistors 655-659 is connected to a termination cap.
connected to a +5 volt power supply (not shown) on board 29.
There is. Bus route capture request signal TRQn from module board
- is applied as an input to bin 515 and the termination voltage
1000 ohm pull-up resistor (shown) on board 50.
(without). TRQn-(ii't is priority) from all modules
It is input to an encoder or encoder 3g+. The output from priority decoder or decoder 382 is TGR
Applied to the module board as an n- signal. this
This means that in Fig. 3, taking the thrower l-0 as an example,
The connection between the output of the first decoder 382 and pin 511
Examples are given below. The circuit 50 shown in FIG.
A portion of the edge card is shown. This termination card is
a suitable pull-up resistor for the
We are prepared. Furthermore, as will be described later in connection with FIG.
This termination card is the clock that is distributed to the clock distribution board.
It is equipped with a circuit for generating a lock signal. Also shown in FIG. 3 are a clock distribution board 55 and a module.
interface via the backplane between
(The clock distribution board 55
role of distributing network signals to modules). Figure 3
The clock signals 03C- and CLK
- are respectively on the module board of slot O.
Distributed to pins 493 and 499. S-bus clock bus timing is 10.00 megahertz (MHz)
is synchronized with the timing signal of clock 5CLK.
Ru. 5CLK is radial on the S-bus backplane.
from two timing signals distributed to each module.
This is a clock generated at these two taiimi
The ringing signal is 20. OQMHx oscillator clock signal 0
5C- and 2. (b00MHz oscillator clock signal CL
It is K-. To explain in more detail, in the disclosure legend
(b) O3C- has a jitter of less than 2 nanoseconds
50%±lθ% due to the 50 nanosecond period and the output voltage.
It has a cycle (impact coefficient) of 20.00
±0.001%) megahertz (MH) oscillator,
and (2) CLK- is one every 500 nanoseconds.
Derived from 05C-, which acts for an O3C period (50 nanoseconds)
This is a 2,00MHz signal. In the disclosed embodiment, the timing of the bus is
Falling edge of 05C- or rising edge of 05C- on lane
It is inaccurate because it is based on the edge of the
It should not be used for service operations. between individual clock signals
timing defined as the difference in timing between
The slew should be minimized between 03C- and 5CLK.
. Clock Distribution All S-Bus timing is controlled by a single 20MHz clock.
Generated from a Listal oscillator. The output of this oscillator is
radiated to each board on the S-bus by the termination card.
distributed as follows. This clock distribution is shown in FIG. All signals are at backbrain bin 49g.
The falling edge of 05C- is used as a reference. Place of disclosure example
In this case, the board-to-board throughput within the chassis is ±6 degrees.
It is preferable that the time be less than 100 seconds, and ±
Preferably, the time is 10 nanoseconds or less. In the disclosed embodiment, the S-bus termination card 5G is provided with
The oscillator 401 connected to the coaxial cable and the 4-bin
A connector is used to supply the clock to the chassis. oscillation
The device 401 is also connected to the second chassis via a coaxial cable.
Supply clock. To minimize throughput,
The electrical lengths of the bulls should be equal. The signal osc, which is the output from the oscillator 401, is, for example,
Texas Instruments r74Aslo00”
It is inverted by an inverter 420 consisting of a buffer.
Generates 05C-. This 05C- is then "divisor -2
It is applied to the j frequency divider circuit 403. “Divisor-2” frequency divider circuit
One output of 403 is, for example, Fairchild's
r74F163 type presettable synchronous binary counter
Apply "divisor - 5" to the frequency divider circuit 404.
2 MHx signal C1, along with NANl142+
- is generated. This signal CLK- is output every 100 nanoseconds.
Consisting of 50 nanosecond pulses appearing one at a time, 100
Synchronize the S-Bus with nanosecond cycles (IGM!IZ)
used for. NAIJD421 requires CLK-
One for each chassis. Signal O5C is, for example, Texas Instruments'
Input that can be r71AsI000J buffer
It is inverted by inverter 40g to generate 05c-. Signals CLK- and osc- are routed through coaxial cable 467.
is applied to the clock distribution board 55. Clock 05C- is clocked by buffer 41G.
received on the distribution board 55, while the buffer 7a+1oc,
/<Drive sofa il+. for buffer 411
One incoming end is grounded and the inverter 4o9, e.g.
For example, Fairchild's r74FO4J hex inverter
is inverted via the data. This allows the module board to
The board is inserted into the slot driven by buffer 411.
Even when not plugged in, electromagnetic interference is reduced. Buffer 411 receives signal 03C applied to bin 498.
- drives one module board. Therefore, the bar
Buffer 411 is represented by buffer 412, for example.
Repeat for each module board driven, as in
provided. Clock CLK-, along with the output of buffer 410,
JK-Flip Flop 4 on Lock Distribution Board 5s
77. JK-Flip-flop 477?
For example, the output of Texas Instruments r7
Buffer that can be 4AsI000J buffer
Temporarily stored on day 3. The buffers 413 are
CLK applied to bins 49g, 469 and 479
- to drive the three module boards. therefore
, buffer 413 is represented by buffer 414, for example.
Repeat for each 3 module board that is driven as follows:
provided. In the disclosed embodiment, the trace consists of six
smaller than a single inch and unterminated. In the disclosed embodiments, each S-bus module board
Like the module board 89, the
The stub length of the race imposes a load of "74F" on CLK-.
obtain. Each S-Bus module port
Terminated with a 100 ohm resistor, similar to the LePort 89.
up to 5 trace stub lengths up to 10 inches
A 74F load of 74F may be applied to O5C~. backplane 2
9 signals 03C- are provided on the module board 89.
The back shake is reversed by the inverter 450
JK-flip flip along with signal CLK- from zone 29.
Rip 406 (or JK-7 rip 70 nbu etc.
(logic element) which operates on line 4.
91 and 492 have module rotor signal 5CLK.
and 5CLK- are generated. Transfer of Information Using the S-Bus Notation Signals use uppercase letters to identify individual signals within a field.
It is represented by a mnemonic symbol consisting of a number of suffixes. fee
A field is written with a colon along with its bit range.
. That is, T31:Go is a 32-bit signal T31 to T
Represents oo. Most significant bit comes first. is a suffix
The minus sign indicates that the condition indicated by the mnemonic is "true"
represents the complement of the signal that is in the "active" state if . One "word" is 32 bits wide, and a "half word"
is 16 bins 1 - medium irises, and "baite" is 8 bins
width, and a "nibble" is a 4-bit bucket. binary
Values are expressed in hexadecimal notation, so each nibble ranges from 0 to
has a value of up to 9 or A(-+o) to F(-15)
. The notation “act number 2” indicates the number of bits in the field.
l This is used. Therefore, T31 is the data field
TFN4 is the most significant bit in the function field.
TID7 is the most significant bit in the ID field.
and so on. Bit “0”
is the least significant bit in the field. weight of each bit
"n" is "two JJ", that is, it is the left number of "2". However, bytes and half words are "left to right"
numbered. That is, byte “0” is the most significant byte.
There is a door, and byte 3 is the least significant byte. Signal Definitions T-path and F-path signals are equivalent. All T-kei
The F-path signals have the prefix "T" and all F-path signals have the prefix "T" and all F-path signals have the prefix "T".
11”J prefix. T31:0Q-F31:00- 32-bit data
Field TFN4:0-FFN4:Q-5 bit machine
function selection signal TID7:0-FID7:O-8 bit unit
Parity bit TPARI-FPAR4-ID and function field of knit identification number message
For even parity bits TPAR3-FPAR3-data bits! at 1:24
For even parity bits TPAR2-FI'AR2-delta bits 23:16
For even parity bits TPARI-Ff'Al1- data bits 15:8
For even parity bits TPARQ-FPARQ-data bits 07:00
Definition of code for even parity bit function field On T-path and F-path, 5-bit function field
identifies the data present on the path during each cycle.
do. For memory writes or input/output writes,
A data cycle must immediately follow an address cycle.
Must be. Like memory read and input/output read
Other data cycles are separate cycles. Function "0" represents an idle cycle in which no transfer occurs. pa
Other fields containing properties are ignored. the result,
The mask drives the function code to zero during idle cycles. Other fields do not need to be driven. T-Path Function Field Code T-Path is used simply to initiate a memory operation.
1 degree FNI with no error is for address cycle
is "1" for data, and "0" for data
be. For disclosed embodiments, TFNI: 0 abbreviated
Symbol Operation 00 000 (b01DL
Idle pass cycle 0f-03 years old (reservation) ...Data... 04 001HDWO Data word ending with byte 0
O5at) 101 DWI Ends with byte 1
Data word 06 0'0110 DW2
Data ending in byte 2 Word 07 001
11 DW3 Data word ending with byte 3
Code 08-OF Book (Reservation)...
Read... IQ 1flOHMRI Memory read = 1
Word 10 10001 MR2 memory read
:2 words 12 10010 MR3 memory read
Output: 2 words 13 10HI MR4 memory
Read: 17-D...Write... 10100 MWI Memory write
:I word +5 10101 MW2
Memory write: 27-de 16 +011θ M
W3 Memory write: 3 words 17 +01
11 MW4 Memory write = 4 words
...Special...H11000MFIS Memory reading and setting
19 1100! MIi memory
Read and reset +A 11010 MR
I Memory read and increment IB
11011 MRD Memory read and
IC11100MIIW Memory extension and decrement (decrement)
Code write ID 11101 MWD
Memory write diagnosis IE-IF 1 piece
(Reserved) F-Path Function Field Code F-Path is used for reading data from memory, direct input/output, and
Used for communication interrupts and messages between units. Four "return communication" functions are received by all units.
The other side is memory read data, direct input/output.
and four “message” functions are provided by FID7:O.
decrypted only by units addressed by
FFN4: 0 Simple symbol Operation G
o 00000 1DL Idle Bus Sai
Cruise □ ... Direct input/output response ... 01 00001 ATN Attention
Interrupt (compatible +10 interrupt line) 02 uuo! OK I 10 received
Confirmation, data 0K03 0HII IERI1
0 reception confirmation, data error... memory response... 04 00100 MDCO memory read, word
O50f11OI MDCI memory read
, word 11 cache unavailable 06 00 HOMDC2 memory read, word 2, cache unavailable
Cache unavailable 07 00111 MDC3 memory read, word
code 3, cache unavailable 08 011100 MOKO, ' Read memory
, word 01 data is correct 09 0+001 , lOK+ memory
Read, word 1, data is proper OA 01010 MOK2 Memory read
output, word 2, data is correct QB 01011 MOK3 memory read
Output, word 3, data is correct QC01100 MERQ memory read, word 01 data
Data is error〇D HIOI MERI Memory read
but word 1, data is error OE 01110 MER2 memory read, word
Word 2, data is error OF 011+1 MER3 memory read, word
Code 3, data is error... Direct input/output... 10 10000 10R input/output read++
10001 ne (reservation) +2 10
010 IOW Input/output write +3 1
00+1 FDAT F-route data is 10
Follow W or MSGΩ...simultaneous notification...H10100PRE r pre-emption' broadcast communication interrupt +
5 +0101 DVA rvirtual address
Broadcast communication interrupt 16 +0110 3YNCr real-time clock start
17 10111 * (Reservation)
Broadcast communication interrupt...Message...18 11000 MSGO message 019
11001 MSGI Message IIA
11010 MSG2 Message 2
1B 11011 MSG3 Message
3IC-IF Ne (Reservation) 1
0W and FIIAT must be sent as a pair of consecutive items.
Each MSGn must be followed by two FDAT entries.
However, other items can be sent alone. 10K and IER are responses to IOR and tOW commands.
That's the answer. M OK o, M E Ra and 1JDcn
This is a response to a memory read operation. Multiple word read
Responses to motion usually occur in successive cycles
However, this is not required. In response 10, to IE, MOK, MI4 and MDC
, to confirm completion of direct input/output or memory operations
Send one item to. All direct l10 (input/output)
confirmed and this is communicated to the handling process.
Ru. In the IOR, the read data is returned with F31:Go.
It will be done. Memory reads are returned in F31:QO
Confirmed by data. Farad words Each word read from memory is M
OK, sent to VER or MIIC for individual confirmation
be done. The memory module stores all 4 words.
However, the bus can be held. In the case of a memory write, there is no response on the F-path. Immediately
The processor does not wait. Electrical Specifications Four types of signals are used in the S-bus. I already mentioned it
In other words, logic signals are generated by circuits provided in the backbrain.
0SC-1CLK-1TGRn-1FGRn- and
or as TRQn-1FRQn-
Received. Bus signals are sent to all modules via the S-Bus.
supply to the module board. Bus line with backbrain
path is terminated, but the backbrain has sent a signal
It will not be sent or received. S-Bus logic signal 1, 05C- and CLK-Tlock are assigned to each module.
distributed radially. 2. Bus request signals TRQn- and FRQn- are sent to each module.
is generated on the control board, and in the disclosed embodiment,
These signals are "Fairchild 74F" logic signals.
be. 3. Bus permission signals TRGn- and FGRo- are S-bus
Generated on the backbrain and on each module board
J″L. In the disclosed embodiment, these signals
is the "Fairchild 74F" logic signal. S-bus signal 1.3 status bus signal T3]:0O-1TFIJ4:0-1TID7:fl-
1TPAR5:IJ-F31:611-1FFN4:G
-1FID720-1FPAR5: D-2, open
Collector bus control signal TKEEP-1 REQ-1T
RREQ-1TFiREQ-1TAXI:0-TKEE
P-1T father EQ-1TRREQ-1THREQ-1TA
KI:O - In the disclosed embodiments, the logic used is:
Conforms to Fairchild OF logic levels and loads. Bus line receiver: Input height > 2.0 volts [-1H < 0.04 mA Input low 0.8 volts I-IL < 0.6 mA Bus line Driver output height > 2.7 volts 1mA output voltage low 0.
5 volts, but the F-path and T-path are each 50 mA, such as the 30 mA 3-state path.
A three-state path signal is used. These bus signals are 10
The current bus path is synchronized with 5CLK with a 0 nanosecond cycle.
It is driven by a module that serves as a mask. Open
In the illustrated embodiment, these three-state path signals are
Preferably, it is driven and received by a G-type register. Each space
The Reig receives the bus signal during each bus operation cycle and
decipher that address or IJ]. Disclosure Example 1. Second, please wear a mask if it is on the bus route.
During each bus operation cycle, the T-path is masked by
In the case of the functional signal line T F N, also the F-path
In this case, the functional signal line FFN must be driven.
. If the module does not use the bus path, then
Joule drives the function code to "0", immediately high level.
(Must be pulled. The tracks for other fields are
Save power j second 17 high [~ float with bell
be able to. This is because the bus termination
This is because a considerable amount of power is consumed for each number. 3
State signal line stand' Nili is slow and runo, to high level
floating is very slow and cannot guarantee a sufficiently high logic level.
I can't do seven. Therefore other fields are ignored6
The three-state signal as shown in FIG.
terminated at 3 volts on the S-Bus termination card with a resistor of
do. A series bar is connected to the terminal that produces 3 volts on the termination card.
A voltage regulator (not shown) is used. This termination car
has an AC response similar to a split resistor termination device.
However, almost no power is applied to non-active (high level) Ig.
Don't consume. T-path or F-path for the resistor shown in FIG.
The termination power of the path is as follows: 50 three-state bus lines
Road main 20mA = 1000 (G, large), 50
0 (average) 2 high speed opening rolerectors main 35mA =
70 35 i.e. RREQ- and HREQ- 4 slow opening rolerectors Main 22mA = 90
'45 i.e. KEEP-1REQ- and AKI:
0 total + 16 (b (maximum), 589 (average), and termination
Clamp with diode to 0.6 volts on card 50
open collector signal by
Negative fluctuations are reduced. Bus terminated at one end only
be done. This is because when terminating at two ends, the
A large drive voltage is required, and as a result, a considerably large current is required.
This is because power is required. Signal edge is absorbed at the termination
However, it is reflected at the far end. Therefore, bus timing
20 nanoseconds (>2 nanoseconds) for settling.
/ft x 1.5 feet L x 4) is not taken into account.
It won't happen. Therefore, the bus timing is determined as follows.
It will be done. 5CLK delay for disabled drivers: typically 15
Nanoseconds Disabled J-Driver Delay to SC[, Max.
25 ns delay of 5CLK for enabled driver; typically 39
SCI, K delay for nanosecond enabled drivers: up to 45 nanoseconds bus set-up
Tring time: up to 20 nanosecond passes
Setup time: up to 25 nanoseconds
Skew of stock: Maximum lO nanoseconds
A total of 10 (l nanoseconds) three-state driver is clearer and faster than the open collector case.
Guaranteed switching speed of 4. However, two
When opposite drivers of
Opening/closing occurs with significant noise. driver is suitable
Short overlaps of several nanoseconds can occur if the separation is very strong.
top is acceptable. Each driver has an adjacent 0.1 μF
An isolation capacitor should be provided. There is an overlap
This increases system noise, but avoids disconnecting high-capacity buses.
When switching, a comparable current spike occurs. deer
However, a sustained overlap greater than 5 nanoseconds
must be avoided. Each module board has a bus
10 ns bus enable vs. disable
Must reduce three-state contention by delaying
do not have. Position Priority Signal As already mentioned, the encoder in Figures 2 and 3
Each position-first encoder, such as encoder 316
for each path for each S-Bus module slot.
At clock 17, one input, i.e., TRQn- or FRQn-
and one output, namely TGRn- or FGRn-.
do. In the disclosed embodiments, as described above, each
The encoding circuit or encoder 316 consists of three 7-wire circuits.
Child 74F1411 type priority encoder or encoder
Coda and three Fairchair Redo 74F138 type decos
It is equipped with a card. Maximum delay of RQ11- to GRn
is 20.5 nanoseconds. Each RQn- signal has one frame.
Airchild 74F Unisol l-1 For example, N0 in Figure 2
li31S with a 1k ohm pull-up resistor, e.g.
Provide the input load by adding the resistor shown in Figure 2. 1 km
Ohm pull-up resistors connect unused inputs to
It is maintained at the working state of high 1 to bell. Therefore, the board
When inserting or removing the
No switching is required. The timing of the bus route capture request and bus route permission signal is
It is given as follows. 5CLK delay for RREQ-, HREQ-: 15
Nanosecond (maximum) settling time = 3
RREQ-, HRE for 0 nanoseconds (maximum) RQn-
Delay of Q-: lO nanoseconds (max) RQ for GRn-
Delay of n: 20 nanoseconds (c゛dog) G to LCLK
Rn - Settling time = 15 nanoseconds (maximum) clock
Skew: lO nanoseconds (maximum) total
100 nanosecond bus capacity bus connections have high distribution capacity. This capacitance is
affects signal transmission by reducing impedance.
In addition, the opening [・Increase the rise time of the lid signal. Multiplex wiring per board 3pF/inch x 3inch 1oI
IFX 1.5 inch/59F input
74F-SpF, 74F/SpF output
74F・59F. 74F3g・1fl
pF connector, bottle, etc. ・SpF,
Total 2SpF per SpF board,
25pF 22 boards total ・
5SOpF, 5SOpF backplane
Multiplexed 12pF/inch Xl fin, 35pl' per line
Total of 58SpF 58Sp
F Hold Time During one bus operation cycle, the data is at the source.
Transferred from register to incoming register. cycle time
(nominally 100 nanoseconds) is the worst case delay and required
Determined by setup time. In fact, the cycle
10 (b-10・90 nanoseconds due to clock skew)
It is shortened to . Bold time indicates that the tarokk skew is on the minimum delay path.
Since they are comparable, they are even more difficult to set. extra timing
It is desirable to keep a margin. The input register is
Clocked every cycle. The output clock is gated
and may have extra gate delay. Clock skew osc- is distributed radially to each board in the system
. 05C- is a nominal 50% duty cycle d2l
0% or 5 nanoseconds. High level period and low level
The bell period varies between nominally 20 and 30 nanoseconds.
obtain. However, the pulse width is uncertain at each buffer stage.
Become. Therefore, timing includes only the falling edge of 0SC-.
Say goodbye to S-bus memory, which can be used for controllers and semiconductors, respectively.
one or more having an array of memory chips
memory module. These modules
is memorized using a decoder on each board.
Selected by real address. Same bust but different I
- Size and speed modules can be mixed
. Memory operations that can be performed on memory modules
There are three types. i.e. reading, writing and special operations.
It is made by For special operations, read-modify-write
(RMW) Actions combined into one primitive command
It will be done. Burst transfers to or from interleaving memory are
divided into word block transfers. Each memory module
The module adjusts the bus bandwidth for quadword transfers.
Dynamic on quadword boundaries to match
Interleave the four columns of RAM. Dynamic R
In order for AM to be able to access it again
requires precharging time. 2. in any column.
During the quadword cycle read with t L,
time, including the 200 nanosecond precharge time.
In the example, it is 800 nanoseconds. accessed
During precharging of the current column, the memory module
Activate other columns. This means that successive quadwords
accesses overlap by 200 nanoseconds, and
Therefore, the effective cycle time required for these operations is 60
means decreasing to 0 nanoseconds. However, one module has two bus bands.
Unable to match width. Also byte, half word
and special operations are slower than the bus speed. Two or more memory modules to share the work
Bandwidth can be improved by providing . These memories
The modules are configured as bus operations alternate between modules.
Most effectively share the bus. Therefore, two or four
increment modules by quadwords
be able to. Burst transfer access for each module
Ses is cyclical, with successive quadwords occurring in different orders.
It is sent to the module. Module interface
Reaping is an address provided for each module.
determined by the decoder. Each module performs various operations.
Stores addresses and data received while the machine is busy.
It is equipped with 7 input vanes for storage. With this buffer
Improved performance by allowing more effective bus sharing
. However, the size of the buffer has a high priority
To achieve sufficient access time for read operations
limited to. In the disclosed embodiment, the data is already in the buffer.
The operation being performed in completes first. Buffers store sequences of operations on arbitrary storage locations.
save. Otherwise, memory values may become uncertain. Operations on different addresses are performed in arbitrary order
. Queues in any module are
It has nothing to do with the file. Address space A 32-bit memory address is transferred on the T-path.
Ru. This gives us 4 gigabytes of real address space.
It will be done. Memory read operation 4 memory read commands M! , MR2, MR3 and M
In R4, remove 1 from memory without changing the contents of memory.
4 words are read. MRI is one complete
A command to read a word, however, a byte
and can also be used for half-word reading. by
Words and half words are aligned on the bus as in memory.
have a ment. i.e. byte selection of data address
Bit A 01: 00 is set by the memory module.
It will be ignored. One complete Wattword is read in MR4,
On the other hand, in MR2 and MR3, 2
One or three words are read. word notes
Selected by address bits 03:02. a
The addressed word is transferred first, the remaining two
Words are in cyclic order, 0, l, 2.3, OS! , 2nd prize
are transferred in the same order. The 2-bit word address is
, returned with each word as part 4 of the F-path function code.
be done. The read operation sequence is a bus operation as follows:
[1] 1:2] [3] [4] ...
[5] 1:6 cycles [7 cycles] t
] ci<...Memory reading...>T-
Route [rq] [A] [] [akl [
] 'L] f] [IF-path [1
[] [ko [”Frq] EDE E]
[akF cycle 1, source module, e.g.
Processor acquires T-cycle, '8 (rq) cycle
Le 2. Address cycle (A) - source module
, for example, the processor sends a read function or command CM:? to (b) TFN4:0.
Set LMR2, [3, MR4) to Sera i, (2) Source Unino1-ID to TID7: (b)
and (3) set the memory address to 731:00.
. All memory modules have T −k for each cycle.
latch the path data. The source module is then
Release the bus after only dress (A) is sent out. Cycle 3. Each memory module has a memory address.
contains the addressed word.
Determine whether or not. If not included, subsequent actions
No work will be done. Parity is checked. selected
The memory module starts memory operations. Cycle 41 Selected memory module reads
Check the received message (!k). The memory module retrieves the required data from the memory array.
The source module that reads the data, requests it, and then
Cycle 5 to prepare for sending to the market. Memory module
Joule acquires F-path (rq). Cycle 6, Data Transmission Cycle (D) - Memory Module
Joule (b) Adds response function to FFN4:O! ·do. data is valid for rvOKnJ or rMDcnJ
to instruct. rMERnJ represents an uncorrectable memory error. 1'B" - 0, 1, 2 or 3 is a quad word block
indicates which word in the block. ``n'' is the address for the word on the bus.
Bit AO3:02. (2) The above memory module is latched in cycle 3.
Set the source unit ID to FID7:0.
. (3) Set the data word to F31:Go. The memory module is transferring the last data word.
to release the F-path. Usually all requested words
are transferred in consecutive cycles. However, memory
Data errors slow or interrupt this transfer
there is a possibility. The memory controller of the disclosed embodiments includes:
Require F-path before checking data validity
be able to. If there is an error, the next cycle is
The discarded and corrected data words are
Sent by car. Each module, such as a processor, has F during each cycle.
- Check the data on the route. Cycle 7, each module such as processor uses FID
Check against its own ID. If not equivalent, then
Does not have any effect. The source module has proper parity.
The data is searched as to whether it is or not. Cycle 8. The source module is
or ``out of order'' to prevent receipt of the item or items.
confirm. In the disclosed embodiments, the source module
is "blocked" or "blocked" for the memory operation you are requesting.
It is not possible to respond with "not present". Other than "acknowledgement"
response indicates malfunction. Cycles 6-8 are repeated for each additional word accessed.
will be returned. For example, MR4 has four words in the F-path.
transfer the code. Cycle... [5] [6] [7] [8]
[9] [101 [11] Read...>] F-path [rql [DO] [Dl] [
D2] [D3] [] []*ck [
] [3[][dO] [111[d2] [d3] Me
Memory Write Operation A memory write operation can be a byte, word, or multiple word.
The code data is written to memory. data word
(s) immediately to the address on the T-route
Continue. F-path is not used. The sequence of write operations is as follows. Cycle [11 [2] [3] [4] [5
] [6] [7] [8] [] [3<...me
Memory write...>Quadword...> T-route [
rq] [A] [DI] [D2] [D3
] [+14] [] []ack
[] [] [] [al [d11 [d
2] [d3 "d4] D2, D3, D4 are
Used only in forward word operations. write operation
The sequence is as follows. Cycle 1. Source module, e.g.
The server acquires the T-route (rq). Cycle 2. Address Cycle - This cycle is
Function code is written MWI, MW2, MW3 or MW
The read operation is the same as
be. The source module sends TKEEP to
will be put on hold. Cycle 3. Data Cycle - Source Module
sends (+) write data to Sera 1 at T31:00, and (2
) Set the unit ID to TiO2:fl, and (
3) Data code TFN4: O1 or DWOl
DWI, nwt; is set to [i3. during the last data cycle in a normal memory write
, function DWn is very easy to write!・"End with nJ"
Specify. This can be bytes, half words or other parts.
Used for writing the 7-minute code. Other write data cycles as well as all on the T-path.
Use function code DW3 for special memory data.
Must. On the other hand, each memory module has an
memory address to determine whether it contains a
decipher the response. Addressing word not included
In this case, no further action will be taken. Parity checked
be done. Selected memory module begins memory operation
. Cycle 4, selected memory module is at address
Cycle 58 Selected to Acknowledge Cycle
memory module is positive about data cycles.
respond. For MW2, MW3 and MW<, cycle 4.5
Additional data is sent in and 6. The size of each item after sending
It is checked and decrypted by the computer. Then the next cycle
7 and 7 in the affirmative. Multi-word write operation In multi-word write operation (MWI-MW4), data strip
is written to a quadword of memory. This space
The tring begins with the addressed byte. subordinate
bytes to the left of this word are not written.
stomach. In the last word, function code TFN4: written as 0.
The last byte to write is selected. Words are circular or itinerant within a quad sword.
be. The write begins with the addressed word and cycles through.
cyclic order 0, l, 2.3, fl, 1.2, etc.
be controlled by. The entire quadword can be any word
You can write for the first time. Partial quadword writing is performed on addresses with no alignment specified.
String movements and bursts that start and end at
This is useful for client transfers. data by (・in memory)
are lined up on the bus so that they are not in use.
Bytes that are not valid are ignored except for parity checking. Field names where only l words are transferred include address and TF
N imposes restrictions on which bytes can be written (hZ). TOI:00-00 0,1,2,3 DWO00
1000Gl 1,2.3 DW+ 001
111 0.110 2.3 DW2 00
110 [1,1,2II 3
D1113 (b+1111 0.I
J, 3 only words transferred and 5 written to the buffer
b) 0. ! Wl) Function code address with data word DWfl DWI DI9
2 DW3...00 0 01
012 G+23...Ol None
1 12 123...10
None None 223...No IO
None None 3-byte and half-sword movement
Byte and half word operations are performed using one data word MWI
is executed as a partial word write. This operation is a special case of the partial word described above. Memory address specifies the first byte written
. DWn identifies the last byte. other bytes are changed
Not changed. Bus timing is the same as full word write
It is. For memory timing, the error is
error correction code is calculated so that one long read
A write (RMW) cycle is used. each written
Bytes must be properly aligned within the data field.
Must be. The memory controller is
Do not shift the light. Unused bytes are ignored
. 0 0000100DWOOO, + 00 001
01DW11 0100101 DWI 2 10f1011iW2 1 2,3 1fl
O(l)1lDW33 II 00+11 DW
3 Special memory operation Special memory operation allows multiple processor interactions to
communication (dialogue) becomes easier. This kind of operation is
An indivisible preprocessor that operates as a modify/write cycle.
It is a mitivistic movement. According to this operation, on the S-bus
The transfer of write and read data is combined. original change
Unmodified memory values are read and sent to the F-path
It will be done. In the disclosed embodiments, several types of operations are described.
It is stated. 1. Bit operation M2S and MRR in data word
Any one bit of is set or reset. This bit
The number of cuts is selected by the write data value TO4:Go.
It will be done. 2. Exchange words! ,! Word swap with memory in RW
Watsuping is performed. The addressed word is read.
and returned to the F-path. After that, the T-route data
data word is written. 3. Address specification in semaphore operation MRI and IJRD
and the nisode is incremented or decremented. T-route de
data word is not used. In the disclosed examples, the
By convention, all written messages must be at least 2 words long.
It is a C-length. The sequence of special operations is as follows. Cycle [+] [2] [3] [4] [51...[6]
][7][31[9][][]<...read/modify
/Write cycle...>T-route [rq) [A 3
[DW][1k-A][xk-DlF-pathway[][H
][H]...[rql[DlF[][aklT-pathway is
Operates as a memory write, F-path is a memory read.
used. Test and Set Operations Test and St (T&S) Memory Operations Multitask
used to coordinate activities within an execution system
. T&S memory operations are limited to devices, tables and other resources.
A race is created to allocate access to the source.
Performs an interlock function to prevent Memory
The system reads the interlock word and sets the specified bits.
test the bit, set the bit, and write the word.
Execute the inseparable action called. This function is MR5 command
done in response to. Overview of direct transfers on the F-path In addition to the memory read data described above, the F-path
Inter-processor messages, simultaneous notification interrupts, direct input/output and
and compatible input/output. Inter-Processor Messages An inter-processor "message" is a
is the three data from channels -1' and -t,
i1 included to another specified processor or
・Transfer to Nell. This message is the person/'output (I
lo) To start the channel operation when the operation is completed.
Multiple processes can be used to schedule and reschedule tasks.
processors for the purpose of harmonizing processors in a system.
used by system designers. It is a message. In the disclosed embodiments, the channels are stored in memory.
according to the “Channel Command Block” (cCB)
perform input/output tasks. CCB is a specific I10 movement
Selection of related devices, functions, storage buffers, etc.
We have information regarding. The processor is CCB
Message on I10 channel to start operation
send. This message contains the address of the CCB in memory.
I'm here. The channel then performs the memory operation described earlier.
is used to access the CCH and execute the required functions. De
Data is transferred directly to or from memory. Cha
The data buffer and command
Can be chained together. Chang Yi Lu describes the situation as
Report to the processor by sending a message
. In the disclosed embodiment, the inter-processor message is (
a) From the processor to the channel to start the CCB.
“■10 Start” command sent, (b) Execution of CCB
sent from the processor to the channel to stop the
“I10 Stop” command, (e) Pro after CCB is completed.
Processor from channel to interrupt processor.
or (d) the “I10 End” interrupt sent to the
``processor'' sent from one processor to a second processor.
This is an interrupt. Source (outgoing) and incoming module
A channel can be either a processor or a channel.
Such a termination module provides flexibility. For example, I
10 Processors receive and send messages as channels.
You can also access other channels.
110 operations can be requested. Interprocessor messages are word F, which is 3 words long.
FN FID F31-FOOI
Ig unit-d level, unit-8l
Parameter #12 +3 Unit -d
Parameter #23 13 Unit
Table above for parameter #3
The FID, namely FID7:O, is the incoming module.
Unit-5 is the ID of unit-d, and unit-5 is the source (originating)
) is the ID of the module, and the level is CCB operation or
sets the "priority" of interrupts. For example, in the disclosed examples
"0" is the highest priority level. In addition, pa
Parameter #1 represents a half word, parameters #2 and #
3 stands for all words and their meanings are
Defined by convention. The sequence of five messages is as follows. Cycle [+] [2] [3] [+] mouth ]F
-Route [rq)[MSG][Dl][D21[]
[]xckn [][][][a-MS][
a-DI ] [1-02] Cycle 1. source mod
The call requests and captures the F-path (rq). Cycle 2. The source unit sends word 1 to the F-path
(MSG) (b) The source unit sets the function code MSGn to FF.
N4; Set to Q2), Set 1 communication unit ID to FID7:0.
3) Level, source unit ID and parameter #
Set l to F31:00. All processors and channels are
Latch route data. Cycle 3. The source unit is word 2 of the F-path.
(Dl) (b) The source unit sets the function code FDAT to FF.
N4: “Data word” set to 0. (2) Furthermore, set the ID of the receiving unit to FID7:0.
(3) Set parameter #2 to F31:0. Cycle 4. Source unit puts word 3 on F-path
Set (D2). (+) The source unit has a function code in FFN4:0.
A “data word” that sets FDAT. (2) Further? Set the ID of the incoming unit to FID7:0.
3) Set parameter #3 to F31:il.
) Set M communication module acknowledgment word 1. Cycle 57 Incoming Module Acknowledgment Word 2 Cycles
6. Incoming Module Acknowledgment Word 3 Broadcast Communication Interrupt Broadcast Communication
This is an interrupt that is sent simultaneously to The processor is
All broadcast notifications δ are received regardless of ID. Disclosure implementation
The two broadcast interrupts used in the example are
(PRE) and [Real-time clock start J (SY
NC). Broadcast is not acknowledged on F~ route
. Therefore, when the processor receives a broadcast communication, the processor
information must be used. In other words,
"Block" information to request message repeat
cannot be responded to. The sequence of broadcast interrupts is as follows. Cycle [l] [2] [3] [1] F - ? each
[rq][FFN][][]δc
k E ] [3r ] [Kosa Ikl 1. The source unit requests and obtains the F-path.
gain (rq). Cycle 2. Broadcast: Module ()) function code (PRE or other defined code)
) to FFN4:0.2) Set zero to FID7:O.3) Seratose the broadcast message to F31:Q. The processor and channel as F-
Latch route data. Cycle 3. All processors send broadcast messages
decipher. Broadcast communications do not receive acknowledgment of receipt. For those who want to synchronize clocks in a multiprocessor system
"Real-time clock activation" is used. In the disclosed examples
Each processor has an operating cycle of the system bus.
64-bit recorder that records accurate time by counting
It has a ``real time'' clock. −1 initial setting
However, all clocks in the system have exactly the same time.
Record. 5yric does not send any data.
stomach. That is, bit F31:00 is ignored. However, the sending module does not share its ID with the bus
Set bits F23:16 for use by monitor
. The following procedure is used to initialize the clock. Step 1: One processor is connected to all other processors.
The real-time clock is stopped for the processor, and the
Parameters #2 and #3 for words 2 and 3 of the message
reloads the 64-bit time stored in
Sends a message instructing the Step 2: The above one processor processes the message
Acknowledge interrupts and reload their real-time clock
time information for each processor in the system.
Wait 100 microseconds to give information. Step 3: The above one processor has 5
Send YNC. This broadcast message is
It is decoded by the hardware in the processor and all
The processor has two cycles within two cycles to achieve precise synchronization.
Start Florakura. 5 YNCI 1 word of 7 Omatsu l- like the following
It's sage. That is, FFN is χ16 and FID is
Transmitter module ID (all IDs on the S-bus system)
Broadcast communication decoded by processor and channel
(used for messages), F23:16
is the ID of the sending module. According to direct input/output (Ilo), the processor selects
Read the I-device or channel word
Channel I
/'0 complexity is avoided, but the response is
have to wait. Direct I10 is useful for communicating with test equipment. The processor reads data to the selected device.
To read (IOR), 1: or write (tOW)
Can be done. , IOR, one word is sent out and its
Then, in IOW, the data in the second word is sent out. Incoming module indicates successful completion of operation
Reply with IOK or error Table 1-IER. Readings
The output data is returned with an IOK. Direct I10
The sequence is as follows. Cycle [1] [2] r3] [4] 1
:51 ... [6] [7 pieces [8 pieces] [9] [
] [] <...Input/'Output...>F
-route [rqU [IOR] [] fakJ
[] ”・[rq] [IOK] C] [ak
] or [rqU [IOW] l:D] [ak-W] [a
k-D]”・[rqF EIOKI [] [a
k] Cycle 1. The processor obtains the F-path (r
q). Cycle 2o cycle selection, the processor: (b) sets IOR or tow to FFN4:0;
(2) Incoming call module (7) ID
Set FID7:0, (3) Set the sub function/device to F31:G as follows. Set to . F31:N (4-bit) Subfunction F'17:24 (4-bit) Not used F23:16
(8-bit) IDFIS of sending unit: 00 (
+6-bit) Channel/Device Number Cycle 3. It is a data write cycle and only Iow is
If possible, the processor sets FDAT to (+) FFN4:0.
(2) ID tl-FID of the destination S unit at 7:0.
Set (3) ■Inclusive day/evening to F3]:00.
to Cycle 40 The incoming module acknowledges the selection cycle.
Constant response (ak). Cycle 57 Incoming module is data write cycle 1
Acknowledge only 0W (ak-W). (b10 unit performs data transfer) Cycle 6, arrival
The communication module acquires the F-path (rq). Cycle 7.1 OK or IER cycle for incoming calls
(+) IOK, I- set IER to FFN4:O
(2) Enter the processor unit ID as FID? :O
(3) Set 7'-Ichiyo to F3+:Ofl -1O
Response to R only. I'm cumming 8. The processor decodes and checks the received items.
Check. Cycle 9. The processor acknowledges (bk). Compatibility I10 Compatible input/output (Ilo) operations are
Compatible with 3200 series MIX and EDMADMA
Direct memory interface for deposit/withdrawal bus
This is done by SuJ (DMI). The processor directly
10 operations to access DMI, and sub-functions,
Decide which specific MUX bus operation to perform. Multiple S-Bus Systems Interconnect two or more S-Bus systems.
can be operated together. The processor is
access memory in other systems using
You can also use the ID of the unit to connect other modules.
access memory by sending a message to the
can do. The two S-buses are
``Base Expansion'' board (SBX) interface symmetrically.
Connecting systems are connected by cables. Each S
- Bus with separate power supply, diagnostic system and clock distribution
can have means. SEX refers to operations directed to remote systems.
Monitor routes and F-routes. In the D-route,
In the disclosed embodiment, the SBX stores a bitmap and a bitmap in RAM.
response to the selected memory address stored as
Ru. For example, using a 64K x 4-bit RAM, S-
Each bus has 64 byte blocks in the 4 GB real address space.
Stores 4 bits per lock. In the F-pathway
, SBX responds with the ID of the selected unit. child
In the disclosed embodiment, these IDs are 2S6x4 bits.
Stored as a bitmap in RAM. Messages received by local SEX are acknowledged.
, - temporally stored and provided to the remote SBX. Remote S
BX acquires the corresponding remote route and sends the message back
Ru. These two SBXs can be operated from remote systems.
In this case, the roles are reversed. T-B route and F-route J, (7) SBX9JJ work 1
;l:, I'f'l In case of actual distance measurement, the same cable
They are independent from each other except that they are shared. F
- Route transfer has priority over cable 5° SBX decodes address
use cl. In other words, 5IIX uses Takashi RAM memory.
I of each unit to be accessed in the remote system using
D and each 1 MB memory block bitmatsu
can be stored. If desired, the SBX can be
Access will only be allowed to the Zazu set of the remote system.
It can be done. The unit ID and address are
5BXil- is not translated and the message is subject to change.
It will be returned without any problem. The SBX can A-burlap memory reads by 6k.
Use the IDs of the four units so that you can
The BX assigns one of these four IDs to the SBX.
Replace with the ID of each remote memory operation received. Original IDi
;tT- not set in path, stored and read
It will be returned along with the submitted data. In this way,
The ID used to access the memory has a width specific to the system.
There's no need to do it. of units coming from memory requests.
The ID is not checked against the ID RAM. System Cables Figure 1 shows a system including data paths +17 and 118.
Shows 5BXIIO connected to cable. day
The data paths 117 and l1m are similar to the T-path and the F-path.
It is a similar route. Messe from S-Bus 10 or 20
The page is represented in CT by 5BXIIO and 210.
is sent out on the data path from the connection that is connected to the S-bus.
Messages for 10 and 20 are connected to the connection marked CF.
by SBX110 and 210 from the data path at
Received. The system cable 107 includes a local SBX,
For example, connect each CT connection to a remote SBX of 5BXIIO (71)
, for example, connect to the CF connection part of 5EX21G. The signal? The definition is similar to that for the S-Bus. one
An extra signal is used to detect each message arriving.
Instruct the route to take. In other words, T-route is selected at CTT・1
and the F-route is selected at CTT·0. Furthermore, C.T.T.
Note that this is accepted as a CFT by the remote SBX.
It's a lot of attention. S-Cable Signal Definition CT CF Transmission Reception Signal Definition CT31:
00- CF31:00- 32 bit data
Field CTFNI:0- CFFN4:O-
S bit function selection CTID7:07 CFID7
:0- a-bit unit identification number CTPAR5
:fl-CFPAR520-Parity
No. CTT-CFT-T-path (+) and second is F-path (0
) message CTAKI:O-CFAKI:θ-acknowledgement (reception confirmation)
Response) CTRDY-CFRDY-More data available
Each SBX can be connected to continuous clock CTCL after CT.
Transmit K. All items are synchronized to this clock.
Ru. However, the remote SBX
It can be received as CFCLK asynchronously with its own clock.
must be able to is a remote system
may be operating with different oscillators.
Ru. However, the SBX also requires that the S-bus operate synchronously.
If this is the case, it should be possible to operate synchronously. Combined Memory Module DescriptionCombined Memory Module
Joule (cMIJ) 100Q, concurrent controller
Manufactured by Pewter Corporation
Model 32HMPSJ computer system
storage control module and on one board for
It is a combination module of memory controller and memory controller. Ko
Some CMMs in computer systems are two-way or
or in 4-way mode, interfacing on quadword boundaries.
Can be left. As shown in FIG. 5, CIJMlooG includes 1.
2 or 4 dynamic memory arrays 601
up to 60 (with each array having 4 columns x 39 bits)
Be organized! +55 dynamic RAM (61K
XI or 256KX l). This allows for simple
1-bit error detection and correction, 2-bit error detection
7 bits for error detection 1-
32 with error checking and correction (FCC) code
Allows storage of bit data. CMMlooo's
The data storage capacity for the Dairoku Mink R is 61KXl.
If using AM, it is 1.2 or 4 MB,
4.8 when using 256KXl dynamic RAM
Or 16 megabytes. The implementation is a 0.1 inch square cell with 22 bins.
Using 05IL package QSIP which is a lamic substrate.
achieved. Each board is equipped with four RAMs.
QSIP is installed vertically on CMM 100G.
It will be done. According to this method, four memory arrays are realized.
It will be done. Reduce this board to 1 or 2 arrays
It is also possible. As shown in FIG. 5, memory array 601-6
04 each have 64KX I bits with nibble mode.
This is a dynamic RAM. In one embodiment
In nibble mode, 2.3 or 4 bits of data
High-speed sequential access is possible. Activating RAM
Always 8 column address bits and upper 6 of row address
Internal access to 4 bits of data selected by bit
A process is carried out. Two row addresses indicated by A3 and A6
of 4 nibble bits for the initial access.
Select one bit from within. The remaining nibble bits are
Set the CAS control signal on line 605 high and then
accessed by switching to low level following
while the RAS control signal on line 605 is low.
Stay on level. CAS level switching on line 605
, A3 and 86 are internally incremented and the other
All other address bits remain unchanged. nib
Mode: 5 or more bits are accessed during access.
address sequence is repeated.
Ru. If a bit is written during a nibble access, then
, the new value is read on the next nibble access. Ichisaka
Inside the 2S6KX IIIAM chip available as a stock
There is a nibble mode, which is slightly different from the modes described above.
There is something. - As an example, 4-bit data is
Selected by the lower 8 bits of the row address, and
The upper bits of the row address
Used to select one of the bull bits
. The data to be written to memory is stored in the write data register (
WDR) 610 through memory arrays 61G to 60
4. Reading data from memory
Read data from arrays 601-604
buffer (RDB) 612 to read data.
data register (RDR) 613. memo
The address of data in arrays 601-604 is
(CAL) 614. memory
The address is address multiplexer (AMX) 61
6 supplies the memory ゛rReiro01-6〕(
. In each memory array, four columns are connected on line 605.
Signal RASO: 3- quadword boundary under control of
It is incremented above. Each time a column is activated,
Take advantage of the nibble mode to write up to 4 words.
can access the code. This allows memory
High-speed Kanto words just by using only one column.
Access is possible. 7 All commands for memory operations are specified by mask ID, machine
Supply function code and 32-bit address to T-path
This is initiated by the CMM 1000. already mentioned
As such, transfers on the S-bus are derived from 0SC-
Synchronized by CLK-
held in state. 05C- and CLK- are line 6
CMM 1 to clock driver 620 via CMM 19
000 is supplied. The CMI, l 1000 is
Continuously monitors 50 conductors that make up the T-path in connection 621
By doing so, the command will be accepted. This is for each bus operation
The T-path is processed by input latch (IL) 622 every cycle.
This is achieved by sampling. IL 622 is
, has seven outgoing latches that receive data from the T-path.
It is growing. The output of IL 622, i.e. 50 input bits.
All kits are equipped with a parity check circuit (FCC) 67
1. PCC671 has 5Q bit parity.
Revised 2? and transmit (compared with U TPAR4:O)
Ru. When an error occurs, the FIFO 621 array of the T-path
Parity error in T-path confirmation circuit (TPA) 673
- A signal is sent. Furthermore, 19 bits, T31:
2OSTO5:04 and TFN4:0 are IL622?
board select logic (BSL) 67 via line 627
Sent to 2. BSL 672 is Pi1-TFN4:
0 to determine whether the command is a memory operation;
And using Pi1-T31:20 and TO5:04
, addresses of memory operations that configure the CMM 1000.
memory arrays 601-604.
Determine whether or not it is possible. If the two conditions are true, then
, BSL 672 connects TPA 67 via line 628
Send a signal to 3. In response, TPA 673
sends the associated acknowledgment TAKI:flo message on line 625.
Apply the number. Additionally, the function code of the received bus data item is memorized.
indicates that re-operation is requested, and CMMo2
If an address match occurs for O3, SL 62
2 to 45 bits - T31:00, TFN4.0, TI
D7:0- to PIFO624 via line 623
Sent. As already mentioned, four words with a write command
The write data up to
Continue the cycle. The written data sent after this is also
It is also stored in the PIFO 624. In the disclosed examples
The FIFO624 is 15 words wide, and! case of l
I will continue to receive orders until the storage area is full. CMM
1000, 11 storage locations of PIFO624 are full
You cannot receive commands after this happens. That's because
For the quadword write command, the PIFO624
This is because five storage locations are required. FIFO62
If TPA 4 no longer accepts commands, the signal TPA 6
23, the TPA is sent to the track or line 62
5, transmit the "blocked" response as TAKl: 0-
do. In the disclosed embodiment, there are 13 T-path HFOs 624.
It has 16KX4 RAM. Enter FIFO621
The data signal is negative and true, and positive and true when it exits. That is, the data signal is inverted. The command signal in FIFO 621 is sent via line 630.
Sent to command latch (cL) 631 to start memory operation
let This command signal contains the ID of the mask unit.
TID7:0, memory operation function code TFN, 4:0
and status information. At the same time, FIFO624
The address of the memory operation to be
Sent to the 6th Res Latch (AL). Read operation CL 631 and AL 614 were loaded with read command
Later, in one of memory arrays 60b 604
Ru RA! One row of J is CL 631 and AL 61
4 and sends a signal to the array driver 47.
, thereby line 6 Q S
J2's associated RASn- signal goes low. A
MX 616 first connects AL 6 via line 705
14 receives the column address for the data. then
, AMX 616 provides the row address for the array
It is switched as follows. This line address is
is received from AL6!4 via link 706. Then,
CAS- appears on line 605. Therefore, line 635
selected l− in memory array 601604 via
Data is read from the column. This data is stored in buffer R
RDIi through DB 612! stored in 613
Ru. The contents of RDR613 are then monitored for checking purposes.
6 transmitted to error check correction circuit (FCC) 610
If no error is detected in ECC6411
, the data is transmitted to the data output register (DOR) 645.
36F-path control circuit 57
(b) read data in DOR615;
In addition to In646, (2) operation in DOR65G
Enter the ID of the mask you requested, then enter line 665.
Intervention 1. 1 supplied from TecL 631 to ooR656
0 to line 660 and (3) from DOR658.
on line 662, and (4) D
Adding parity from OR557 to line 661
The bus data term is passed through the 50 conductors of the F-path by
The eyes are output. The above parity is a special function gate.
Generated by the parity generation circuit (PGC) in the array 59.
It is something that was born. If you want to access up to 3 additional words.
is the signal applied via line or line 605
CAS- is switched to array control line driver 47.
Ru. Write Operation A write operation is performed when signal CAS- is initially
The read operation begins in exactly the same way during the time that appears. book
The included data is sent to the FIFO 624 via line 666.
is stored in the data input register CDIR>667.
. The contents of DIR667 are transmitted to ECC64G. blood
The check bit is generated by ECC 640. Che
The read bits and write data are then sent to WDR61G.
Stored. Next, array control line driver 47
sends the signal WE- and writes the write data in wDR610.
The memory arrays 601-604J are stored therein. addition
When writing up to 3 words into memory, write up to 3 words.
These words can be written to FIFO62
4 and loaded into DIR667 and NOR6
1G and low level signal WE~ and switching signal
Written into memory by CAS-. Byte, half-word and string write operations are described above.
using the 8-inclusive operation and the appropriate
CM related function code and address! ,! 1000
The first of the six aging operations performed by supplying
For the second word, the lower two bits of the command address
The geometry bytes of the first word are stored in memory using
It is determined whether it should be written to. r OOJ is byte O-
“Ol” indicates writing bytes 1-3.
``!O'' represents write bytes 2 and 3, and
"11" represents writing of byte 3. bytes are data
Byte '0' in bits 31-32, data bit
Byte “1” in bits 23-16, data bit
Byte “2” and data in 15-8 PILL-7
This is the order of byte "3" in -0. Accompanying function code
How many bytes of that word are written to memory?
JOOlooJ, which determines whether the
0 and roololJ represents write byte Q-1.
, f'00110J represents write by h O~2,
rou++” represents write bytes 0-3. MW1
MW along with the function code in the write data part of the command.
Many different combinations of the lower address 2 bits of one command can be used.
It is possible to perform partial writing. when a part of a word has to be written to memory
The CMM ION always first locates the desired storage location in memory.
Read the word in the location to RDR613 and check the error
Check it and write some of the data in RDR613.
Replace the new data with the data from DIR667, and
generates new check bits and
Store new check bits in WDR6101m and WD
R61G(7) Write contents to memory. In the special operation disclosure embodiment, CMI,! 1000 is 6
Performs special actions. The first five actions are
Read data from memory, send data to F-path
, modifying or modifying data and placing data into memory.
This is writing. Memory read and cellar 1-MR5 and memory read and
and reset MRR, the data is placed on the F-path) T:
The read operation begins exactly the same as the read operation. at the time
The data is then latched into gate array 675. A 5-bit selection code is then read from FIFO 624.
and sent to the game 1 array 59. This code is
1 on the T-path. I RS /'M Immediately after IIR command
Derived from Te3:Go- in the following cycle. then
Gate array 59 stores the 32 bits in the latched word.
Serialize or reset one bit of the bit. There, the modified or qualified word is added to the gate array.
The new check bits are read into the ECC640 from
is generated, data bits and check bits are WD
Stored in R61Q. Next, the contents of WDR610
is written to memory. Memory read and increment MHI and memory
The reading and decrement MRD of PIFO624
Points and gates where no 5-bit code is extracted from
Array S9 ``1''s the word read from memory.
Increment or Decrement〉1・(Decrement)
) is carried out exactly the same as 1AR5/MRR1 except that
Ru. Memory switching operation MEX reads from memory.
(1) to modify or change the gate array 5;
9, the new 32-bit word is F
This new L2 is placed in DIR667 from IFO624.
MR3/I except that one word is written to memory.
It is done exactly the same as JRR. The sixth special operation, that is, memory write diagnosis MWD, is as follows:
F-Does not generate any data on the path. MWD is
Read word from memory and discard 32-bit data
and the new 3 from FIFO 624 via DIR 667.
2 bits and check the new word with the old bit.
It is written to memory via the WDR 610 along with the data. to this
Therefore, the error will appear at the same position on subsequent reads.
It becomes possible to In the disclosed embodiment, the y3 Emperor ECC640 is
Instrument Corporation NorTI 74ALS632Ju32 pin
This is realized by using a 1-FCC chip. ECC64G detects all single bit errors in memory
detects and corrects all double-bit errors and
has the ability to detect several multi-bit errors.
There is. If a single bit error is detected during a memory operation, the EC
C640 connects internal data bus 640 from RDR6N.
The error data is latched, the data is corrected, and the corrected data is latched.
Store the data in WDR610, and
from WDR610 to RDi! Move to 613. Read
In case of operation, the new check bit is set to RDR6.
Generated for new data in N, data and check
The clock bits are stored in WDR61G and WDR
The contents of 61G are written into memory. Write operation and
Special operations usually require corrected data to be stored in the RDRaN.
It will continue until it is paid. If a double or multiple bit error is detected,
CMM 1000 does not support read or special motion, except for MWD.
During the work, error data is placed on the F-path along with the associated response behavior.
Send. In a write operation, a partial word is written.
Sometimes CMMlooo is addressed
Rewrite the memory location with "all-1 pattern". this
This allows multiple bit error conditions to occur while performing a write operation.
is sent back to Mask, who is making the request. read again
If multiple bit errors occur during special operation,
Data in memory is not modified. Memory error is
This cannot occur during MWD operation. Do you mean memory?
This is because the data read from there is not checked. It will be obvious that those skilled in the art will be able to deviate from the teachings of the present invention.
Other embodiments of the invention may be devised without departing from the scope of the invention.
I would like to add that.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a block diagram of the module connection to the path in the bus system of the present invention;
FIG. 2 is a diagram showing a block diagram of the bus route capture circuit in the bus system of the present invention, and FIG. 3 is a block diagram of the bus route capture circuit of the bus system of the present invention. FIG. 4 shows a block diagram of a clock distribution circuit of the bus system of the present invention, and FIG. 5 shows a memory module for use with the bus system of the present invention. 1...F-route, 2...T-route, 10.20
...S-bus, 29...backbrain, 30...
・Bus capture request circuit, 4G...priority encoding circuit, 10
1...Composite memory module, +02...CPU
, 10S...Input/output channel, 106...Module, 107...S-bus cable, +l0
121G...S-bus exchange circuit, 30m-301.
...HANDX303310...JK flip-flop, 309.311...D-flip-flop,
3!2.314...AND, 3+5...N0R1
3. Position number destination circuit, 320... Inverter, 3
21... NANI+, 371... Pull-up resistor, 381... Priority encoder (encoder), 3
82...f3J first decoder (decoder), 3R5,3
86...NOR, 652-6N, 655-659...
·Resistor. FIG, 3 ・Gutsuku plane 29

Claims (1)

[Claims] 1. A bus system for transmitting data, function codes, identification codes, and parity information between connected modules, having at least one path, the path comprising: (a) 32 route lines for transmitting route data (
(b) five route lines for transmitting a route function code; (c) eight route lines for transmitting a route identification code; and (d) five route lines for transmitting route parity information. (e) four route acquisition lines for transmitting route acquisition signals; and (f) two route acknowledgment lines for transmitting route acknowledgment codes; means for connecting a module to a route and a route system capture means, the route system capture means for: (a) generating a route capture signal in response to a route module signal generated by the at least one module; (b) means for generating a route module capture permit signal in response to a route module capture request signal generated in the at least one module in response to a route capture signal; route module capture means for generating a route module capture request signal in response to the route capture signal; (c) means for determining whether the at least one module has captured a route in response to a route module capture permission signal. 2. The bus system of claim 1, wherein the route system capturing means further comprises means for assigning location priorities to modules to give preferential access to the route to modules with relatively high location priorities. . 3. (a) the route module capture means further comprises means for generating a "simple route request" signal as one of the route module signals; (b) the route system capture means further comprises means for generating a "simple route request" signal from the module; ” signal in response to the “compound simple request” signal RE.
3. A bus system as claimed in claim 2, including means for generating Q- as one of the route acquisition signals. 4. A route module capture means for determining whether at least one module has gained access to the route in response to a route capture permission signal, wherein the at least one module has access to the route. take first and second logic values, respectively, and generate MINE and MINE- signals, respectively, that take first and second logic values when the at least one module does not have access to the path. 4. A bus system according to claim 3, comprising means for. 5. The route module capture means takes a first logical value in response to a signal from at least one module if the module requests to gain access to the route, and otherwise takes a second logical value. 5. A bus system according to claim 4, further comprising means for generating a bus request signal (RQ) having a logic value. 6. The route module capture means, in response to the MINE- and RQ signals, if at least one module requests to gain access to the route and the route is not already accessed by that module, i.e. RQ and MINE - a patent comprising means for generating a "simple bus request" signal which assumes a first logic value if the signal has a first logic value and a second logic value otherwise; The bus system according to claim 5. 7. The path system capture means further includes the
7. The method according to claim 6, further comprising means for ORing the "simple bus request" signals to generate a "compound simple request" signal (REQ-) on one of the first route capture lines. bus system. 8. Claim 7, wherein the route module capture means further comprises a flip-flop for generating an RQ signal in response to a signal from at least one module.
Bus system as described in section. 9. (a) the route module capture means further comprises means for generating a "route access hold" signal as one of the route module signals; and (b) the route capture means further comprises means for generating a "route access hold" signal from the module. means for generating a "Keep Composite Route Access" signal (KEEP-) as one of the route capture signals in response to the "KEEP" signal, the controller having access to the route and requesting the route to complete the task; 4. A bus system as claimed in claim 3, in which a module having access to the path can withhold access to the path for the next bus system operating cycle. 10. The path module capturing means further takes a first logical value when the module is requesting path access for an operation other than a single bus system operation, and otherwise takes a second logical value. in response to an "additional data" signal and a MINE signal from the at least one module;
Claims comprising means for generating a "route access retained" signal which assumes a second logic value if the module wishes to retain access to the route and takes a first logic value otherwise. The bus system described in paragraph 7. 11. The route system capture means further logically ORs the "route access hold" signals from the modules and issues a "composite route access hold" signal (K
11. The bus system according to claim 10, further comprising means for generating EEP-). 12. The path module capture means is further responsive to the KEEP- and REQ- signals to take a second logic value if no module seeks to retain path access, and a first logic value otherwise. A path signal (PAS) that takes a value
Claim 1 comprising means for generating S-)
The bus system described in item 1. 13. The bus system of claim 12, wherein the path module capture means further comprises means for generating a path module capture request signal in response to the RQ signal. 14. The path module capture means is further responsive to one of a PASS- signal and a path module capture permission signal;
first and second logical values, respectively, when at least one module has gained access to the path;
14. The bus system of claim 13, further comprising means for generating GETBUS and LOSEBUS signals having second and first logical values, respectively. 15. The path module capture means further receives the signal GETBU.
Signals MINE and MI in response to S and LOSEBUS
15. A bus system as claimed in claim 14, comprising means for generating NE-. 16. (a) the route module capture means further comprises means for generating a "round robin request" signal as one of the route module signals; and (b) the route system capture means further comprises means for generating a "round robin request" signal from the module. A "compound round robin request" signal (RREQ) is sent as one of the route capture signals in response to a "round robin request" signal.
-), thereby causing a module requesting round-robin priority to have access to one module until all modules requesting round-robin priority have access. 10. The bus system of claim 9, wherein access to paths for bus operation cycles is provided. 17. The route module capture means further comprises first and second logical values, respectively, if a round robin request is desired, and second and first logical values, respectively, otherwise. 16. A bus system according to claim 15, comprising means for generating request signals (RREN) and (RREN-). 18. The route module capturing means further includes RQ and RRE.
in response to the N signal, generating a "round robin request" signal that takes a second logical value when the module is seeking round robin priority access to the route and takes a first logical value otherwise; 18. The bus system according to claim 17, comprising the means of: 19. The route system capture means further logically ORs the "Round Robin Request" signals from the modules and places a "Composite Round Robin Access" signal (
14. The bus system according to claim 13, further comprising means for generating RREQ-). 20. The route module capture means further includes RREQ-, R
20. The bus system of claim 19, further comprising means for generating a path module capture request signal in response to the Q, RREN and RREN- signals. 21. The route module capture means includes: (a) means for generating a logical product (AND) of the RREN and RQ signals; 21. The bus system according to claim 20, comprising: means for generating a logical product; and (c) means for generating a NOR of the logical product output. 22, (a) the route module capture means further comprises means for generating a "high priority request" signal as one of the route module signals, and (b) the route system capture means further comprises means for generating a "high priority request" signal from the module. means for generating a "composite high priority request" signal as one of the route capture signals in response to the "request" signal, whereby the module having a low priority is 17. The bus system of claim 16, wherein priority access is given to the first path in advance, and high priority requests are accepted in order of position priority. 23. The route module capturing means further generates a high priority signal (HPEN) having a first logic value when the module is seeking high priority access to the route and a second logic value otherwise. 21. A bus system according to claim 20, comprising means for. 24, the path module capture means further comprises HPEN and R.
In response to the Q signal, the module comprises means for generating a "high priority request" signal having a second logical value when requesting high priority access to the path. The bus system according to item 23. 25, Patent in which the route system capture means further comprises means for ORing the "high priority request" signals from the modules and generating a "composite high priority" signal (HREQ-) on one of the route capture lines. The bus system according to claim 24. 26, the route module capture means further includes RREQ-, H
26. The bus system of claim 25, further comprising means for generating a path module capture request signal in response to the REQ-, RQ, RREN, RREN- and HPEN signals. 27. The path module capture means further comprises: (a) means for ANDing the RREQ-, HREQ-, RQ, and RREN- signals; and (b) means for ANDing the HREQ-, RQ, and RREN signals. (c) means for calculating the logical product of the RQ and HPEN signals; and (d) means for calculating the negative sum (NOR) of the logical product output, and generating a path module capture request signal. The bus system according to clause 26. 28, the route module capture means further captures the signal RREQ-
and signals RREN and RREN in response to GETBUS.
21. The bus system according to claim 20, further comprising a flip-flop for generating -. 29. The bus system of claim 26, wherein the path module capture means further comprises a flip-flop for generating the signal HPEN in response to a signal from the module. 30. The bus system according to claim 29, wherein the signals REQ- and KEEP- are open collector signals. 31. The bus system according to claim 19, wherein the signal RREQ- is an open collector signal. 32. The bus system according to claim 25, wherein the signal HREQ- is an open collector signal. 33, R to generate the route module capture request signal.
14. The bus system of claim 13 further comprising means for inverting Q. 34, the route module capture means further receives the signal GETBU.
Signals MIME and MI in response to S and LOSEBUS
16. The bus system according to claim 15, comprising a flip-flop for generating NE-. 35. The bus system of claim 1, wherein the route acknowledgment code is an open collector signal. 36. The bus system according to claim 35, wherein the route data is a three-level signal. 37. A path system capture circuit connected to a bus system path for transmitting data, function codes, identification codes and parity information between connected modules, and generating a path capture signal and a path module capture permission signal; In a bus system having a bus route capture circuit for connected modules, comprising: (a) means for generating a route module signal, the route system capture circuit generating a route capture signal in response to the route module signal; (b) means for generating a route module capture request signal, and in response to the route module capture signal, the route system capture circuit generates a route module capture permit signal; (c) a route module capture request signal; A bus system having a bus route capture circuit, comprising means for determining whether a module is capturing a route in response to a capture permission signal. 38. A route system capture circuit for assigning a location priority to a module and giving priority access to the route to a module with a higher location priority, and a "compound simple request" signal (REQ-) as one of the route capture signals. and means for generating a "simple bus request" signal, the bus capture circuit further comprising means for generating a "simple bus request" signal as one of the route module signals, and the route system capture circuit further comprises means for generating a "simple bus request" signal as one of the route module signals; "Compound Simple Request" in response to a signal
A bus system having a bus route capture circuit according to claim 37 for generating a signal. 39, means for determining whether the module has gained access to the route in response to the route capture permission signal, the means for determining whether the module has gained access to the route; MINE and MIN which take a logical value of , and take second and first logical values, respectively, if said module does not have access to the route.
39. A bus system with a bus path capture circuit as claimed in claim 38, comprising means for generating an E-signal. 40, in response to a signal from a module, a bus system request signal RQ having a first logic value if the module is issuing a request for access to the path and a second logic value otherwise; 40. A bus system having a bus route capture circuit as claimed in claim 39, comprising means for generating a bus route capture circuit. 41, means for generating a "simple bus request" signal in response to the MINE- and RQ signals, the signal indicating that a module is requesting to gain access to a path and that the path has already been accessed by the module. It has the first logic value when it is not accessed, i.e. when the RQ and MINE- signals have the first logic value, otherwise it has the second logic value.
41. A bus system having a bus route capture circuit according to claim 40, having a logical value of . 42. The route system capture circuit further includes a circuit for ORing the "simple bus request" signals from the modules to generate a "compound simple request" signal (REQ-), and the bus route capture circuit 42. A bus system having a bus path capture circuit as claimed in claim 41, further comprising a flip-flop for generating an RQ signal in response to signals from the bus path capture circuit. 43, from the module having a first logical value when the module is requesting path access for more than one bus operation, and a second logical value otherwise.
in response to the ``More Data'' signal and the MINE signal, a ``Keep Path Access'' signal having a second logic value if the module wishes to retain access to the path and a first logic value otherwise; 42. A bus system having a bus route capture circuit according to claim 41, comprising means for generating a bus route capture circuit. 44. The route system capture circuit includes a circuit for ORing the "Keep Route Access" signals from the modules to generate a "Keep Composite Route Access" signal (KEEP-); - and REQ- signals, for generating a PASS- signal which takes a second logical value when no module requests retention of access to the path; otherwise it takes a first logical value; 44. A bus system having a bus route capture circuit according to claim 43, comprising the means for:. 45. Claim 44 comprising means for generating a path module capture request signal in response to an RQ.
A bus system having a bus route capture circuit as described in 2. 46, PASS-signal and path module capture signal 1
GETBUS and LOSEBUS signals having first and second logic values, respectively, when the module is gaining access to the bus and first and second logic values, respectively, in response to the module gaining access to the bus; 46. A bus system having a bus route capture circuit according to claim 45, further comprising means for generating a bus route capture circuit. 47. A bus system having a bus path capture circuit according to claim 46, further comprising means for generating signals MINE and MINE- in response to the GETBUS and LOSEBUS signals. 48, generating round robin request signals RREN and RREN- having first and second logical values, respectively, when a round robin request is occurring; otherwise having second and first logical values; 41. A bus system having a bus route acquisition circuit according to claim 40, further comprising means for determining the bus route acquisition circuit. 49, in response to the RQ and RREN signals, generates a "round robin request signal" having a second logic value when the module is seeking round robin priority access to the route and a first logic value otherwise; 49. A bus system having a bus route acquisition circuit according to claim 48, comprising means for. 50. The route system capture circuit further includes a circuit for ORing the "round robin request signals" from the modules to generate a "composite round robin access" signal (RREQ-), R.R.E.Q.
50. A bus system having a bus route capture circuit according to claim 49, further comprising means for generating a route module capture request signal in response to the -, RQ, RREN and RREN- signals. 51. to generate a route module capture request signal: (a) means for ANDing the RREN and RQ signals; and (b) means for ANDing the RQ, RREQ-, and RREN- signals. 51. A bus system having a bus route capturing circuit according to claim 50, further comprising: (c) means for calculating a negative sum (NOR) of the logical product output. 52, comprising means for generating a high priority signal (HPEN) that takes a first logical value if the module requests high priority access to the route; otherwise, a second logical value; A bus system comprising the bus route capture circuit according to claim 48. 53. Claims comprising means for generating, in response to the HPEN and RQ signals, a "high priority request" signal having a second logic value when the module is requesting high priority access to a route. A bus system comprising the bus route capture circuit according to item 52. 54. The route system capture circuit further comprises circuitry for ORing the "High Priority Request" signals from the modules to generate a "Composite High Priority" signal (HREQ-);
The bus capture circuit further includes RREQ-, HREQ-, RQ,
54. A bus system having a bus route capture circuit according to claim 53, further comprising means for generating a route module capture request signal in response to the RREN, RREN- and HPEN signals. 55, to generate a path module capture request signal: (a) means for ANDing the RREQ-, HREQ-, RQ, and RREN- signals; (b) ANDing the HREQ-, RQ, and RREN signals; (c) means for calculating the logical product of the RQ and HPEN signals; and (d) means for calculating the negative sum of the output of the logical product. bus system with 56. A bus system having a bus route capture circuit according to claim 50, comprising flip-flops for generating signals RREN and RREN- in response to signals RREQ- and GETBUS. 57. A bus system having a bus system path capture circuit as claimed in claim 52, comprising a flip-flop for generating the signal HPEN in response to a signal from the module. 58. Claim 4 comprising means for inverting the RQ signal to generate a path module capture request signal.
A bus system comprising the bus route capture circuit according to item 5. 59. A bus system having a bus path capture circuit according to claim 47, comprising flip-flops for generating signals MINE and MINE- in response to signals GETBUS and LOSEBUS. 60, Claim 3 for connecting with the first path
a first bus capture circuit according to claim 7; a second bus capture circuit according to claim 37 for connection with the second route; 32-bit route data; and 5-bit route function. code, i.e. a function field and an 8-bit route identification code;
That is, in a bus system having a module with means for generating an ID field, 5 bits of path parity information and a 2 bits of path acknowledgment code, one of said parity bits is for the ID and function fields. an even parity bit, the second parity bit is an even parity bit for data bits 31-24, the third parity bit is an even parity bit for data bits 23-16, and the fourth parity bit is an even parity bit for data bits 23-16. A bus system having a module, characterized in that the bits are even parity bits for data bits 15 to 8, and the fifth parity bit is an even parity bit for data bits 7 to 0. 61, comprising means for receiving, via a path, a function code for reading and writing data from a memory means arranged in the module, and a function code for reading or writing data, said function code comprising: For reading, the function code has the following 5 bits: 10000 Memory reading: 1 word 10001 Memory reading: 2 words 10010 Memory reading: 3 words 10011 Memory reading: 4 words For writing, the function code has the following 5 bits, 10100 61. A bus system having a module according to claim 60, having memory writes: 1 word 10101 memory writes: 2 words 10110 memory writes: 3 words 10111 memory writes: 4 words. 62. The at least one module further comprises means for generating an acknowledgment signal two bus system operating cycles after the bus data item has been placed on the at least one path. bus system. 63. In a bus system having modules connected to a bus route for transmitting data, function codes, identification codes and parity information between connected modules, the bus route: (a) transmits route data; 32 route lines for (
(b) five route lines for transmitting a route function code; (c) eight route lines for transmitting a route identification code; and (d) five route lines for transmitting route parity information. (e) four route acquisition lines for transmitting route acquisition signals; and (f) two route acknowledgment lines for transmitting route acknowledgment codes. . A bus system having a module further comprising means for generating an acknowledge signal two bus operation cycles after sending a bus data item onto the path.