JPS6387655A - Code modulating method - Google Patents

Abstract

PURPOSE:To reproduce a carrier component with a stable phase by setting 2n-number of modulating bits to a repeat pattern of n-number of times of '1' and '0' if a bit of original data is '0' and inverting polarities of a prescribed number of continuous pairs of modulating bits except both end parts of said repeat pattern if the bit of original data is '1'. CONSTITUTION:2n-number of modulating bits, for example, (2X12)-number of modulating bits are assigned to each bit of original data. If the data bit is '0', 2n-number of modulating bits are set to the repeat pattern of n-number of times of '1' and '0'; and if the data bit is '1', polarities of pairs of modulating bits of this repeat pattern are inverted. Consequently, the repeat pattern of n-number of times of '1' and '0' is fundamental whether the data bit is '1' or '0', and this repeat pattern is preserved as the carrier component. Consequently, the frequency of the carrier component of a modulated signal is allowed to coincide with a wobbling frequency to record data of the time code as a pregroup of an optical disk. Thus, the carrier component is reproduced with a stable phase.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a code modulation method that is applied to record a time code as a wobbling group for tracking servo on an optical disk, for example. Regarding.

[Summary of the invention]

In this invention, in a modulation method in which 2n modulation bits are assigned to each bit of original data for modulation, bit "0" of original data is 2n modulation bits "1" and "O".
The pattern is repeated n times, and bit ``1'' of the original data
”, by reversing the polarity of two predetermined continuous modulation bits excluding both ends of this n-time repeated pattern, the carrier wave component can be extracted with a stable phase.

[Conventional technology]

When modulating original data with a low bit rate, PSK is a modulation method that can preserve the carrier wave component of a predetermined frequency.
(Phase 5hift Keying)jttl
J is known. . The PSK modulation is 18 times corresponding to "l" and "0" of the binary original data shown in FIG. 12A.
Sine wave signals with phases different by 0° are assigned, and the modulated signal shown in FIG. 12B is obtained. This PSK modulation is currently widely used in fields such as telephone communications.

As is clear from FIG. 12B, in the PSK modulated signal, the phase of the carrier wave component changes depending on the original data, and the phase is not continuous.

[Problems to be solved by the invention] For example, in optical discs, tracking servo requires
The wobbling pre-group (guide 'a') is
) is formed, and the frequency components corresponding to the pre-groups included in the reproduced signal are separated and subjected to synchronous detection to obtain a tracking error signal. As this pre-group,
When recording data that changes at a low frequency, it is necessary to preserve the above-mentioned wobbling frequency component and to be able to reproduce the wobbling frequency component with a stable phase. However, using conventional PSK modulation,
Since the phase of the modulated signal becomes discontinuous, it cannot be applied to the case where data is recorded as a pregroup, as described above.

Therefore, an object of the present invention is to provide a code modulation method that can preserve the frequency components of a carrier wave and can reproduce the carrier wave components with a stable phase.

[Means for solving problems]

In this invention, in a modulation method in which 2n modulation bits are assigned to each bit of original data in which multiple bits of information are repeated at a predetermined frequency, when the original data bit is o'', the 2n modulation bit is “1”, “0”
When the bit of the original data is "1", the polarity of two predetermined consecutive modulation bits excluding both ends is reversed with respect to the repeating pattern of "1" and "0". be done.

[Effect]

An example of 2n modulation bits for each bit of the original data, t (
2x12) modulation bits are allocated.

When the data bit is “0”, the 2n modulation bit is “1”
, "0" repeating pattern n times; when the data bit is "1", the polarity of the two modulation bits is inverted with respect to the repeating pattern of 1", "-o". Therefore, the data bit Regardless of whether it is "1" or "0", the basic pattern is a repeating pattern of "1" and "0" n times. This repeating pattern is stored as a carrier wave component.

Therefore, by matching the frequency of the carrier wave component of the modulated signal with the wobbling frequency, time code data can be recorded as a pregroup on the optical disc.

〔Example〕

An embodiment of the present invention will be described below.

This description is given in the following order.

36 Time code and modulation rules, modulation circuit C, pregroup formation d, wobbling signal generation circuit e, disk recording/reproducing circuit f, modification 39 Time code and modulation rules In this embodiment, a spiral pregroup When a pre-group (guide groove) is wobbled and formed on an optical disk and trasoking is performed using this pre-group, a time code is recorded on the pre-group itself. As this time information, an absolute time code used in CDs (compact discs) is used. This absolute time code has a one-to-one correspondence with the scanning position of the optical disk head (pink amplifier), and provides information on the disk diameter when rotating the optical disk using the CLV (constant linear velocity) method. Provides address information at the time of access.

A signal is recorded on a CD using 588 channel bits as one frame, and the frame frequency at a predetermined linear velocity is 7.35 (kHz). On the CD,
A space (user's information or subcode) is provided in which information other than music signals can be recorded. The subcode consists of 8 independent bits (referred to as PQR3TUVW), and currently two channels, P and Q, are used. The above eight independent bits are EFM modulated and inserted into the l frame. Each channel of the subcode is composed of 98 bits included in each 98 frames as one block.

In the music signal and in the data of channel Q in the lead-out track, “AM I N” “ASEC
An absolute time code called "APRAME" is inserted. The absolute time code is set as "00 minutes OO seconds 00 frames" at the start of the program area, and changes according to the running time of the disc. From the above-mentioned frame frequency, for CD, it is (1 second - 75 frames). Each minute and second of the absolute time code, each frame is BC
It is expressed by two digits of D code. In other words, minutes and seconds are (
00-59), and the frame is (00-74).
), and a total of six characters of the BCD code are used.

EFM (Eig) as channel coding
ht to Fourteen Modulation
) converts one signal of 8 hits into 14 hits each according to a predetermined rule. EFM narrows the occupied frequency band, increases the number of clock components, and reduces the number of DC components.

On the other hand, in the tracking method in which the pre-group wobbles, a 22.05 (kHz) sine wave is used. Therefore, as a wobbling pregroove, CD
When recording an absolute time code of a format, it is necessary that a sine wave signal of the above-mentioned frequency can be reproduced with a stable phase. In this example, (22,05X2=
Absolute time factor modulation is performed based on the sampling frequency of 44.1 (k)lz]).

Since the frequency of change in the absolute time code is 75 (H2), in the case of a sampling frequency of 44.1 (kHz), 588 samples are included in one cycle.

A predetermined number, for example, 24 samples (2×12 modulation bits) is allocated to 1 bit of absolute time code data of 6 BCD characters of 4 bits each (24 bits in total). As shown in Figure 4A, 588 samples (-1/75
A preamble with a length of 12 samples is added to the beginning of (seconds), followed by data of (24×24=576) samples.

Each of one data bit "0", "1" and the preamble is modulated as shown in FIG. 4B. The data bit "0" is modulated into a series ("0" series) in which 24 samples alternately repeat high level and low level. For data hit "1", the 12th sample of 24 samples goes from low level to high level, the 13th sample goes from high level to low level, and the other samples are the same as data bit "0". sequence (“1” sequence). Further, the preamble has a pattern in which a high level and a low level are alternately repeated every three samples. The data bit "0" is modulated into a DC-free sequence. This series has a repetition frequency of 21.0
5 (kHz) and includes a sine wave component for tracking control. The “1” series corresponding to the data hit “l°” is also DC-free, and the run length is limited to two samples.
The "0" series, which corresponds to ", is more preferable than the "1" series in terms of the sine wave component for tracking control. Regarding the absolute time code, "0" is better than "1". Since the continuous length is longer, the "0" sequence is preferred over the "l" sequence.The sequence corresponding to the preamble is also DC-free and occurs once every (1/75) second.

A method of actually generating the "1" sequence and the preamble sequence will be explained with reference to FIG.

As shown in Figure 5A, the 24 samples of the series “1” are
0” series by adding a ternary signal that becomes (+1) at the 12th sample and (-1) at the 13th sample. The series is “0” as shown in Figure 5B.
It is formed by adding to the series signals that are (+1) at the 8th and 14th samples, and (-1) at the 11th and 17th samples.

b. Modulation circuit As mentioned above, FIG. 1 shows an example of a modulation circuit that modulates each data bit "0" or "1" into a series of 24 samples in a predetermined pattern.

In Figure 1, 1 is the frame frequency (75 (Ilz)
The input terminal 2 is supplied with the frame pulse A of 44.
This is an input terminal to which a clock pulse B having a frequency of 1 kHz is supplied. The period of clock pulse B is represented by T. 31JA and 3B show frame pulse A and clock pulse B, respectively.

Clock pulse B is applied to T flip-flops 7, 3 and 12.
This is used as the clock input for the digit counter 4. The T flip-flop 3 generates a "0" series C with a period of 2T as shown in FIG. 3C. Frame pulse A is supplied to these T flip-flop 3 and hexadecimal counter 4 as a clear input.

The frame pulse A is supplied as the cent input of the SR flip-flop 5, and the carry output of the hexadecimal counter 4 is supplied as its reset input. Therefore, at the output terminal ζ of the SR flip-flop 5, a pulse signal which becomes low level in a period of 127 from the frame pulse A is obtained as shown in the third diagram. This pulse signal is AN
The signal is supplied to the D gate 6 and the edge detection circuit 7. AND
A clock pulse B is supplied to the gate 6, and the clock pulse passed through the AND gate 6 is supplied to the 24-base counter 8. The carry output E of the 24-decimal counter 8 clears the 24-decimal counter 8, and the carry output E is supplied to the adder circuit 9.

As shown in FIG. 3E, the carry output E of the 24-digit counter 8 is 24T after the pulse signal becomes high level.
Occurs every time. Further, a pulse signal that coincides with the rising edge of the pulse signal is generated from the edge detection circuit 7,
This pulse signal is supplied to the adder circuit 9. Therefore, the pulse signal (2) from the adder circuit 9 is generated every 247 times after the 12T period of the preamble, as shown in (2) in FIG.

The parallel outputs of the 24-ary counter 8 are supplied to a decoder 10. The output signal of the decoder 10 that is generated when the content of the 24-decimal counter 8 becomes 12 is supplied to (1) the generation circuit 11, and the output signal of the decoder 10 that is generated when the content of the 24-decimal counter 8 becomes 13 is (- 1) Supplied to the generation circuit 12. Therefore, (1) the pulse signal F of level 1 is generated from the generation circuit 11 as shown in FIG.
) A pulse signal G having a level of (-1) is generated from the generating circuit 12 as shown in FIG. 3G. These pulse signals F
and G are added by the adder circuit 13, and the output signal of the adder circuit 13 is supplied to the adder circuit 14.

The adder circuit 14 receives “0” from the T flip-flop 3.
Since the series C is supplied, the output signal of the adder circuit 14 is “
1” series.

These “0” series and “1” series are connected to the switch circuit 15.
are supplied to the two input terminals of . Switch circuit 15
is controlled by the switching signal K from the switching signal generating circuit 18, and data from the switching circuit 15 is supplied to the combining circuit 20.

The synthesis circuit 20 adds a 12 sample preamble to every 588 samples. The preamble is formed by a 3(1fi') logic signal generation circuit 16 and an adder circuit 17 to which the frame pulse A is supplied.The ternary logic signal generation circuit 16 receives the frame pulse A three-value pulse signal H (0100-100100-10) is generated in synchronization with A. This pulse signal H and the "0" series C are supplied to the adder circuit 17, and a preamplule is obtained from the adder circuit 17. It will be done.

A modulated sequence is obtained at the output terminal 21 of the combining circuit 20.

Reference numeral 19 denotes an absolute time counter that generates an absolute time code of the CD formant based on the frame pulse A.

FIG. 2 shows the structure of the absolute time counter 19, in which each frame and 2 minutes of a second consists of two BCDs. Figure 2 shows
An example of "28 minutes 34 seconds 63 frames" is shown, and in this case, r (0010) (1000) (001
1) (0100) (0110) (0011) J
Six characters of OBCD are occurring. The absolute time code from the absolute time counter 19 is supplied to the switching signal generation circuit 18. In the switching signal generation circuit 18, each data bit of the absolute time code is taken in in synchronization with the pulse signal I, as shown in FIG. A high-level switching signal K (K in FIG. 3) is generated. When the switching signal K is at a low level, the "O" series is selected by the switch circuit 15, and when the switching signal K is at a low level, the "1" series is selected by the switch circuit 15.

C. Formation of pre-groups A cutting system for forming pre-groups on an optical disc is shown in FIG. In FIG. 6, 25 indicates a glass disk, and a photoresist 2 is placed on the glass disk 25.
6 is applied. The glass disk 25 is rotated by a spindle motor 27 at CLV. 28 is a recording laser such as an argon ion laser. Recording laser 2
A laser beam from 8 is reflected by a galvanometer mirror 30 of an optical radar 29 surrounded by a broken line, and is irradiated onto a photoresist 26 through an objective lens 31. Galvano mirror 3
0 is rotated by the galvano motor 32, so that the laser beam wobbles in the radial direction.

A drive signal from a mirror driver 33 is supplied to the galvano motor 32 . A wobbling signal is supplied to the mirror driver 33 from a wobbling signal generation circuit 34 . The wobbling signal generation circuit 34 is composed of the above-mentioned modulation circuit and a band-limiting filter.

A spiral and wobbled pre-group is exposed to the photoresist 26 by a laser beam.

In FIG. 7, ▪ indicates an optically cut glass master, and when developed, recesses corresponding to the pre-groups are formed in the photoresist 26, as indicated by ▪. Next, aluminum 35 is deposited on the photoresist 26 (■). Furthermore, nickel plating 36 is applied (
■) A metal master is produced by peeling off the nickel plating 36 (■). A stamper is made from this metal master, and the optical disc 41 is manufactured through the steps of injection molding using the stamper, recording layer formation, and protective film addition (2). The optical disc 41 includes a polycarbonate substrate 37, a recording layer 38, and a transparent protective film 39, and a pre-group 40 is formed in the recording layer 38. If necessary, the optical disc 41 may have a laminated structure to enable double-sided recording.

The recording layer 38 is made of a material such as 5bSe or B1Te in the case of a write-once (WORM) optical disk, and is made of T b in the case of an erasable optical disk, such as a magneto-optical disk.
It is made of material such as Fe Co. Further, the present invention can also be applied to a phase change type optical disk that utilizes a crystal-amorphous phase change. The pre-group 40 has a Us or V groove, and a focus is formed on the pre-group 40 or in a region between the pre-groups. FIG. 8 shows a part of the pre-group 40 formed on the optical disc 41. As shown in FIG. The diameter of the optical disc 41 is the same as that of a CD.

d. Wobbling signal generation circuit FIG. 9 shows a wobbling signal generation circuit, and 45 is:
This is the modulation circuit shown in FIG. 1 mentioned above. The modulation circuit 45 generates a pulse train modulated with an absolute time code in CD format. This pulse train is 22.05 (k
Basically, the pulse train has a repetition frequency of Hz), and the pulse train is passed through a filter to limit the band. Bandwidth limitation towards the low frequency side is necessary to suppress interference with the tracking error signal, and band limitation towards the high frequency side is necessary in order to suppress interference with the EFM modulation signal (return data).

A digital bypass filter 46 connected to the modulation circuit 45 is provided to limit the band on the low frequency side, and has frequency characteristics shown at 50 in FIG. In Figure 10, fn is 22.05 (kHz
) and fs respectively represent 44.1 (kHz).

The output signal of digital bypass filter 46 is supplied to digital low-pass filter 47.

This digital low-pass filter 47 has frequency characteristics shown at 51 in FIG.

As the digital low-pass filter 47, a configuration using oversampling is used. The output signal of digital low-pass filter 47 is supplied to D/A converter 48 . The D/A converter 48 converts the high level and low level of the pulse signal into DC voltages of appropriate values.

The output signal of the D/A converter 48 is supplied to an analog low-pass filter 49. This analog low pass filter 4
9, a wobbling signal is generated. This wobbling signal is supplied to the mirror driver 33 (see FIG. 6).

e. Disc recording/reproducing circuit FIG. 11 shows an example of a disc recording/reproducing circuit. CD
An optical disk 41 of the same size as the spindle motor 5
It is rotated by CLV by 5.

Various types of optical heads are known, but in this example, a focus adjustment section and a tracking control section 3 are used.
An optical head incorporating both of the 11 parts is used.

The optical head includes a semiconductor laser 56. Collimator lens 57
．． Heemsplinota 58. Z wavelength plate 59° objective lens 6
0. An actuator 61 consisting of a coil and a magnet that moves the objective lens 60. It consists of an optical sensor 63 to which a laser beam from a beam splitter 58 is applied via a cylindrical lens 62. A drive signal is supplied to the semiconductor laser 56 via a recording/reproducing switch 64 .

The recording data from the terminal 65 is supplied to the recording circuit 66,
A recording signal from the recording circuit 66 is supplied to the semiconductor laser 56 through the recording side terminal r of the recording/reproduction changeover switch 64. The recording circuit 66 is a circuit that adds a redundant code of an error correction code.

An EFM modulation circuit, a recording timing control circuit, etc. are provided. When reproducing the optical disc 41 , a predetermined DC voltage 67 is supplied to the semiconductor laser 56 via the reproducing side terminal p of the recording/return switch 64 .

The return beam from the optical disk 41 is sent to the beam splinter 5
8 and a cylindrical lens 62 to illuminate the optical sensor 63 . The optical sensor 63 has a four-part detector configuration. The output signal of each sensor of the optical sensor 63 is A
, B, C, D, the addition circuit 68 calculates ((A+B
) + (C + D)) is formed, and the subtraction circuit 69 generates ((A + B) - (C + D>)
A focus error signal represented by is formed.

This focus error signal is transmitted to the force search circuit 70.
A focus servo control signal is supplied to the actuator 61.

The main reproduction signal from the adder circuit 6 is sent to the waveform shaping circuit 7.
1 and a bandpass filter 72. In the waveform shaping circuit 71, the reproduced signal is converted into a pulse signal,
This pulse signal is supplied to the EFM demodulation circuit 73. E
The reciprocating signal from the FM demodulation circuit 73 is sent to the data processing circuit 74.
supplied to

Reproduction data obtained from the data processing circuit 74 is supplied to an optical disk control circuit provided between the optical disk drive device and the computer.

The band-pass filter 72 is (22,05(kH2)±
It has a passband of 900[)1zll), and components of the reproduced signal corresponding to the pregroup are separated by a bandpass filter 72, and the output signal of the bandpass filter 72 is supplied to a synchronous detection circuit 75 and a waveform shaping circuit 79. Ru. The synchronous detection circuit 75 has a voltage of 22.05 (kHz) from the terminal 76.
z) is supplied. The output signal of the synchronous detection circuit 75 is supplied to a low-pass filter 77, and a tracking error signal is extracted from the low-pass filter 77.

This tracking error signal is supplied to the tracking servo circuit 78, and the tracking servo circuit 78 gives a tracking control signal to the actuator 61.

The waveform shaping circuit 79 provides a pulse train modulated with an absolute time code in CD format.

This pulse train is supplied to the demodulation circuit 80, and the demodulation circuit 80
At , the pulse train is demodulated into absolute time code data bits. The absolute time code obtained from the demodulation circuit 80 is supplied to a system controller (not shown) of the optical disk drive device, and is used to control the CLV servo of the spindle motor 55, the scanning position of the optical head during a seek operation, etc.

f. Modifications The present invention is applicable not only to CD formant time codes but also to the case where other SMPTE time codes or digital data other than time codes are modulated and recorded.

Further, according to the present invention, information such as a time code may be superimposed on signals other than the pregroup signal of the optical disc.

〔Effect of the invention〕

According to the invention, the predetermined frequency, for example 21.05
It is possible to realize a code modulation method that can preserve the [kHz], transmit other information such as a time code, and reproduce with a stable phase.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a modulation circuit for modulating an absolute time code into a pulse train in one embodiment of the present invention, and FIG.
The figure shows a block diagram of a force counter that generates an absolute time code.
Figure 3 is a time chart for explaining the operation of the modulation circuit.
Figures 4 and 5 are waveform diagrams used to explain the modulation rules and modulation method, Figure 6 is a route diagram showing the configuration of the cutting system, and Figures 7 and 8 are route diagrams showing an example of the optical disc manufacturing method. FIG. 9 is a block diagram of an example of a wobbling signal generation circuit, FIG. 10 is a frequency spectrum diagram used to explain band limitation in the wobbling signal generation circuit, and FIG. 11 is a recording/reproduction of an optical disc. A block diagram of an example of the circuit, FIG. 12 is a conventional P
FIG. 3 is a waveform diagram used to explain SK modulation. Explanation of main symbols in the drawings 1: Frame pulse input terminal, 2: Clock pulse input terminal, 4: Decimal counter, 8: Quadrilateral counter, 15: Switch circuit, 16: Three-value logic signal generation circuit, 19: Absolute time counter, 26: Photoresist, 34: Wobbling signal generation circuit, 4
0 nibli groove, 41: optical disc, 46: digital bypass filter, 47: digital low-pass filter, 72: band-pass filter, 75: synchronous detection circuit. Agent Patent Attorney Tadashi Sugi Yu = ・Hai Imoku =

Claims (4)

[Claims] (1) In a modulation method in which 2n modulation bits are assigned to each bit of original data in which multiple bits of information are repeated at a predetermined frequency, when the bit of the original data is “0”, the 2n modulation The bit is “1”, “
When the bit of the original data is "1", two predetermined consecutive modulation bits excluding both ends of the repeating pattern of "1" and "0" are used. A code modulation method characterized in that the polarity of the code is inverted. (2) The code modulation method according to claim 1, wherein the original data is a BCD code. (3) In the code modulation method according to claim 1, the value obtained by dividing the bit frequency of the modulation bit by the predetermined frequency is the number of modulation bits obtained by subtracting an integral multiple of the number of plural bits from the divisor. 1. A code modulation method characterized in that one preamble code is provided for each cycle of the predetermined frequency by assigning the preamble code to a preamble code. (4) The code modulation method according to claim 3, wherein the preamble code does not have a DC component.