JPS6386196A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent the lowering of writing voltage by constituting a column selecting circuit of an N channel type MOS transistor for reading and a P channel type for writing. CONSTITUTION:In a program mode, a program mode signal PM goes to a high level, and a read mode signal RM goes to a low level, and an N channel MOS transistor (N-MOS) 18 and read column selection N-MOS 271-27n go to a off state. When a data inversion Gin for program is '1', a P channel type MOS transistor (P-MOS) 29 is turned on. Thereby, high voltage is applied from a high voltage power source VPP to a column signal line 14j through the P-MOS 29 and column selection P-MOS 281-28n, and data '0' is written in a memory cell 12ij. By such a constitution, the lowering of level due to a threshold voltage is eliminated and the efficiency of writing can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device, and particularly relates to a write operation of a programmable read-only memory (ROM).

(Prior Art) Generally, programmable read-only memory (
FROM) is configured as shown in FIG. 6, for example. In FIG. 6, 11 is a memory cell array, and this memory cell array 11 includes floating gate type MOS transistors 1211 to L2m n as memory cells.
are arranged in a matrix. The above floating gate type MOS transistors 1211 to 12m
Each control gate of n is connected to a row signal line 13, ~13m for each row, and each drain is connected to a column signal line 14□~14n for each column.
are connected, and a ground point is connected to each source. The output ends of the row decoder 15 are connected to the row signal lines 131 to Hm, and the column selection circuit 16 is connected to the column signal lines 141 to 14n. This column selection circuit 16 includes decode outputs A1 to An of a column decoder (not shown).
Column selection MOS transistor 171 whose conduction is controlled by
~17n, these MOS transistors 171~
Each of the column signal lines 141 to 1 is connected to one end of 17n.
4n are connected, and the other ends are commonly connected. One end of a MOS transistor 18 for reading (reading) and a MOS transistor 19 for writing (programming) are each connected to this common connection point. MO5 for the above lead
The other end of the transistor 18 is connected to the input end of the sense circuit 20 and also to the power supply VCC via a resistor 21, and conduction is controlled by a read mode signal RM.

On the other hand, the other end of the programming MOS transistor 19 is connected to a high voltage power supply Vpp, and conduction is controlled by the output of the programming gate circuit 22. This programming gate circuit 22 has an operating power supply of Vl)p and an output terminal of the above-mentioned M
It is composed of a buffer circuit 23 connected to the gate of the OS transistor 19, and an AND gate 24 whose output terminal is connected to the input terminal of the buffer circuit 23 and which takes the logical product of the program mode signal PM and the program data D1n.

In the above configuration, the read mode signal RM is 1
When the program mode signal PM is at the "02 level," the MOS transistor 18 is on, the MOS transistor 19 is off, and the memory cell 12i selected by the row decoder 15 and column decoder
j(i-1~m.

The data read from j-1 to n) is sent to the sense circuit 20.
supplied to Then, amplification is performed in this sense circuit 20, and read data Dout is obtained from its output terminal.

On the other hand, when the program mode signal PM is at the "1" level and the read mode signal RM is at the "0" level, the MO
The S transistor 18 is turned off, and when the data Din is "1", the output of the AND gate 24 is set to the "1" level, and the MOS transistor 19 is turned on. As a result, the high voltage power supply Vl)I) is connected to the MOSl-transistor 19 and the column selection MOS transistor 17j selected by the column decoder and turned on.
A high voltage is applied to the column signal line 14j via (j-1 to n).
is applied to Then, data "0" is written into the memory cell 12ij located at the intersection of the row selected by the row decoder 15 and the column selected by the column decoder. On the other hand, the program mode signal PM is “1”
When the read mode signal RM is at the "0" level and the data Din is at "θ", the output of the AND gate 24 is at the "0" level, and the MOS1-transistor 19 is turned off. At this time, hi os + - transistor 1
8 is also in the off state. Therefore, the row decoder 15
Memory cell 12 selected by and column decoder
No high voltage is applied to ij, and data "1" is written.

FIG. 7 focuses on the case where one memory cell is programmed in the circuit of FIG. 6, and shows necessary MOS transistors extracted.

When programming data "0#" to the FROM memory cell 12ij, it is done as follows.That is, the programming MOS transistor 19, the column selection MOS
The gate potential of the transistor 17j and the memory cell 12ij is set to a level (21v or 12.5V) below Vl), and each MOS transistor 19.17j, 12i
Set j to on state. As a result, a current I flows from the high voltage power supply Vl)p connected to the drain of the programming MOS transistor 19 to the source (ground point GND) of the floating gate type MOS transistor 12ij as a memory cell, and this current The hot carriers (electrons) induced by
2ij floating gate. This state is the state in which data 'O'' is written into the memory cell 12ij.On the other hand, when the gate potential of the programming MOS transistor 19 is set to the GND level, the column selection M
Even if the gate potential of OS transistor 17j and the control gate potential of memory cell 12ij are at the vpp level, MOS transistor 19 is turned off, so no current flows from high voltage power supply vpp to memory cell 12ij. As a result, no electrons are injected into the floating gate of the memory cell 12ij, and the write data becomes "1".
m. Note that in the above description, the MOS transistors 19, 17j and 12i j are all described as N-channel MOS FETs.

FIG. 8 shows the circuit shown in FIG. 7 rewritten to the state when data "0" is programmed. MO for program
A high voltage V is applied to the gate and source of the S transistor 19.
pI) is applied, this MOS transistor 19 is in an on state. At this time, the drain potential Va of the MOS transistor 19 does not reach the vpp level, and if the MOS transistor 19 is an enhancement type and its threshold voltage is VTHN, then rV a ≦vpp−Vt o N J teal. Actually, drain potential Va and substrate voltage (GND
), the apparent upper threshold voltage of the MOS transistor 19 increases due to the back gate bias effect, and the drain potential VaharVpp
-Vt HN J It is lowered. The drain potential vb of the master/column selection MOS transistor 17j is approximately equal to the above-mentioned Va, and as a result, the potential Va is applied to the source of the memory cell 12ij. At this time, if the level of the high voltage power supply Vl)I) is sufficiently high, there is no particular problem with programming. However, in recent years, there has been a trend towards lowering the level of the high voltage power supply vpp. This is because if a high potential signal line runs inside the LSI, the LSI
This is because it accelerates the deterioration inside I and causes latch-up in CMO8-LSI. Another factor is that it is necessary to generate a high voltage externally, but it is difficult to generate this high voltage. As described above, when the level of the high voltage type RV pp is lowered, it becomes necessary to flow a current sufficient to generate hot carriers between the source and drain of the memory cell 12ij even at a low voltage. For this purpose, the column selection MOS transistor L7j
It is necessary to make the drain potential vb as close to the vpp level as possible. However, as mentioned above, the program MO
A drop in potential by the threshold voltage VTHN of the S transistor 19 is unavoidable. For this reason, memory cell 12
The current between the source and drain of ij also decreases, resulting in poor efficiency when writing "Oo" into the memory cell.

(Problems to be Solved by the Invention) As described above, in conventional semiconductor memory devices (FROM), the write voltage decreases by the threshold voltage of the programming MOS transistor, so the current between the source and drain of the memory cell decreases. There is a drawback that efficiency is low when writing "0" to a memory cell.

This invention was made in view of the above circumstances, and its purpose is to be able to supply sufficient current to memory cells even when the write voltage is relatively low, and to improve the efficiency when writing "0". An object of the present invention is to provide a semiconductor memory device that can improve the performance.

[Structure of the invention] (Means and effects for solving the problem) That is, in this invention, in order to achieve the above object, a P-channel type MOS transistor is provided as a MOS transistor for selecting a program mode. In addition, two types of circuits are provided as column selection circuits, one for read mode and one for program, and the read mode is configured with an N-channel MOS transistor and the program mode is configured with a P-channel MOS transistor. This is to prevent the write voltage from decreasing due to the threshold voltage.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. In FIG. 1, the same components as in FIG. 6 are denoted by the same reference numerals, and the memory cell array II is formed by floating gate MO5 transistors 121, 12m, . Ru. Each control gate of the floating gate type MOS transistors 1211 to 12mn is connected to a low signal line 13. .about.L3m are connected, column signal lines 141 to 14.OMEGA. are connected to each drain for each column, and a ground point is connected to each source. And the low signal lines 131 to 13
The output terminal of the row decoder 15 is connected to m.

Further, a column selection circuit 25 for reading and a column selection circuit 26 for writing are connected to the column signal lines 141 to 14n, respectively. The read column selection circuit 25 is composed of N-channel type MO5I-transistors (read column selection MOS transistors) 271 to 27n whose conduction is controlled by decode signals A1 to An output from a read column decoder (not shown), and these MOS The columns (λ return lines 141 to 14n) are connected to one end of the transistors 271 to 27n, respectively, and the other ends thereof are commonly connected. On the other hand, the write column selection circuit 2G receives a decode signal of a write column decoder (not shown). P-channel type M whose conduction is controlled at 81~BΩ
It consists of OS transistors (write column selection MOS transistors) 281-28n, one ends of which are connected to the column signal lines 141-L4n, respectively, and the other ends are commonly connected. The read column selection MOS transistors 26, -
One end of the N-channel type MOS I-transistor 18 for reading is connected to the common connection point on the other end side of the writing column selection MO3I-transistor 28.28n. One end of a P-channel type MOS transistor 29 for writing (programming) is connected to the common connection point on the other end side of 28n. The other end of the read MOS transistor 1a is connected to the input end of a sense circuit 20, and is also connected to a voltage gVcc via a resistor 21, and conduction is controlled by a read mode signal RM. On the other hand, the other end of the programming MOS transistor 29 has a high voltage of 7I.
'' source Vpp is connected, and this MOS transistor 29 is rendered conductive by the output of the buffer circuit 23 whose operation Tx J4 is ■pp. The input terminal of this buffer circuit 23 is a program mode signal PM and program data D1.
The output terminal of a Nandt gate 30 that takes the AND of n is connected.

Next, the operation in the above configuration will be explained. First, during a read operation, the read mode signal RM is “1”.
level, the program mode signal PM becomes "02 level," the MOS transistor 18 is turned on, and the MOS transistor 29 is turned off.At this time, one of the outputs A1 to An of the read column decoder (not shown) is "02".
1" level, and the selected MOS transistor 27j (j-1 to n) among the read column selection MO3 transistors 27. to 27n is turned on. At this time, the decode outputs B1 to Bn of the write column decoder are All of the memory cells 12ij (i-1 to m, j-1 to
The data read from n) is supplied to the sense circuit 20. The sense circuit 20 amplifies the read data, and outputs the read data D ou from its output terminal.
get t.

On the other hand, in the write mode, the program mode signal PM is at the "1 level" level, the read mode signal RM is at the "0" level, and the outputs of the read column decoders are all at the GND level, so that the MOS transistors 18,
and read selection MO3 transistors 271-27n
All are turned off. Here, when the program data Din is “1”, the output of the Nantes gate 30 is “1”.
The level reaches θ''' level and the MOS transistor 19 is turned on.

As a result, a high voltage is applied to the column signal line 14j from the high voltage power supply Vl) through the MOS transistor 29 and the write column selection MOS transistors 28j (Cj-1 to Cj-n) selected by the write column decoder and turned on. applied. The memory cell L2ij is located at the intersection of the row signal line 13i in the row selected by the row decoder 15 and the column signal line 14j in the column selected by the write column decoder.
Data “0” is written to. On the other hand, the program mode signal PM is at the “1° level,” and the read mode signal RM is at the “1° level.”
0" level, and when the data Din is "0", the output of the Nant gate 30 becomes "1" level, and the MOS transistor 29 is turned off. At this time, the MOS transistor 18 is also turned off. , the high voltage vpp is not applied to the memory cell 12ij selected by the column decoder for writing and the row decoder 15, and no writing is performed (data "1" is written).

FIG. 2 focuses on writing "0" to one memory cell in the circuit of FIG. 1, and extracts and shows the necessary MOS transistors. GND level is applied to the gates of program MOS transistor 29 and write column selection MOS transistor 28j, and high voltage Vl)I) is applied to the back gates of these MOS transistors 29 and 283. Since the MOS transistors 29 and 28j are of P-channel type, there is no drop in level due to threshold voltage, and the drain potentials Vc and Vd of the MOS transistors 29 and 28j are respectively,
The potential is the same as Vpp, which is the source potential of the MOS transistor 29. Therefore, a high voltage Vl) is applied between the source and drain of the memory cell 12ij, and the data "O" is
Sufficient current can be obtained for writing.

The reason why two column selection circuits 25 and 26 each consisting of an N-channel type MOS transistor and a P-channel type MOS transistor are provided for reading and writing is as follows. That is, the reason why the column selection circuit 26 consisting of a P-channel MOS transistor is used for writing is to apply the pp level to the drain of the memory cell as described above.
An N-channel MOS transistor is used for reading when the source of the memory cell 12ij is at GND level (
This is because the memory cells 1211 to 12mn are of N-channel type), and this GND level is read out. GN
For reading D level, read column selection M
The OS transistor needs to be of N-channel type. This is because if it is configured with a P-channel type MOS transistor, its drain potential will not reach the GND level, and will be lower than Vt HP (VT HP H Pf + Nel type M
This is because the potential becomes higher by the threshold voltage of the transistor o S .

According to such a configuration, there is no drop in the potential of the high voltage power supply Vl) when programming "O", so the high voltage power supply Vl)
l) Writing can be performed efficiently even if the level of I) is set low. In addition, by setting the level of Vl)I) low, it is possible to prevent deterioration inside the LSI, prevent latch-up, and prevent high voltage Vp1) inside the LSI.
It is possible to simplify the circuit that generates the .

FIG. 3 shows another embodiment of the invention.

In FIG. 3, the same components as those in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted. That is, the column selection circuit 25 for reading and the column selection circuit 26 for writing in FIG. 331 to 33n. The column selection circuit 34 made up of transmissicon gates 331 to 33n operates in both read and write operation modes, and is controlled by decode signals A1 to An of a column decoder (not shown) and their inverted signals A and An. Ru.

In the above configuration, the operation is basically the same as that of the circuit shown in FIG. ) level is mainly controlled manually via a P-channel MOS transistor. Therefore, when writing data "O", the Vl)I) level is the threshold voltage VTH of the N-channel MOS transistor.
The GND level does not decrease by N, and the GND level does not increase by the threshold voltage VTHP of the P-channel MOS transistor during reading.

According to such a configuration, unlike the circuit shown in FIG. 1, there is no need for two column decoders for reading and writing, but it is sufficient to use the decoded output of one column decoder and generate its inverted signal. Therefore, the increase in pattern area due to application of the present invention can be reduced.

FIG. 4 shows another embodiment of the present invention.
The column selection circuit 25 for reading and the column selection circuit 2B for writing in the circuit shown in the figure are connected to the memory cell array ■1.
It is divided into both sides. In FIG. 4, the same parts as in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted. The reason why the memory cell array 11 is configured like this is that the memory cell array 11 is a floating gate type M
Column signal lines 141 to 14n connecting the drains of OS transistors 12,1 to 12mn are lined up at a very narrow pitch, so column selection circuits 25.2 for reading and writing If the signal line to the column decoder is N-channel type M
This is because since it is connected to two locations, the OS transistors 271 to 27n1 and the P channel type MOS transistors 281 to 28n, a large pattern area is required for this portion, increasing wasted area for wiring. Also, P
Channel type MOS transistor and N channel type MO
If an S transistor exists nearby, it becomes vulnerable to latch-up, so it is necessary to ensure element isolation between the P-channel MOS transistor and the N-channel MOS transistor (in the program mode, write column selection M
(Since a large current of several tens of mA flows through the OS transistor, a pattern that is resistant to latch-up is required.) To solve these problems, the column selection circuits 25 and 26 for reading and writing are separated.

FIG. 5 shows an example of the pattern configuration of the write column selection circuit 26 in FIG. 4. In FIG.

In FIG. 5, parts corresponding to those in FIG. ~3518 is the contact part, 361~367
is a polysilicon layer, 37. , 372 is a diffusion layer, 381
~384 is a floating gate, and write column selection MOS transistors 28□~28 are written in the area surrounded by the broken line.
4 is formed.

[Effects of the Invention] As explained above, according to the present invention, even if the write voltage is relatively low, sufficient current can be supplied to the memory cell.
A semiconductor memory device that can improve efficiency when writing 0'' can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining a write operation in the circuit of FIG. 1, and FIGS. A circuit diagram for explaining another embodiment of the invention, FIG. 5 is a bottom view of a pattern showing an example of the pattern configuration of the write column selection circuit in the circuit of FIG. 4, and FIG. 6 is a diagram showing a conventional semiconductor memory device. Circuit diagram shown, No. 7
8 and 8 are diagrams for explaining the write operation in the circuit shown in FIG. 6, respectively. 1211-12m n... Floating gate type 10S transistor (memory cell), 11... Memory cell array, 131-13m... Low signal line, 15.
...Low decoder, 14. ~14n... Column signal line, 81~Bn... Column decode signal for writing,
26...Writing column selection circuit, A, ~An...
・Column decode signal for reading, 25... Column selection circuit for reading, vpp... High voltage power supply, 29.
... MOS transistor for writing, 18... MOS transistor for reading, 331 to 33n... transfer gate. Applicant's representative Patent attorney Takehiko Suzue Figure 2 Figure 3 Figure 4 341 Skin Figure 5 Section b

Claims (3)

[Claims] (1) A memory cell array consisting of floating gate MOS transistors arranged in a matrix, a row signal line to which the control gates of these floating gate MOS transistors are connected in each row, and a row decode signal to this row signal line. a row decoder which selects the row direction of the memory cell array by supplying a column signal line to which the drains of the floating gate type MOS transistors are connected for each column; A write column selection circuit consisting of a P-channel MOS transistor whose conduction is controlled by a column decode signal, and an N-channel MOS transistor whose one end is connected to the column signal line and whose conduction is controlled by a read column decode signal. a column decoder that supplies the write column decode signal and the read column decode signal to the write and read column select circuits; and the write column select circuit. A P-channel write MOS transistor connected to the other end of each P-channel MOS transistor is turned on in a "0" program mode to supply high voltage power to a selected memory cell. Characteristic semiconductor memory device. (2) P-channel type M of the write column selection circuit
N of the OS transistor and the read column selection circuit
In each channel type MOS transistor, corresponding MOS transistors for each column are connected in parallel to form a transfer gate, and the switching of this transfer gate is controlled by a column decode signal outputted from the column decoder and its inverted signal. A semiconductor memory device according to claim 1, characterized in that: (3) The semiconductor memory device according to claim 1, wherein the write column selection circuit and the read column selection circuit are respectively arranged at both ends of the column signal line.