JPS6383849A - Address converting system - Google Patents

Abstract

PURPOSE:To ensure an access to the entire address space of an image bus by performing the conversion of addresses via an image bus controller which functions to secure connection between a system bus and an image bus. CONSTITUTION:The data is previously set to a control register 32 by a CPU 1 to decide the specific part of an address space of an image bus 10 that receives an access. While a decoder 31 decodes the higher order bits of a system address and delivers a using request for the bus 10 after the arrival of read/ write signals SRD and SWT. Here a bus arbitrating circuit 36 functions to arbitrate the using right of the bus 10 to give a permission for the use of the bus 10. As a result, buffers 37-40 are activated and the data on the lower order bits of the system address serving as the lower bits of an image address are delivered together with the data on several bits written into the register 32 as the higher order bits of the image address. At the same time, a read/write command is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Field of Industrial Application) The present invention relates to an address conversion method suitable for use in a data processing device having two independently operating buses.

(Prior art) With the advancement of man-machine interfaces, the key display devices are required to have more advanced functions year by year, and high-performance workstations that can display not only kanji characters but also advanced graphic displays and even images are becoming more and more popular. It has come to appear.

Since the above-mentioned workstations include those that require large amounts of data transfer such as images, a dedicated image bus independent of the system bus is provided in consideration of bus usage efficiency. The system bus contains the main CPU and main memory, and the image bus contains the image memory, drawing, etc.
A dedicated LSI for display is connected.

(Problems to be Solved by the Invention) In the above-described workstation system, when viewed from the CPU, it appears that part of the address space is allocated to an image bus device. This relationship is shown in FIGS. 5 to 7. Figure 5 shows the address space of the system address in the main memory (MM) area and the image bus area (
IBA), and the image bus is accessed through this IBA. In this case, if the address space of the image bus is not so large, it can be completely covered by IBA, but if the address space of the image is large, it cannot be completely covered. In other words, an image bus address space that cannot be accessed by the CPU is created.

On the other hand, FIG. 6 shows a system in which the IBA is made thicker so as to cover the entire address space of the image bus. In this case, the CPU can access the entire address space of the image log, but the disadvantage is that the memory area becomes smaller. FIG. 7 shows a system in which the shortcomings of the system shown in FIG. 5 are compensated for by puncture switching.

A part of the system address can be used as main memory or IBA- by puncture switching. When accessing the address space of the image node, the puncture is set to the IBA side and the access is made. However, this method requires complicated hardware provided on the system side.

Furthermore, when data is transferred between the main memory and the image 747 that share a puncture, the puncture must be switched each time, resulting in a reduction in processing speed.

The present invention has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to provide an address conversion method that allows access to the entire address space of an image bus without occupying the address space of the system bus.

Another object of the present invention is to provide an address translation method that simplifies the hardware configuration of a bus and prevents a decrease in data transfer speed.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a system having two independently operating buses as described above, in which a bus master connected to one bus is connected to a memory connected to the other bus. When accessing, the entire address space on the memory side can be accessed without occupying much of the address space on the bus master side. For this reason, the bus controller that connects the buses,
a decoder that decodes an address that arrives via the system bus and detects that it is an access to the image bus; a control register in which address data that determines which part of the address space of the image bus is accessed is set; Decoder output and RFAD/WRI
A gate that generates a bus use request for the image bus using the TE multiplication signal, a bus arbitration control circuit that performs bus arbitration based on the gate output and generates a bus use permission signal, and a control register output based on the signal generated here. It consists of a buffer that drives address information and commands.

(Operation) The control register contains data for determining which part of the image bus address space is accessed by the CPU.
Yes, it is preset. On the other hand, the decoder decodes the upper bits of the input system address, waits for the arrival of the READ/WRITE signal, and issues a request to use the image bus. Here, the bus arbitration circuit functions, and after arbitrating the right to use the image bus, permits the use of the bus.

This causes the puffer to be active, and the low-order bits of the system address are used as the low-order bits of the image address, and the several bits of data written to the control register are used as the high-order bits of the image address, rather than the high-order bits of the system address. Output. Also, READ/
A WRITE command is also output in the same way.

In this way, the image bus controller outputs an address command to the image bus, and the memory on the image bus is accessed. Due to this,
A CPU serving as a bus master can access the entire address space of the image bus without worrying too much about the address space of the system bus.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings. FIG. 1 is a system configuration block diagram of a high-performance workstation in which the present invention is implemented. In the figure, 9 is the system bus, 9, CPU 1 and main memory IJ (MM) 2.
is connected. 10 is an image bus to which a graphics image processor (GIP 4 ), an image memory (IMj), a frame memory (FM6), and a display controller (DCL 7 ) are connected. CPU 1 accesses main memory 2 via system bus 9 .

Further, the graphics image processor 4 accesses the image memory 5, frame memory 6, and display controller 7 via the image bus 10. The display controller 7 sequentially generates addresses for the frame memory 6 and reads the data. A video signal is generated based on this data and sent to the CRT monitor 8. The contents of the frame memory 6 are always displayed on the CRT monitor 8.
will be displayed.

By the way, the system bus 9 and the image bus IO operate independently. Both are image bus controllers (I
BC) and is provided to connect the two buses 9.10. The CPU 1 may access the image memory 5 connected to the image bus 10 and the like. At this time, the image memory 5 is accessed through a path including the CPU 1, the system bus 9, the image bus controller 3, and the image bus 10. When the image bus controller l detects that the access request from the CPU 1 is for a device connected to the image bus 10, it issues a bus release request to the graphics image processor 4. When the graphics image processor 4 releases the bus, the image bus controller 1 becomes the bus master of the image bus 10 and drives the address line and command line. WR
In the case of ITE operation, data on the system bus 9° is outputted onto the image bus 10, and conversely, in the case of READ operation, the data on the image bus 10 is outputted onto the system bus 9. In this way, CPU Z uses image bus 1
Access the device connected to 0.

FIG. 2 is a diagram showing an example of an address space according to the present invention developed on a memory. The method of the present invention is similar to the method of FIG. 5, which accesses the image bus through a relatively small image bus area (IBA), but allows access to the entire address space of the image bus. In the control register built into the image bus controller l, which will be described later,
The data written in advance determines which part of the address space of the image bus is accessed.

FIG. 3 shows the internal configuration of the Image Zobus controller. In the figure, the left side shows the system bus and the right side shows the image bus side. A decoder 31 decodes the upper part of the system bus (SA), and sets a decode signal to "1" when SA is an image bus area. 32 is a control register and outputs data arriving from the outside to the input line 308 according to the ITE signal also obtained.

33 and 34 are AND gates, and when the decode signal outputted through line 307 is "1", when the system bus read (SRD) or system bus write (sw'r) becomes 11", lines 309 and 3
Set each 10 to “1#”.

35 is an O'r gate, line 309 or line 3
When the signal propagating line 10 is @1'', the image bus use request signal propagating line 311 is set to 112.36
is a bus arbitration control circuit.

Bus arbitration control circuit 36 performs bus arbitration on the image bus use request signal, and outputs an image bus use permission signal via line 312 as a result. 37.38.3
9 and 40 are buffers. These buffers 37~
40 is an image bus use permission signal propagated through line 312. When it is "1#," the contents of lines 308.304.309 and 310 are transferred to lines 312, 314.315, respectively.
and 316, and when the image bus use permission signal on the line 312 is ``0'', the lines 313, 314.
315 and 316 are placed in a high impedance state. The signal propagated on line 313 is IA (image bus address) upper, and the signal propagated on line 314 is IA lower. The signal propagated on line 315 is IRD (image bus read), and 316 is IWT (image bus write).

In the embodiment of the present invention, the following address assignments will be considered as an example.

(1) 2 bits for SA upper 5A23 and 5122, 22 bits for SA lower (Sh; zr, 5k2o, -8Ao)
24 bits in total.

+2) IA upper (IA, 9.9.IA2.?) is 2 bits, SA lower (I A 21 , I A 20 ,
・IAO) is 22 bits, making a total of 24 bits.

(3) S A 23 = S A 22 = “1”
When , it is set as an image bus area. That is, the address space C00OOOH to FF'FFFFH of the system bus is the image bus area.

In the above example, the decoder 31 is configured with a two-man AND gate.

FIG. 4 is a conceptual diagram showing the operation of the embodiment of the present invention expanded on the memory.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail. 2-bit data is supplied to the control register 32 by the CPU 1 via line 301 and is written based on the ITE signal arriving via line 302. C
PU 1 is C00O of the address space of system bus 9.
READ or ■IT for OOa~FFFFFF
Consider the case where E is performed. The decoder 31 has 5A23=
5122 = 11'', the decode signal on the line 307 is set to ``1''.Here, when the SRD on the line 305 or the evening on the line 3θ6 becomes @1#, the gate 33.3
4, the signal propagating through line 309 and line 310 becomes "1". Here gate 35 output (line 311)
is 1'', the bus arbitration control circuit 36 adjusts the right to use the image bus and then sets the bus permission signal on the line 312 to 1. At this time, the buffers 37 to 40 become active. .At this time, IA lower (IA2Z ~ I
The signal of the lower SA (SA21 to SA5Ao) is output as is as A(11). On the other hand, IA top (1123, 1
122), the 2-bit data written in the control register 32 is output instead of the SA upper (sA23, 5A22). IRD on line 315, line 31
Signals propagating through lines 309 and 310, respectively, are output to the IWTs on IWT 6. In this way, addresses and commands are output from the image bus controller 1 to the image bus 1°, and the memory and the like on the image bus 10 are accessed.

By the way, 00000 in the address space of system bus 9
For 0H-BFFFFFH, the output of the decoder 31 (line 307) is @0''. Therefore, the access of the CPU 1 is not to the image bus 1o, but to the memory (M M ) on the system bus. be exposed.

Now, in the case of accessing the image bus l0tlC,
The image bus address output from the image bus controller differs depending on the data written in the control register 32. This relationship is shown in FIG. If the data written to the control register 32 is "00", the upper two bits of the image bus address will be "100", so
System bus address C00000H to FFFFFF
H is image bus address 000000n~3FF
Converted to FFFH. When the data written to the control register 32 is 01'', the upper two bits of the image bus address are 01=, so the system bus addresses 000000H to FF'FFFFH are transferred to the image bus addresses 400000H to 7FFFFFFH. Converted.The data written to the control register 32 is "10"
, the top two pits of the image bus address are '
Since it is "10", the system address C00000
H~FFFFFFH is the image bus address 800
Converted to 000H to BFFFFFH.

If the data written to the control register 32 is 111#, the upper two pits of the image bus address id @1
1”, so the system bus address C00000
H~FFFFFFH is the image bus address coo
Converted to ooo□~FFFFFFH.

In this way, coooooo□~F on the system bus
From F F F F FH, the entire image bus 0O
OOOOH to FFFFFFH can be accessed.

In the embodiments of the present invention, the explanation is given by exemplifying a high-performance work stage, but the invention is not limited to this, and as mentioned at the beginning, any system having two independently operating buses can be used. , is applicable to all. Further, while address conversion has been described only in a simple manner, complex address conversion including operations on address bits is also possible.

[Effects of the Invention] As explained above, the method of the present invention provides an image bus controller that connects a system bus and an image bus.
It performs address translation, and the effects listed below can be obtained.

(1) The entire address space of the image bus can be accessed.

(2) Does not require more system bus address space than necessary.

(3) The hardware configuration around the bus is simple.

(4) Prevent data transfer speed from decreasing.

Note that when viewed from the system bus, the image controller appears to be a memory equivalent to the main memory.

On the other hand, when viewed from the image bus side, the image bus controller appears to be a bus master equivalent to a graphics image processor. Therefore, the system structure is simple and a highly flexible system can be constructed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a system configuration of a high-performance work stage in which the present invention is implemented, and FIG. 2 is a diagram showing an example of an address space according to an embodiment of the present invention developed on a memory.
3 are block diagrams showing the internal configuration of the image bus controller shown in FIG. 1, FIG. 4 is a diagram showing the operation of the embodiment of the present invention developed on memory, and FIGS. 5 to 7. 1 is a diagram showing an example of an address space in a conventional example. l...Image lot controller, 3Z...Decoder, 32...Control register, 33-35...Gate, 36...Bus arbitration control circuit, 37-40...Background Figure 1, Figure 2 figure

Claims (1)

[Claims] In a data processing device consisting of two independently operating buses connected to each bus master module via a bus controller, the bus controller decodes an address arriving via one of the buses. , a decoder that detects that the other bus is being accessed, a control register in which address data is set that determines which part of the address space of the other bus is accessed, and the decoder output and READ/
A gate that generates a bus use request for the other bus based on the WRITE signal, a bus arbitration control circuit that performs bus arbitration by obtaining the output of this gate and generates a bus use permission signal, and a bus arbitration control circuit that generates a bus use permission signal based on the signal generated here. An address conversion method comprising a buffer for driving the control register output, address information, and commands.