JPS6383845A - Memory card - Google Patents

Abstract

PURPOSE:To ensure the application of a memory card to both memory bus and input/output bus systems by controlling the output of an address register and an address bus based on a connection interface and validating the direct or indirect addressing. CONSTITUTION:A bus switch signal MEM is set at '1' with the interface of a memory bus system together with the outputs of address registers 111 and 112 set under high impedance states. Then the address signal received from a data processor drives directly memory address bus MAD0-12 and a decoder 113 to give the direct addressing to a memory chip in a memory card through the data processor. While the signal MEM is set at '0' with the interface of an input/out bus system. Then the bus MAD0-12 and the decoder 113 are driven based on the registers 111 and 112.

Description

[Detailed Description of the Invention] [Object of the Invention (Field of Industrial Application)]
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(Prior Art) In recent years, memory cards with built-in memory chips have come to be used for document files for word processors and the like. A memory card generally has a business card size of 86 m in length and 54 m in width, and a thickness of 2 to 5 m. This memory card is connected to a data processing device through a multi-contact parallel interface. Memory cards are attracting attention as storage media with built-in semiconductor memory and excellent features such as small size, light weight, low power consumption, high speed, and high reliability. The built-in semiconductor memory can be used as RAM or mask, depending on the application.
ROM, 0TP (ONE TI PROM)%
EEPROM (ELECTRIC ERASABLE)
PROM) or a combination thereof.

A set of interfaces for connecting a conventional memory card and a data processing device are shown in FIGS. 3 and 4. FIG. 3 shows a memory card with a memory path interface suitable for connection to the memory path of a microprocessor. This interface includes an address bus (ADo 5 on one side) corresponding to the memory capacity, a bidirectional path (DTo 7),
It consists of a read control line (RD), a write control line (WR) and a card select signal (CS). The elements built into a memory card are generally one or more memory chips 3
There is only 1. The characteristics of the memory path method are listed below.

(1) Direct addressing allows high-speed access.

(2) No additional circuit is required for using all terminals of the memory chip as input/output terminals.

FIG. 4 shows a memory card with an input/output path suitable for connection to the input/output path of a microprocessor. This interface does not perform direct addressing using the memory address V22 address signal line, but accesses the memory after setting the address to be accessed in advance in the address register 42 in the memory card via the data bus (DT.-7). This is an indirect addressing method. The bidirectional data bus (DTo-7) is used as a data bus when reading/writing the memory and when setting an address in the address register 42. The address bus (AD(, -7) is used to select the input/output ports shown in Figure 5.R output control line (RD), write control @ (WR) and card select signal (CS)
is the same as the memory path method. Therefore, the memory card includes, in addition to one or more memory chips 41, an address register 42 for addressing an address space corresponding to the memory capacity. A read/write control circuit 43 for controlling the memory chip 41 and address register 42 is also required as a component.

FIG. 5 shows input/output ports and their functions.

(2) writes an address to address register 420 bit θ-7; (2) writes an address to bit 8 or 5 of address register 42;

■ reads/writes the memory address set in ■ and ■.

The characteristics of input/output path method 0 are listed below.

(1) The number of interface signal lines is small.

(2) Even if the memory capacity increases, it does not affect the interface signals. Therefore, it is highly expandable.

(Problems to be Solved by the Invention) Conventionally, there are many memory cards of the memory path type shown in FIG. 3. However, since the interface signal largely depends on the capacity of the memory chip, the signal terminal of the memory chip, and the capacity of the memory card, the interface lacks uniformity. Furthermore, in the future, the number of memory cards using the input/output path method shown in FIG. 4 is expected to increase for file applications such as document files for word processors, data files for personal computers, and RAM disks. As the needs for memory cards become more diversified, the types of interfaces are also increasing, and it becomes necessary to change the interface circuits, connectors, etc. for each memory card. As the scope of use of memory cards expands, it is desired to unify the interface.

The present invention has been made based on the above-mentioned circumstances, and an object of the present invention is to provide a memory card that can be used in an interface.

[Structure of the Invention] (Means for Solving the Problems) The present invention has a structure that allows the same memory card to support both connection interfaces of the memory path method and the input/output path method. In addition to the memory chip, a memory card has a mechanism for directly addressing the memory chip, a mechanism for indirect addressing via an address register, and a mechanism for direct addressing by controlling the address register output or address bus based on the memory card's connection interface. It has a built-in switching device WIlt that enables either indirect addressing.

(Function) In the above configuration, in the memory path type interface, the address register output is set to a high impedance state based on the path switching signal, and the address signal from the data processing device directly drives all address paths and decoders. In an input/output hash type interface, an address bus and a decoder are driven from a preset address register based on a path switching signal. In an input/output path type interface, the address bus is set to a high impedance state.

As a result, the same memory card can be used for either interface, allowing a highly flexible and expandable system to be constructed and greatly expanding the scope of use.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings. @1 Figure is a block diagram showing an embodiment of the present invention.1 The embodiment of the present invention is an example of a 64-byte memory card with eight built-in 64-pit (8K x 8 bits) memory chips, and a control circuit. This memory card consists of a memory chip 22 and an interface signal HEM.
The memory path type interface shown in FIG.

Alternatively, you can switch to the input/output path type interface shown in Figure @4. ■When the χ signal is 1'', it functions as a memory path type interface, and when it is '0'', it functions as an input/output path type interface. On the other hand, ADo 5 is an address bus, which directly addresses the memory in a memory path type interface. In the input/output, P4 interface, one of the ADo's is used to select an input/output port in a control circuit as shown in FIG. DTo-7 is a bidirectional data bus, which is used for reading/writing memory data in a memory path interface.

In the input/output path type interface, it is used as a data bus for reading/writing memory data (b) and writing an address register inside the control circuit 11. When accessing the memory card using the csh card select signal, “
1". RD Fi is a read control line and WR is a write control line. MADo and 2 are address buses for the memory chip.

MDT. -7 is a bidirectional data bus to the memory chip. MCEo-7 uses a memory chip enable signal to select which chip of the eight memory chips 7p12 is to be accessed. OE is an output enable signal for the memory chip and is used when reading memory data.

2 is a write signal to the memory chip.

FIG. 2 shows the internal structure of the control circuit 11 shown in FIG. 1, and is a diagram showing only the periphery of the address bus and data bus. In the figure, 111.112 are address registers, 1
13Ff: Decoder. address register≠0(
111) and S1 (112) are used in an input/output path type interface, and the memory address to be accessed is written via the data bus DTo-7. Address register ÷ 0 (111) n Memory address 0-7, Address register 1 (112) d Memory address 8 One side 5
Set f. The decoder 113 decodes the highest address (13 on the other hand 5) and decodes the memory chip enable signal M (
Generate J-7.

The mechanism for switching the interface between the memory path method and the input/output path method will be described below.

J Engineering 11) When the two beaks are inserted, the pass cut signal port is set to @l'', and the outputs of address registers 0 (III) and 1 (112) are in a high impedance state. The address signal from the processing device directly drives the memory address bus MADo 2 and the decoder 113, so that the memory chip 12 in the memory card can be directly addressed from the data processing device.In an input/output path type interface, path switching is required. The signal port is set to 10'', and the memory address bus MADo 2 and decoder 113 are driven based on address registers 0 (111) and 11 (112) to which data has been set in advance. In the input/output path type interface, one address bus ADo 5 from the data processing device is set to a high impedance state or is not connected. However, address ADo-J is used to control the input/output ports.

[Effects of the Invention] As explained above, according to the present invention, a memory path type interface and an input/output path type interface or M-system can be realized.
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(1) The range of use is greatly expanded because the same memory card can be used as an interface for both a memory path that can be accessed at high speed by direct addressing and an input/output path method that is simple and has excellent expandability.

(2) Since the path method is switched inside the memory card, the data processing device does not require any special circuit.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is @
Figure 1 shows only the internal configuration of the ratio control circuit that is relevant to the present invention, and Figures 3 and 4 show the memory card in the memory path interface and the input/output path interface, respectively. FIG. 5 is a diagram showing an example of a configuration, and is a diagram showing an example of assignment of input/output ports in an input/output path type interface in a table format. 11... Control circuit, 12... Memory chip, 111
゜112...Address register, 113...Decoder. Figure 3 Figure 4

Claims (1)

[Claims] A memory card that is removable from a data processing device, with means for directly addressing the memory built in the memory card from the data processing device, and indirect addressing of the memory via an address register to which an arbitrary value is set by the data processing device. and switching means for controlling the output of the address register or the address bus to enable either direct addressing or indirect addressing based on the connection interface of the memory card.