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JPS638146Y2 - - Google Patents

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Publication number
JPS638146Y2
JPS638146Y2 JP1980029096U JP2909680U JPS638146Y2 JP S638146 Y2 JPS638146 Y2 JP S638146Y2 JP 1980029096 U JP1980029096 U JP 1980029096U JP 2909680 U JP2909680 U JP 2909680U JP S638146 Y2 JPS638146 Y2 JP S638146Y2
Authority
JP
Japan
Prior art keywords
switch
contact
lead frame
semiconductor device
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1980029096U
Other languages
Japanese (ja)
Other versions
JPS56132757U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1980029096U priority Critical patent/JPS638146Y2/ja
Publication of JPS56132757U publication Critical patent/JPS56132757U/ja
Application granted granted Critical
Publication of JPS638146Y2 publication Critical patent/JPS638146Y2/ja
Expired legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Description

【考案の詳細な説明】 本考案はスイツチを組込んだ半導体集積回路に
関し、リードフレームにスイツチの接点を形成し
てスイツチ機構と半導体集積回路を一体に形成し
た半導体装置を提供することを目的とする。
[Detailed description of the invention] The present invention relates to a semiconductor integrated circuit incorporating a switch, and an object of the present invention is to provide a semiconductor device in which a switch mechanism and a semiconductor integrated circuit are integrally formed by forming a switch contact on a lead frame. do.

本発明のスイツチを具えた半導体装置につい
て、第1図乃至第5図に基づき説明する。
A semiconductor device equipped with a switch of the present invention will be explained based on FIGS. 1 to 5.

第1図は本考案に係るスイツチを具えた半導体
装置の一実施例である。1は半導体装置、2はス
イツチのキー、3は端子ピンである。
FIG. 1 shows an embodiment of a semiconductor device equipped with a switch according to the present invention. 1 is a semiconductor device, 2 is a switch key, and 3 is a terminal pin.

第2図は本考案に係るスイツチの接点を具えた
リードフレーム4であり、外枠5に端子ピン3を
具えている。6はガイド孔であり、7は支持枠で
ある。端子ピン3の先端部である点線で囲まれた
部分8がスイツチの接点3a,3bを形成してい
る。接点3a,3bの他端3eはセラミツク基板
15に被着された半導体素子10と配線11によ
つて接続されている。尚、セラミツク基板15は
半導体素子10、或いは、チツプコンデンサ等の
回路素子が被着され集積回路を形成しており、端
子ピン3とその先端部のスイツチの固定接点部が
熱融着等の手段によつて、セラミツク基板15に
固着されている。
FIG. 2 shows a lead frame 4 equipped with contacts of a switch according to the present invention, and an outer frame 5 is provided with terminal pins 3. 6 is a guide hole, and 7 is a support frame. A portion 8, which is the tip of the terminal pin 3 and is surrounded by a dotted line, forms the contacts 3a and 3b of the switch. The other ends 3e of the contacts 3a, 3b are connected to a semiconductor element 10 attached to a ceramic substrate 15 by a wiring 11. The ceramic substrate 15 has a semiconductor element 10 or a circuit element such as a chip capacitor attached thereto to form an integrated circuit, and the terminal pin 3 and the fixed contact portion of the switch at the tip thereof are bonded by means such as thermal fusion. It is fixed to the ceramic substrate 15 by.

第3図はスイツチの接点部8を具えたリードフ
レームの他の実施例である。端子ピン3の先端部
3c,3dが接点であり、3gは端子ピン3の先
端部に半導体集積回路素子10等の回路素子を被
着する部分であり、端子ピン3の先端部3fと半
導体素子が配線11によつて接続されている。リ
ードフレームの形状は第2図及び第3図に限るこ
となく種々のものとなし得る。
FIG. 3 shows another embodiment of the lead frame with the contact portion 8 of the switch. The tip portions 3c and 3d of the terminal pin 3 are contacts, and 3g is a portion to which a circuit element such as the semiconductor integrated circuit device 10 is attached to the tip portion of the terminal pin 3, and the tip portion 3f of the terminal pin 3 and the semiconductor element are connected by wiring 11. The shape of the lead frame is not limited to those shown in FIGS. 2 and 3, and can be made into various shapes.

次に、スイツチ機構について第4図と第5図に
基づき説明する。
Next, the switch mechanism will be explained based on FIGS. 4 and 5.

第4図は、第2図の接点部8のスイツチ機構を
示す側面断面図である。9は外観形状が円筒形の
導電性ゴムで形成された弾性のある接点である。
端子ピン先端部の接点3bがスイツチの可動接点
9の中央に設けた突出部と接触しており、矢印方
向からの圧力によつて、導電性ゴムが歪み接点3
aと接触して可動接点9を介して接点3aと3b
が導通状態になる。
FIG. 4 is a side sectional view showing the switch mechanism of the contact portion 8 of FIG. 2. FIG. Reference numeral 9 denotes an elastic contact made of conductive rubber and having a cylindrical appearance.
The contact 3b at the tip of the terminal pin is in contact with the protrusion provided at the center of the movable contact 9 of the switch, and the conductive rubber is distorted by the pressure from the direction of the arrow.
contacts 3a and 3b through the movable contact 9 in contact with
becomes conductive.

第5図は、樹脂モルードされたスイツチ機構の
一実施例を示す側面断面図であり、第3図のリー
ドフレームを用いた場合の実施例である。導電性
ゴムからなる接点9の突出部がセラミツク基板1
5に接触しており、接点9は係合体13に嵌合し
ており、係合体13はキー2を装着している。矢
印方向にキー2を押すことにより、接点9が歪ん
で接点3cと3dが接点9の介在によつて導通状
態となる。12はハウジングである。
FIG. 5 is a side sectional view showing an embodiment of a resin-molded switch mechanism, and is an embodiment in which the lead frame of FIG. 3 is used. The protruding part of the contact 9 made of conductive rubber is connected to the ceramic substrate 1.
5, the contact 9 is fitted into the engagement body 13, and the engagement body 13 is equipped with the key 2. By pressing the key 2 in the direction of the arrow, the contact 9 is distorted and the contacts 3c and 3d become electrically connected through the interposition of the contact 9. 12 is a housing.

本考案に係るスイツチを具えた半導体装置は、
セラミツク基板15に半導体装置10等の配線が
なされたリードフレーム4が接着され、リードフ
レーム4に形成されているスイツチの固定接点を
被う如く、可動接点が収納されているハウジング
12が接着された後、これらの部品を樹脂モール
ドしてスイツチ機構部品と半導体装置等の部品を
一体に樹脂成形したものである。
A semiconductor device equipped with a switch according to the present invention is
A lead frame 4 on which wiring such as the semiconductor device 10 was formed was adhered to a ceramic substrate 15, and a housing 12 containing a movable contact was adhered so as to cover the fixed contact of the switch formed on the lead frame 4. These parts are then resin molded, and the switch mechanism parts and parts such as the semiconductor device are integrally resin molded.

第6図は本考案に係る半導体装置1をプリント
基板14に取付けた使用状態を示す図である。1
6はパネルであつて開口部17がある。パネル1
6に固定された取付軸18に、半導体装置1が取
り付けられたプリント基板14が固定されて開口
部17にキー2が装着される。
FIG. 6 is a diagram showing a usage state in which the semiconductor device 1 according to the present invention is attached to a printed circuit board 14. 1
6 is a panel having an opening 17. Panel 1
The printed circuit board 14 to which the semiconductor device 1 is attached is fixed to a mounting shaft 18 fixed to the mounting shaft 6 , and the key 2 is mounted in the opening 17 .

本考案に係るリードフレームは、通常のコパー
ル板でよく、半導体装置1の形状はトランスフ
ア・モールドや種々のパツケージが可能である。
第5図に示したようにキー2を装着した係合体1
3に嵌合した接点9を収納しているハウジング1
2を予めセラミツク基板15に固定して樹脂モー
ルドする方法や、また、半導体集積回路が形成さ
れた基板を第5図のようなハウジング12内にキ
ーボードスイツチを形成して収納容器に装着し、
この収納容器と基板に固着された半導体集積回路
とを樹脂モールドしてスイツチを具えた半導体集
積回路を形成する。ハウジング12の底部が突起
部が形成され、固化した樹脂によつて半導体集積
回路10と共に固定される。
The lead frame according to the present invention may be an ordinary copper plate, and the shape of the semiconductor device 1 can be transfer molded or various packages.
Engagement body 1 with key 2 attached as shown in FIG.
A housing 1 housing a contact 9 fitted into a housing 3
2 to a ceramic substrate 15 in advance and resin molding, or a method in which a substrate on which a semiconductor integrated circuit is formed is formed with a keyboard switch inside the housing 12 as shown in FIG. 5 and mounted in a storage container.
This storage container and the semiconductor integrated circuit fixed to the substrate are resin molded to form a semiconductor integrated circuit equipped with a switch. A protrusion is formed on the bottom of the housing 12, and is fixed together with the semiconductor integrated circuit 10 by solidified resin.

また、第4図及び第5図は導電性ゴムを接点9
に用いているが、これに限るものでなく、接点3
aと3b間、或いは、接点3cと3d間を短絡す
ることができるような例えば、板状の金属の接触
子を用いても良いことは明らかである。(図示せ
ず) 更に加えるに、第3図のリードフレームに示し
たように、端子ピン3の先端部3gに半導体素子
10を被着した場合、セラミツク基板15は接点
部8を除きかならずしも必要としない。勿論、半
導体集積回路等の回路素子が被着される基板はセ
ラミツク基板に限ることはないことは言うまでも
ない。
In addition, in Figures 4 and 5, conductive rubber is connected to the contact point 9.
Contact point 3 is used, but is not limited to this.
It is obvious that, for example, a plate-shaped metal contact that can short-circuit between a and 3b or between contacts 3c and 3d may be used. (Not shown) Additionally, when the semiconductor element 10 is attached to the tip 3g of the terminal pin 3 as shown in the lead frame of FIG. do not. Needless to say, the substrate on which circuit elements such as semiconductor integrated circuits are attached is not limited to ceramic substrates.

上述のように、本考案はスイツチを具えた半導
体装置であつて、リードフレームに接点部を設け
て集積回路に組み込んだことを特徴とするもので
ある。本考案に係る半導体装置は、電子ボリウム
のようにスイツチを押すことによつて電圧を可変
したり、AM受信からFM受信へと切換える等
種々の用途に適用することができる。このよう
に、スイツチと半導体集積回路とを一体に組込む
ことにより部品数を低減できるので小型に形成で
きると共に、実装時の組立作業工数を低減するこ
とができる。無論、リードフレームを用いている
ので量産化に優れた効果を奏することは明らかで
ある。
As described above, the present invention is a semiconductor device equipped with a switch, and is characterized in that a contact portion is provided on a lead frame and incorporated into an integrated circuit. The semiconductor device according to the present invention can be applied to various uses such as changing the voltage by pressing a switch like an electronic volume control or switching from AM reception to FM reception. In this way, by integrating the switch and the semiconductor integrated circuit, the number of parts can be reduced, making it possible to form a compact device and reducing the number of assembly steps during mounting. Of course, since a lead frame is used, it is clear that it has an excellent effect on mass production.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係るスイツチを具えた半導体
装置の斜視図、第2図及び第3図はスイツチの接
点を具えたリードフレームの平面図、第4図及び
第5図はスイツチの接点機構を示す側面断面図、
第6図は本考案に係る半導体装置の使用状態を示
す一実施例の側面図である。 1:半導体装置、2:キー、3:端子ピン、
4:リードフレーム、5:外枠、6:ガイド孔、
7:支持枠、8:接点部、9:接点、10:半導
体素子、11:配線、12:ハウジング、13:
係合体、14:プリント基板、15:セラミツク
基板、16:パネル、17:開口部、3a,3
b,3c,3d:接点。
Figure 1 is a perspective view of a semiconductor device equipped with a switch according to the present invention, Figures 2 and 3 are plan views of a lead frame equipped with switch contacts, and Figures 4 and 5 are switch contact mechanisms. A side sectional view showing
FIG. 6 is a side view of one embodiment of the semiconductor device according to the present invention, showing how it is used. 1: Semiconductor device, 2: Key, 3: Terminal pin,
4: Lead frame, 5: Outer frame, 6: Guide hole,
7: Support frame, 8: Contact portion, 9: Contact, 10: Semiconductor element, 11: Wiring, 12: Housing, 13:
Engagement body, 14: Printed circuit board, 15: Ceramic substrate, 16: Panel, 17: Opening, 3a, 3
b, 3c, 3d: Contact points.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体集積回路素子と、基板と、該基板に接着
され該半導体集積回路素子と配線がなされたリー
ドフレームの内部端子と、該リードフレームの内
部端子の少なくとも二つをスイツチの固定接点と
しキーの押圧により該固定接点を短絡する可動接
点が収納されたハウジングを該固定接点上に載置
されて該基板と固定してなるスイツチとを樹脂モ
ールドによつて同一パツケージに形成したことを
特徴とするスイツチを具えた半導体装置。
A semiconductor integrated circuit element, a substrate, an internal terminal of a lead frame bonded to the substrate and wired to the semiconductor integrated circuit element, and at least two of the internal terminals of the lead frame are used as fixed contacts of the switch to press the key. A switch characterized in that a housing housing a movable contact for short-circuiting the fixed contact is placed on the fixed contact and fixed to the substrate, and a switch is formed in the same package by resin molding. A semiconductor device equipped with
JP1980029096U 1980-03-05 1980-03-05 Expired JPS638146Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1980029096U JPS638146Y2 (en) 1980-03-05 1980-03-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1980029096U JPS638146Y2 (en) 1980-03-05 1980-03-05

Publications (2)

Publication Number Publication Date
JPS56132757U JPS56132757U (en) 1981-10-08
JPS638146Y2 true JPS638146Y2 (en) 1988-03-10

Family

ID=29625004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1980029096U Expired JPS638146Y2 (en) 1980-03-05 1980-03-05

Country Status (1)

Country Link
JP (1) JPS638146Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50108559A (en) * 1974-01-28 1975-08-27

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5174758U (en) * 1974-12-06 1976-06-11

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50108559A (en) * 1974-01-28 1975-08-27

Also Published As

Publication number Publication date
JPS56132757U (en) 1981-10-08

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