JPS6379386A - Hall element array - Google Patents

Abstract

PURPOSE:To obtain an element, by forming a plurality of Hall element parts on a semiconductor single crystal substrate as a unitary body, providing a Hall element array, thereby improving the resolution of a detector for rotation, positions and the like. CONSTITUTION:The dimensions of a semi-insulating GaAs substrate 10 are as follows: width (W) is 5 mm; length (L) is 10 mm; and thickness (D) is 0.3 mm. On the substrate 10, an active layer comprising N-type GaAs having a carrier concentration of 10<l7>cm<-3> is formed by a vapor growth method to a thickness of 2 mum. Thereafter an active layer 20a comprising Hall element part 20 is formed in a comb shape by photolithgraphy and etching steps. The dimensions of the layer 20a are as follows: width (H) is 0.1 mm; length (l) is 2 mm; and element interval (P) is O.2 mm. Thereafter Au-Sn is evaporated by mask evaporation. Then thermal diffusion is performed, and output electrodes 63a and 64a and current electrodes 61a and 62a are formed.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a Hall element array in which a plurality of Hall element parts are arranged on the same substrate.

[Prior art]

Conventionally, Hall elements have been used for detecting the rotational speed of encoders, position detection, proximity switches, and the like. However, such hole strings were composed of individual strings.

[Problems to be solved by the invention]

Since it is an individual element, there is only one magnetically sensitive surface, and its output is the average value of the entire magnetically sensitive surface. Therefore, there was a problem in that the resolution of the encoder etc. could not be increased. Furthermore, the magnetization pattern of the encoder is made finer in order to increase the resolution, but this also has its limitations, which is the reason why it is not possible to increase the resolution. The present invention has been made in order to solve such problems, and its purpose is to provide a detection element for improving the resolution of a rotation, position, etc. detector. .

[Means for Solving the Problems] In order to solve the above problems, the structure of the invention is a Hall element array in which a plurality of Hall element parts are integrally formed on a semiconductor single crystal substrate. This array can be formed by using semi-insulating gallium arsenide for the semiconductor substrate and epitaxially growing gallium arsenide for the Hall element portion. In addition, single crystal silicon is used as the semiconductor single crystal substrate, on which an intermediate layer is epitaxially grown between the substrate and the Hall element portion to alleviate the lattice mismatch between the two, and on top of that, gallium arsenide is grown. A Hall element portion may be formed using an epitaxially grown layer as an active layer. In this case, the intermediate layer is preferably gallium phosphide (G
aP), and more preferably has a superlattice layer. In the case of a superlattice, the intermediate layer is formed from the main surface side of the silicon single crystal substrate: a superlattice layer of gallium phosphide (G a P ) and gallium arsenide phosphide (GaAsP), and a gallium arsenide phosphide (GaAsP) layer. GaAsh) and gallium arsenide (GaA
It is preferable to form a bond layer with the superlattice layer of s). Further, between the superlattice layer and the silicon single-crystal substrate, a multilayer of a layer consisting of aluminum phosphide (AIP>) and a layer consisting of gallium aluminum phosphide (AIGaP), or a layer consisting of gallium aluminum phosphide (AIGaP) is formed from the silicon single-crystal substrate side. When a single layer of (GaP) was interposed, the crystallinity of the active layer made of gallium arsenide was further improved.

【Effect of the invention】

Since the plurality of Hall element parts are integrally formed on the same substrate, each element part can be configured finely and uniformly. This made it possible to improve resolution and measurement accuracy. For example, one of the fine magnetized patterns is detected by a plurality of Hall element sections, and the center position of that one magnetized pattern can be detected with a resolution equal to the arrangement pitch of the Hall elements. Further, from the phase relationship of the detection signals of the plurality of Hall element sections, position detection can be similarly performed with the resolution of the array pitch. In addition, when silicon is used for the semiconductor single crystal substrate,
Since a large wafer can be used, the mechanical strength is increased and the Hall element array can be mass-produced at low cost. Furthermore, by setting the intermediate layer to a predetermined configuration, the crystallinity of the Hall element portion was improved, and the detection sensitivity was improved.

【Example】

Example 1 FIG. 1 is a perspective view of a Hall element array showing how the Hall element sections are arranged, and FIG. 2 is a plan view thereof. In the figure, 10 is a semi-insulating GaAS substrate, with dimensions of width (W) 5 mm, length L>10 m+, and thickness D.
) 0.3 mm. On the substrate 10, an active layer made of n-type GaAs with a carrier concentration of 10110l7'' is formed to a thickness of 2 layers by a vapor phase epitaxy method.After that, a photolithography and etching process is performed to form an active layer of n-type GaAs as shown in Fig. 'fS1. , width (14)Q, 1mm, length j2)2++t+n
, each Hall element part 2 is arranged in a node shape with an element spacing (P) of 0°2 mm.
0 active layer 20a is formed. Thereafter, ΔU-3n was vapor-deposited by mask vapor deposition, and then thermal diffusion treatment was performed to form output electrodes 63a, 64a and current electrodes 61a, 62a as shown in FIG. Embodiment 2 FIG. 4 is a plan view showing the arrangement of the element portions of the Hall element array according to this embodiment, and FIG. 3 is a sectional view thereof in the direction of arrows. In the figure, 1o is n whose main surface is inclined in the [110] direction at an off angle of 2 degrees with respect to the [:100] direction.
It is a type of silicon single crystal substrate. 30 is an intermediate layer, 50 is an active layer consisting of an n-type gallium arsenide epitaxial layer,
61.62 is a current electrode made of Au-3n, 63.64
Is the output composed of Au-3n? ! ! It is extreme. The thickness of the layers is 300 μm for the silicon single crystal substrate 10, 0.25 μm for the intermediate layer 30, and 1 μm for the active layer 50. The intermediate layer 30 includes a first intermediate layer 31 made of a single layer of gallium phosphide (GaP), and a gallium arsenide phosphide (GaAso,
The second intermediate layer 32 consists of a superlattice of s P o, s ) and gallium arsenide phosphide (Ga A S
o, s P o, s ) and a third intermediate layer 33 made of a superlattice of gallium arsenide. First intermediate layer 3
1 is a single layer with a thickness of 500 mm, and the second intermediate layer 32 and the third intermediate layer 33 are each composed of a superlattice consisting of 5 layers of 200 mm thick. . This Hall element array is manufactured using metal-organic pyrolysis vapor phase epitaxy (
They were successively epitaxially grown on a silicon single crystal substrate 10 by MOCVD). A horizontal induction heating atmospheric pressure furnace was used as the reactor. The raw material gas includes trimethyl gallium (TM Ga, Ga(Cl13)3
), trimethylaluminum (TMΔI, AI(C1
1,),), arsine diluted with hydrogen (A s Hs),
Bosfin (P i-+ , ) is used. Furthermore, diethyl zinc (DEZn) and 1I2se diluted with hydrogen were used as n-type and n-type dopants, respectively. The flow rate of these gases is precisely controlled by a flow rate controller so as to obtain a constant crystal growth rate. Also, pre-crackin of group III elements.
g) has not been done. First, the silicon substrate 10 was annealed by heating at 1000° C. for 10 minutes in a hydrogen cloud to remove the oxide film. Then, increase the growth temperature to 900
The first intermediate layer 31 was formed by epitaxially growing GaP while the temperature was maintained at 700°C, and then the second intermediate layer 32 and the third intermediate decoy 33 of a superlattice were epitaxially grown while the growth temperature was maintained at 700°C. In order to make the intermediate layer 33 semi-insulating, V group raw materials (AsHa or Δ5l(3+PH3) and
The molar ratio of the group raw material (trimethyl gallium) to be supplied was set to 30. At this time, the specific resistance was 1×10 5 Ωcm. Next, the growth temperature was maintained at 750°C, and Se-doped n-type GaAs (carrier concentration 5X101?cm) was grown.
3) The active layer 50 of the epitaxial layer was continuously grown. Next, by photolithographic and etching processes, only the n-type GaAs epitaxial layer in other parts was removed so that the active layer 50 of each Hall element part was separated into the shape shown in FIG. Thereafter, as shown in FIG. 4, Au-
After depositing 3n, annealing is performed to form electrodes 61.62.6.
3.64 was formed. The pitch of the Hall element portions formed in this manner is 0.5 mm. If we detect the rotation speed of the encoder using such a Hall element array, the output/power characteristics will be as shown in Figure 6, and 1
In addition to counting the rise and fall of the signal output from one Hall element section, the rotation angle of the encoder can be determined with the resolution of the Hall element array pitch based on the phase of the signal from the other element section. Embodiment 3 FIG. 6 is a sectional view showing the configuration of a Hall element according to another embodiment. In the figure, 10 is an n-type silicon single crystal substrate whose main surface is inclined in the (110) direction at an off angle of 2 degrees with respect to C100), 30 is an intermediate layer for mitigating lattice mismatch, and 50 is an active layer made of an epitaxial layer of GaAs.The configuration of the intermediate layer 30 differs from that of the first embodiment. That is, the intermediate layer 30 is strongly bonded to silicon and is bonded to the substrate 10.
A first intermediate layer 31 made of aluminum phosphide (AlP), which can be easily grown on the top, and gallium aluminum phosphide (A1o,s Gao,
a second intermediate layer 32 consisting of gallium phosphide (sP);
GaP) and gallium arsenide phosphide (GaP) with a mixed crystal ratio of 0.5.
A third intermediate layer 33 consisting of a superlattice of A S a,s-P Q,5 ) and gallium arsenide phosphide (
G a A S Q, S PG, S ) and a fourth intermediate layer 34 made of a superlattice of gallium arsenide. The thickness of the eyebrows is 300 μm for the substrate 10 and 0.0 μm for the intermediate layer 30.
The active layer 50 of the 42μm 5GaΔs pitaxial layer is 1
It is μm. To be more specific about the intermediate layer, the first intermediate layer 31 and the second intermediate layer 32 are each a single layer of 100,
The third intermediate layer 33 and the fourth intermediate layer 34 each consist of a superlattice in which 10 layers of 200 people are laminated. These layers were formed by MOCVD as in the first embodiment. The growth temperature is set at the first to fourth intermediate layers 31 to 3.
4 is 830°C, and the magnetic detection layer 50 of GaAs-+-bitaxial layer is 730°C. As a result of measuring the output characteristics of the Hall element array formed in this manner, good characteristics were obtained.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing an element arrangement of a Hall element array according to a specific embodiment of the present invention, FIG. 2 is a plan view thereof, and FIG. 3 is a Hall element array according to another embodiment. 4 is a plan view thereof, FIG. 5 is a plan view showing the shape of the active layer of the Hall element section, and FIG. 6 is a timing chart of output signals of the Hall element array of the embodiment. , FIG. 7 is a sectional view showing the configuration of a Hall element array according to another embodiment. 10 - Silicon fJ' crystal substrate 30 Intermediate layer 50 - Active layer consisting of GaΔS epitaxial layer 61.62 - Current electrode 63.64 - Output electrode 8
¥Applicant Daido Steel Co., Ltd. Agent Patent Attorney Osamu Fujitani Figure 1 Figure 2 Figure 3 Figure 6-4 Figure 5 Figure 6 Figure 7 - 1111

Claims (5)

[Claims] (1) A Hall element array formed by integrally forming a plurality of Hall element parts on a semiconductor single crystal substrate. (2) The semiconductor single crystal substrate is made of semi-insulating gallium arsenide, and the active layer that converts a magnetic physical quantity into an electrical physical quantity in the Hall element portion is made of an epitaxial layer of gallium arsenide. The Hall element array according to claim 1, characterized in that: (3) the semiconductor single crystal substrate is made of silicon;
The active layer that converts a magnetic physical quantity into an electrical physical quantity in the Hall element portion is composed of an epitaxial layer of gallium arsenide, and reduces lattice mismatch between the semiconductor single crystal substrate and the active layer. The Hall element array according to claim 1, further comprising an intermediate layer. (4) The intermediate layer includes gallium phosphide (GaP) and gallium arsenide phosphide (GaP) from the main surface side of the semiconductor single crystal substrate.
GaAsP) superlattice layer and gallium arsenide phosphide (GaAsP) superlattice layer and gallium arsenide phosphide (Ga
4. The Hall element array according to claim 3, comprising a superlattice layer of gallium arsenide (GaAs) and gallium arsenide (GaAs). (5) The intermediate layer includes, from the main surface side of the semiconductor single crystal substrate, a layer made of aluminum phosphide (AlP), a layer made of gallium aluminum phosphide (AlGaP), and a layer made of gallium phosphide (GaP) and phosphorus arsenide. Gallium oxide (GaAs
P) superlattice layer and gallium arsenide phosphide (GaAsP
) and a superlattice layer of gallium arsenide (GaAs).