JPS6377156A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To suppress an overetching of a silicon oxide film thereby to improve the dielectric breakdown strength of a gate electrode and wirings and to improve the quality of an MOSIC by interposing a silicon nitride film on the gate electrode. CONSTITUTION:A field insulating film 4 is formed on a P-type silicon substrate 1, a gate insulating film 2 is thermally oxidized to be formed, covered with a polycrystalline silicon film 3 for a gate electrode, and further covered thereon with an SiO2 film 6 and an Si3N4 film 10. Then, a resist film 8 is formed, films 10, 6, 3, 2 are simultaneously patterned in the shape of the gate electrode by anisotropically etching. The whole surface is covered with an SiO2 film 9, anisotropically etched perpendicularly from the upper surface to form a sidewall made of the film 9. Then, the exposed substrate 1 is ion implanted, heat treated to form an N-type source, drain regions 5.

Description

[Detailed Description of the Invention] [Summary] A gate insulating film, a gate electrode film, a silicon oxide film, and a silicon nitride film are laminated and patterned in the shape of a gate electrode, and then a second silicon oxide film is covered over the entire surface. Then, vertical anisotropic etching is performed to form a sidewall around the gate electrode and expose the source and drain forming regions. By interposing the silicon nitride film in this way, overetching of the silicon oxide film on the gate electrode is suppressed.

[Industrial Field of Application] The present invention relates to a method of manufacturing a field effect semiconductor device (MrSFET) among methods of manufacturing a semiconductor device.

A typical example of MISFETs is the MOS l-transistor, and semiconductor integrated circuits (MOS IC) made of such MOS transistors are easier to integrate than transistors of other structures, so they have become a popular choice in semiconductor technology. As technology advances, the self-alignment (self-alignment) method has been adopted, becoming highly integrated and widely used in memory circuits such as RAM and ROM, and other electronic circuits.

However, now that ICs have become more highly integrated and miniaturized, a manufacturing method that can be controlled with high precision is desired.

[Prior art] Figure 2 shows a MOS semiconductor element (MOS l-transistor)
1 is a p-type silicon substrate, 2 is a cross-sectional schematic diagram of
3 is a gate insulating film, 3 is a gate electrode, 4 is a field insulating film, 5 is an n+ type source or drain region, 6 is an insulating film, and 7 is an electrode.

An outline of the conventional manufacturing method of this MOS semiconductor device will be explained with reference to FIGS.

FIG. 3(a): A field insulating film 4 made of a thick silicon oxide (Si02) film is formed on a p-type silicon substrate 1 by applying the LOCO5 method, leaving the region where the MOS semiconductor element will be formed exposed. .

FIG. 3(b): Next, a gate insulating film 2 is formed on the exposed surface by thermal oxidation, and a gate electrode film 3 made of a conductive polycrystalline silicon film is coated thereon by chemical vapor deposition (CVD). 5i02 film 6 is deposited on top of it using the same CVD method.
(insulating film) is applied.

FIG. 3(C): Next, a resist film mask 8 is formed using a photo process, and vertically anisotropically etched.
i02 membrane6. Gate electrode film 3 and gate insulating film 2 are patterned into the shape of a gate electrode.

Figure 3(d) Next, the entire surface is coated with a film with a thickness of 40 mm.
A 5i02 film 9 (second silicon oxide film) of 0.00 is deposited. At this time, the film deposited by the CVD method has good coverage (coverage) and is deposited even on the peripheral side surfaces of the gate electric machine.

FIG. 3(e): Next, when the entire surface is anisotropically etched (RI E ; reactive ion etching) perpendicularly from the upper surface, most of the 5i02 film 9 is removed, and the source and drain forming regions are exposed. , the 5i02 film 9 remains only on the peripheral side surfaces of the gate electrode. This 5i02 film 9 is called a sidewall.

FIG. 3(f): Next, phosphorus or arsenic is ion-implanted into the exposed surface and heat treated to define n+ type source and drain regions 5. FIG. Thereafter, electrodes 7 are formed, and a MOS semiconductor device as shown in FIG. 2 is completed.

[Problems to be solved by the invention] According to such a forming method, a photo process is rarely used (the above process is performed only once).
, since it can be formed with self-alignment, element miniaturization and I
This is an extremely effective manufacturing method for highly integrated C, and has recently been widely used.

The reason why the sidewall is formed here is to prevent these regions from penetrating deeply (underneath the gate electrode) when the source and drain regions 5 are defined by ion implantation and heat treatment, and to form the electrode 7. In this case, there is no need to open the electrical window and insulation from the gate electrode can be maintained with the self-alignment line.

In addition, the sidewall is equipped with LDD (Lightly Doped), which is known as a short channel countermeasure.
In a MOS semiconductor device with a drain) structure, low and high concentration ions are implanted to form the source and drain regions before and after sidewall formation. There is.

By the way, among the steps for forming such a sidewall, that is, the manufacturing method explained in FIG.
In the step of anisotropically etching the entire Si○2 film 9 (second 5i02 film) shown in e), the 5i02 film 6 patterned at the same time as the gate electrode 3 becomes the 5i02 film 9.
There is a problem in that the 5i02 film 6 is etched at the same time and becomes thinner to about 1,000 to 2,000 layers. This is also due to the fact that the 5i02 film 9 does not remain on the surface of the source and drain forming regions and the silicon substrate 1 is completely exposed by over-etching.

However, when the 5iOz film 6 is etched and becomes thinner, for example, the wiring (not shown) formed on the upper part
It becomes impossible to maintain sufficient dielectric strength between the electrode and the gate electrode.

The present invention proposes a manufacturing method that solves these problems.

[Means for Solving the Problems] The purpose is to stack a gate insulating film, a gate electrode film, a 5i02 film, and a silicon nitride film on a semiconductor substrate, pattern it in the shape of a gate electrode, and then pattern it on the entire surface. depositing a 5i02 film of No. 2, and further anisotropically etching the second 5i02 film vertically over the entire surface to form a sidewall made of the second 5i02 film around the gate electrode;
Further, the present invention is achieved by a method of manufacturing a semiconductor device in which the source and drain forming regions of the semiconductor substrate are exposed.

[In other words, in the present invention, a 5io2 film and a silicon nitride film are stacked on the gate electrode film, and when the second 5i02 film is anisotropically etched over the entire surface, the 5t02 film in contact with the gate electrode is over-etched. Avoid being etched.

[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

FIGS. 1(a) to 1(f) are cross-sectional views showing the steps of the manufacturing method according to the present invention, and will be explained sequentially with reference to the drawings.

Figure 1(a): First, p
A field insulating film 4 (0,5~
(approximately 1 μm).

FIG. 1(b) Second, gate insulating film 2 (thickness number 100
A gate electrode film 3 made of a conductive polycrystalline silicon film is formed by thermally oxidizing a conductive polycrystalline silicon film (film thickness of about 4000).
was applied using the CVD method, and then 5i02 was applied on the top surface using the CVD method.
Film 6 (thickness 3000-4000) and silicon nitride (
A Si3N4) film 10 (thickness of several hundred layers) is deposited.

FIG. 1(C): Next, a resist film mask 8 is formed using a photo process, and anisotropic etching/notching (R
IE) Si3 N4 film 10. SiO2 film 6° Gate electrode film 3 and gate insulating film 2 are shaped like gate electrode (
Patterning is performed at once to a width of about 1.5 μm). Fluorine gas is used as the etching agent.

Figure 1(d): Next, the entire surface is coated with a film with a thickness of 40 mm.
00 St○2 film 9 (second 5i02 film) is deposited. At that time, the film deposited by the CVD method has good coverage and is also formed around the gate electrode.

FIG. 1(e): Next, the entire surface is anisotropically etched (RIE) vertically from the top surface. Then, 5i02
The film 9 remains only on the peripheral side walls of the gate electrode, and the SiO2 film 9 on the other planar portions is completely removed. Furthermore, the 5t02 film 6 is protected by the Si3 N4 film 10, and over-etching does not occur. As the reaction gas, a fluorine-based gas such as carbon tetrafluoride (CF4) is used.

FIG. 1(f) Second, phosphorus or arsenic is ion-implanted into the exposed surface of the silicon substrate, and ann+ type source and drain regions 5 are defined by heat treatment.

According to the above-described formation method, the problem of lowering the dielectric strength between the gate electrode and the wiring is solved, and the MOS IC
is improved in quality.

Further, although the above description has been made using a MOS semiconductor element having a normal structure, it goes without saying that the present invention can also be applied to a MOS semiconductor element having an LDD structure.

[Effects of the Invention] As is clear from the above description, the present invention has a remarkable effect of improving the quality of MOSIC, such as improving the dielectric strength between the gate electrode and the wiring.

[Brief explanation of the drawing]

1(a-1f) are cross-sectional views in the order of steps of the manufacturing method according to the present invention, FIG.
ff) is a step-by-step sectional view of a conventional manufacturing method. In the figure, 1 is a p-type silicon substrate, 2 is a gate insulating film, 3 is a gate electrode, 4 is a field insulating film (SiO2 film), 5 is an n+ type region source/drain region, and 6 is a 5I02 film (insulating film). ), 7 is an electrode, 8 is a resist film mask, 9 is a 5i02 film (second 5i02; side wall),
10 is Si3N4 film, σJ Mamoto, Enikata Ichipou, tY Sakuzuj Figure 3
Dimensions O N completed ^ -- -Q Q ″.

Claims (1)

[Claims] A gate insulating film, a gate electrode film, a silicon oxide film, and a silicon nitride film are stacked on a semiconductor substrate and patterned into the shape of a gate electrode, and then a second silicon oxide film is deposited on the entire surface, and then a second silicon oxide film is deposited on the entire surface. The second silicon oxide film is anisotropically etched vertically over the entire surface to form a sidewall made of the second silicon oxide film around the gate electrode, and the source and drain forming regions of the semiconductor substrate are etched. A method of manufacturing a semiconductor device, characterized in that the semiconductor device is exposed.