JPS6376452A - Integrated circuit device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate array type semiconductor integrated circuit device.

[Conventional technology]

Conventionally, a gate array type semiconductor integrated circuit device, as shown in FIG. 4, is composed of an internal cell region 18 forming a logic circuit, an I10 buffer 19 serving as an interface between the internal cells and an external circuit, a bonding pad 20, and the like. ing. In addition to this, various power generation circuits are added to a bipolar gate array.

Achieve the desired logic function using multiple internal cells,
An LSI is constructed by laying out buffers for connection with external circuits at positions corresponding to desired leads of the package.

Usually, which internal cells to use, wiring between internal cells, and connections between internal cells and the I10 buffer are executed by an automatic placement and routing program.

Furthermore, in the manufacturing of LSIs, there are always manufacturing variations, which causes variations in the operating speed. The wafer is tested using an LSI tester or the like to determine whether this variation falls within the specifications.

As a testing method, it is possible to evaluate the speed using the logic function of the LSI alone to be tested, and if the operating speed of the 9LSI tester is faster than the operating speed of the LSI, measurement becomes possible.

The method shown in FIG. 5 is used as an example of a test method when the operating speed of the LSI is faster than the operating speed of the LSI tester. The example shown in FIG. 5 is an example of an LSI designed exclusively for this purpose rather than a gate array. If you create a ring oscillator in the section 21 and decide the number of inverter stages so that the oscillation frequency of this ring oscillator is lower than the operating speed of the LSI tester, the relationship between the logic function on the internal cell and its operating speed will be reduced. The manufacturing status of wafers can be tested without any problems.

[Problem that the invention seeks to solve]

In the example shown in FIG. 5 described above, since it was a specially designed product, there were no bonding pads or backing pads in the area 21. Therefore, the manufacturing state of the wafer could be tested using the method described above.

However, in the case of a gate array, as shown in Figure 4, I10
Since the buffers and bonding pads are arranged regularly, there is no space to lay out the ring oscillator shown in FIG.

Also, if you try to provide this space aggressively, you will need space for the bonding pad and ring oscillator, which increases the chip size and has the disadvantage of lowering the chip yield. .

Furthermore, applications that use all I10 terminals of one gate array naturally occur. Monitoring the oscillation frequency of the ring oscillator requires at least one pad, so if you use all the pads, there will be no pads left and you will not be able to check it.

In the conventional gate array described above, when trying to evaluate the speed using an LSI tester, the original function of the gate array is lost or the chip size increases, leading to a decrease in yield. The present invention has an original content in that speed evaluation can be efficiently performed using an LSI tester without impairing the original functions of the gate array.

[Means for solving problems]

The gate array type semiconductor integrated circuit device of the present invention has bonding pads on unused internal cells, and L
It is characterized in that a ring oscillator independent of the SI function or an oscillation output obtained by dividing the output of the ring oscillator by n is connected to the bonding pad.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the invention. One ring oscillator and two bonding pads are laid out in an area independent of the original LSI function. This ring oscillator and bonding pad are also registered as one function block.

Therefore, the connection between the ring oscillator and the bonding pad is also performed by the automatic wiring program. Therefore, the original function of the LSI cannot be prevented.

The first example shows the case of a 0MO8 gate array. In the case of 0MO8, the ring oscillator' is always operated because the power consumption is low. For this reason, only one bonding pad for monitoring the oscillation frequency is laid out on an unused cell. The bonding pad numbered 2 is used for testing in the Uni-No state, and no bonding is performed during assembly.

There is a transistor under the bonding pad 2, which is not flat, and the bonding pad is not flat unlike a normal bonding pad, but there is no problem in testing the wafer with a probe card.

Next, a second embodiment will be described with reference to the drawings.

In the first example, the power consumption is not a big concern because it is 0 MO8, but in the case of an ECL type bipolar gate array, the delay time per inverter stage is short, so the tester oscillates. K, which modulates the frequency by 7, requires a large number of ring oscillator stages, consumes a lot of power, and is extremely uneconomical.

Figure 2 shows the ECL ring oscillator. In this example, the pad numbered 3 is for the oscillation frequency motor, and the pad numbered 4 is for applying a constant voltage source VC8 from the outside during testing. If ■C8 is not applied to the pad numbered 4, the pace electrodes of the transistors numbered 5 and 6 are connected to the lowest potential 7 through a high resistance, so no current flows through the current switches numbered 8 and 9.

In this way, inverters 10 to 12, which consume power only during testing and do not consume power in actual use, have a similar circuit configuration. Further, the pad 3.4 is laid out in an unused portion of the internal cell as in the first embodiment.

FIG. 3 shows a third embodiment.

The gate delay of recent ECL gate arrays is 100P.
A high-speed version of 8 or less has been developed. In this case, if an attempt is made to oscillate a low frequency with the ring oscillator, the number of stages will be large, and a portion of the ring oscillator will occupy most of the internal cells, which will affect the original function of the LSI. In the case of such a high-speed gate array, if the output of the ring oscillator is divided by n as shown in FIG. 3, the oscillation frequency can be lowered more efficiently than by K. 13-15 in the same figure
is a part of a ring oscillator, 16 is an n frequency divider, and 17 is a pad.

Furthermore, in the first to third embodiments shown above, the output of the ring oscillator or branching unit is connected to the pad on the internal cell without going through an output buffer.

For this reason, the level of the busy output signal is different from the input/output signal level of the gate array, but this does not pose a problem since this signal is used only during wafer testing.

〔Effect of the invention〕

As explained above, the present invention lays out bonding pads on unused internal cells in the internal cell area of a gate array type semiconductor integrated circuit device, and outputs a ring oscillator or ring oscillator independent of the original function of the LSI. By connecting a circuit that divides the frequency of the gate array, it is possible to monitor the speed of the LSI without impairing its function as a gate array, and from this result, the manufacturing status of the LSI can be monitored. effective.

[Brief explanation of the drawing]

FIG. 1 shows the first embodiment of the present invention, FIG. 2 shows the second embodiment of the invention, FIG. 3 shows the third embodiment of the invention, and FIG. 4 shows the conventional gate array type. A semiconductor integrated circuit device, FIG. 5 shows an example of speed evaluation in a conventional wafer state. ...transistor,
7...Lowest potential, 8-9...Transistor, 10-12...Inverter, 13-15
...Inverter, 16...n frequency divider,
17...Bonding pad, 18...
・Internal cell area, 19...I10 buffer, 2
0...Bonding pad, 21...
Ring oscillator. ---)′ I /l! ? 3---3rd stage λ〉i pad 4-〆〆〉〉〉〉〉〉〉゛〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉 for 3-) 11 Ishiba Gua 3-15...Inburger/l---...Houbu 17...--E 3-de-Shoulder Pad Well 4TM/3...Inner Cell 4 Attack 12...17.ノ

Claims (1)

[Claims] A gate array type semiconductor integrated circuit device characterized in that a ring oscillator independent of its function as an LSI or an oscillation output obtained by dividing the output of the ring oscillator by n is connected to a bonding pad in an unused internal cell area.