JPS6375852A - Memory access system - Google Patents

Abstract

PURPOSE:To extend the address space by detecting whether the current memory cycle is a fetch cycle of instruction data or work data and accessing an instruction data storage memory and a work data storage memory independently of each other by the detection signal. CONSTITUTION:An address signal ADR is sent from a microprocessor 1 together with a status signal ST indicating whether the current memory cycle is a fetch cycle of instruction data or work data, and the signal ST is decoded by a detecting circuit 4 to send an instruction data status detection signal COM or a work data status detection signal DAT. Further, upper bits of the signal ADR are inputted to a decoder 5, and the other lower bits are inputted to an instruction data memory group 2 and a work data memory group 3, and chip select signals SEL1-SELn from the decoder 5 are inputted to memory groups 2 and 3 through gate circuit groups 6 and 7.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a memory access method.

[Prior Art] As is well known, in a stored program processor such as a microprocessor, when accessing a memory storing instruction data or work data, an address signal specifying a desired address is sent to the memory via an address bus. Addressing is done by giving . When data is to be written to a specified address, write data is provided through the data bus, and when data is to be read, read data is input to the processor through the data bus.

Therefore, it does not matter whether the data sent to and received from the memory is instruction-related data or work data (they are sent and received through the same route).

[Problems to be Solved by the Invention] However, since the number of bits of the address signal output from the processor is normally limited to 16 to 20 bits, when the storage capacity required for instruction data increases, it becomes difficult to store work data. The capacity is limited, and in the opposite case, the storage capacity of instruction data is limited. This makes system design difficult and, in some cases, requires two processors to substantially expand the address space that can be designated by address signals.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory access method capable of expanding an address space that can be specified by an address signal of a predetermined number of bits with a simple configuration.

[Means for Solving the Problems] The present invention takes into account that a status signal is output from the processor to indicate whether the memory cycle is an instruction data fetch cycle or a work data 7 fetch cycle. A decoder is provided that detects whether the current memory cycle is an instruction data fetch cycle or a work data fetch cycle based on a status signal, and a memory storing only instruction data or a memory storing only work data is provided depending on the detection signal of each fetch cycle. This allows memory to be accessed independently.

[Operation] In the command data fetch cycle, the memory storing only command data is accessed, and in the 7 work data fetch cycles, the memory storing work data is accessed. Therefore, the address space that can be specified by one address bus is doubled, and the data storage capacity of the entire system i
can be doubled.

[Embodiment] The figure is a block diagram showing an embodiment of the present invention. When the microprocessor 1 accesses the instruction data memory group 2 or the work data memory group 3, it determines whether the current memory cycle is an instruction data fetch cycle or not. A status signal ST indicating whether it is a work data fetch cycle is output and input to the detection circuit 4. Also, microprocessor 1
sends out an address signal ADR specifying a memory address in synchronization with the status signal ST.

Then, the status signal ST is sent to the decoder 4 of the detection circuit 4.
1 and becomes the instruction data status detection signal COM or the work data status detection signal DAT, and is further synchronized with the address signal ADR in the timing circuit 42 to become the timing signal TCOM or TDAT.

On the other hand, the upper bits of the address signal ADR are input to the decoder 5, and the remaining lower bits are input to the memory brains 21 to 2n constituting memory groups 2 and 3, respectively.
It is input in parallel to address inputs 31 to 3n.

The upper bit address signal input to the decoder 5 is applied to each memory brain 21 to 2n, 31 to 3 of the memory groups 2 and 3.
Chip select signal 5ELI to select each of n
5ELn.

These chip select signals 5EL1 to 5ELn are applied to the gate circuit groups 6 and 6 provided corresponding to the memory groups 2 and 3, respectively.
7 is input. The gate circuit group 6 7 is composed of n Nant gates corresponding to the n memory brains, and a timing signal TCOM is commonly input to one input of each Nant gate constituting the gate circuit group 6. Chip select signals 5EL1 to 5ELn are input to the other input one by one. Furthermore, the timing signal TDAT is commonly input to one input of each Nant gate constituting the gate circuit group 7, and the chip select signal 5 is input to the other input.
EL1 to 5ELn are input one by one.

The memory brains constituting the memory groups 2 and 3 are in a read/write state when the chip select input signal O8 is "0".

Therefore, if the microprocessor 1 outputs the address signal ADR such that the decoder 5 outputs the chip select signal 5ELI, and also outputs the status signal ST indicating that it is an instruction data fetch cycle, the timing circuit 42 timing signal TC from
Since OM is output, only the gate circuit group 6 becomes active, and the chip select signal 5EL1 is inputted as the chip select input signal CS of the memory brain 21 of the instruction data memory group 2 through the gate circuit group 6. .

As a result, the memory brain 21 becomes readable/writable, and the address specified by the lower bit side address signal in this memory brain 21 is accessed.

Conversely, when the status signal ST indicating that it is a work data fetch cycle is output from the processor 1, the gate circuit group 7 becomes active and one of the memory planes 31 to 3n in the work data memory group 3 is output. is designated by an address signal on the upper bit side, and an address within that memory brain is designated by an address signal on the lower bit side.

According to such a configuration, which memory group 2.3 is accessed is automatically determined by the operation of the detection circuit 4 and the gate circuit groups 6, 7, so the system design is based on instruction data and work data. This can be done using the same method as before, without having to be aware of the difference in the storage location. Furthermore, since the address space that can be designated by 〇R for the address signal is doubled, system design becomes easier.

[Effect of the Invention 1] As explained above, according to the present invention, the address space of a memory that can be specified by an address signal of a predetermined number of bits can be expanded with an extremely simple configuration. As a result, system design becomes easier.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Microprocessor, 2... Instruction data memory group, 3... Work data memory group, 4... Detection circuit, 6.7... Gate circuit group, 41... Decoder.

Claims (1)

[Scope of Claims] A system comprising a processor that outputs a status signal indicating whether a memory access cycle is an instruction data fetch cycle or a work data fetch cycle, and a memory accessed by the processor, A decoder is provided which detects whether the current memory cycle is an instruction data fetch cycle or a work data fetch cycle based on the status signal, and the memory storing only instruction data and the memory storing only work data are provided depending on the detection signal of each fetch cycle. A memory access method characterized by independently accessing memory in which .