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JPS6373719A - Bipolar code identification circuit - Google Patents

Bipolar code identification circuit

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Publication number
JPS6373719A
JPS6373719A JP21781586A JP21781586A JPS6373719A JP S6373719 A JPS6373719 A JP S6373719A JP 21781586 A JP21781586 A JP 21781586A JP 21781586 A JP21781586 A JP 21781586A JP S6373719 A JPS6373719 A JP S6373719A
Authority
JP
Japan
Prior art keywords
reference voltage
signal
duty
bipolar
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21781586A
Other languages
Japanese (ja)
Inventor
Shoji Watanabe
渡辺 昇治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21781586A priority Critical patent/JPS6373719A/en
Publication of JPS6373719A publication Critical patent/JPS6373719A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To identify a code without any error even in a bipolar signal with unsharpened waveform by controlling a reference voltage to a small value when a duty signal corresponding to a pulse width is small and controlling the reference value to a large value when the duty signal is large. CONSTITUTION:When outputs 12, 13 of a transformer 1 are inputted to a couple of line receivers 2, 3, they are compared with a reference voltage V0 of a reference voltage control circuit 8 and both the positive and negative bipolar signals are detected respectively. A duty detection circuit 7 outputs a voltage proportional to the pulse width of the output pulse of line receivers 2, 3, and the reference voltage control circuit 8 increases the identification level (reference voltage)V0 of the line receivers 2, 3 when the output voltage of the circuit 7 is large and decreases the identification level V0 when the output voltage of the duty detection circuit 7 is small. Thus, the operation is balanced and made stable when the duty signal reaches a value (e.g., 50%).

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、伝送路で帯域制限され、レベル変動や波形劣
化を被ったバイポーラ信号の符号を識別するバイポーラ
符号識別回路に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bipolar code identification circuit that identifies the code of a bipolar signal that is band-limited in a transmission path and suffers from level fluctuations and waveform degradation.

(従来の技術) 従来、この1のバイポーラ符号識別回路は、第3図に示
す如く、ラインレシーバ2,3に所定ノ基準電圧V、を
与え、トランス1からの入力信号12.13がこの基準
電圧70以上であれば“1″、■、以下であれば“0”
と識別していた。トランス1は、入カバイボーラ信号1
1の正負の極性を反転きせ、入カバイボーラ信号11の
正の極性のものをラインレシーバ2で、負の極性のもの
をラインレシーバ3で識別させるためのものであり、6
はクロック抽出回路、4,5はクロックの立上りで、入
カデーク14,15と同一データ16.17を出力する
D−フリップフロップである。
(Prior Art) Conventionally, as shown in FIG. 3, this bipolar code identification circuit 1 applies a predetermined reference voltage V to the line receivers 2 and 3, and input signals 12 and 13 from the transformer 1 apply to this reference voltage. If the voltage is 70 or above, “1”, ■, if it is below, “0”
I identified it as Transformer 1 has input capabybora signal 1
This is for inverting the positive and negative polarities of the incoming polarity signal 11, so that the line receiver 2 identifies the positive polarity of the input polarity signal 11, and the line receiver 3 identifies the negative polarity of the input polarity signal 11.
1 is a clock extraction circuit, and 4 and 5 are D-flip-flops that output the same data 16.17 as input data 14 and 15 at the rising edge of the clock.

(発明が鰐決しようとする問題点) 上述した従来例は、符号識別レベルV0が固定となって
いるので、第2図(a)のような矩形の入カバイボーラ
侶号の識別には有効であるが、第2図(b)に示すよう
に、伝送路により帯域制限を受け、波形がなまり、レベ
ルが低下したバイポーラ信号に対しては、入カバイボー
ラ信号の“1”と“O”の識別が不可能になるという欠
点があった。
(Problems that the invention attempts to resolve) In the conventional example described above, the code identification level V0 is fixed, so it is not effective for identifying rectangular input Kabaibora numbers as shown in FIG. 2(a). However, as shown in Figure 2(b), for bipolar signals whose waveforms are blunted and the level has decreased due to band limitations due to the transmission path, it is difficult to distinguish between "1" and "O" of the incoming bipolar signals. The disadvantage was that it became impossible.

本発明は、上記問題点に鑑みてなきれたもので、伝送路
においてレベル低下又は波形劣化を受けたバイポーラ信
号を確実に識別することのできるバイポーラ符号識別回
路を提供することを目的とする。
The present invention was developed in view of the above problems, and an object of the present invention is to provide a bipolar code identification circuit that can reliably identify bipolar signals that have undergone level reduction or waveform deterioration in a transmission path.

(問題点を解決するための手段) 前述の問題点を解決し、上記目的を達成するために本発
明が提供する手段は、基準電圧を出力する基準電圧制御
回路と、該基準電圧とバイポーラ信号の正極性と不極性
を分けてそれぞれに検出する一対のラインレシーバ−と
、該一対のラインレシーバ−のパルス出力に基づいて正
極性パルスと負極性パルスを同期して出力するパルス出
力手段と、前記パルス出力のパルス幅を検出して該パル
ス幅に相応したデユーティ信号を出力するデユーティ検
出回路とを設け、該デユーティ3号が小さいとき前記基
準電圧を小さく該デユーティ信号が大きいとき前記基準
電圧を大きく制御することを特徴とする。
(Means for Solving the Problems) In order to solve the above-mentioned problems and achieve the above objects, the present invention provides a reference voltage control circuit that outputs a reference voltage, a reference voltage control circuit that outputs a reference voltage, and a bipolar signal between the reference voltage and the bipolar signal. a pair of line receivers that separately detect the positive polarity and non-polarity of the line receiver, and a pulse output means that synchronously outputs a positive polarity pulse and a negative polarity pulse based on the pulse outputs of the pair of line receivers; and a duty detection circuit that detects the pulse width of the pulse output and outputs a duty signal corresponding to the pulse width, and when the duty No. 3 is small, the reference voltage is set low and when the duty signal is large, the reference voltage is set. It is characterized by great control.

(実施例) 第1図は本発明の一実施例を示したブロック図である。(Example) FIG. 1 is a block diagram showing one embodiment of the present invention.

1はバイポーラ入力信号11の極性を反転させるトラン
スであり、トランス1の出力12.13を一対のライン
レシーバ2,3に入力すると、基準電圧制御回路8の基
準電圧■、と比較してバイポーラ信号の正極性と負極性
を分けてそれぞれに検出する。6はクロック抽出回路、
4及び5は、D−フリップフロップであり、クロック抽
出回路6のクロックの立上りで動作し、一対のラインレ
シーバ2,3に相応するパルス、即ち正極パルス16及
び負極パルス17のそれぞれを出力する。7はデユーテ
ィ検出回路であり、ラインレシーバ2.3の出力パルス
のパルス幅に比例した電圧(デユーティ信号)を出力す
る。8は基準電圧制御回路であり、デユーティ検出回路
7の出力電圧が大なるときにはラインレシーバ2.3の
識別レベル(基準電圧)v6を上げる働きをし、デユー
ティ検出回路7の出力電圧が小なるときには識別レベル
V、を下げる働きをする。
1 is a transformer that inverts the polarity of the bipolar input signal 11. When the outputs 12 and 13 of the transformer 1 are input to a pair of line receivers 2 and 3, they are compared with the reference voltage ■ of the reference voltage control circuit 8 and the bipolar signal is The positive and negative polarities of are detected separately. 6 is a clock extraction circuit;
4 and 5 are D-flip-flops which operate at the rising edge of the clock of the clock extraction circuit 6 and output pulses corresponding to the pair of line receivers 2 and 3, that is, a positive pulse 16 and a negative pulse 17, respectively. 7 is a duty detection circuit which outputs a voltage (duty signal) proportional to the pulse width of the output pulse of the line receiver 2.3. Reference numeral 8 denotes a reference voltage control circuit, which functions to raise the discrimination level (reference voltage) v6 of the line receiver 2.3 when the output voltage of the duty detection circuit 7 becomes large, and when the output voltage of the duty detection circuit 7 becomes small. It functions to lower the discrimination level V.

このように構成された回路に第2図(b)のようなバイ
ポーラ信号が入力されると、デユーティ検出回路7の出
力電圧(デユーティ信号)が小さくなるので、基準電圧
制御回路8はラインレシーバ2.3の識別電圧(基準電
圧V、)を下げるように動作し、デユーティ信号がある
値(例えば、50%)となったときに、動作が平衡して
安定する。。
When a bipolar signal as shown in FIG. 2(b) is input to the circuit configured in this way, the output voltage (duty signal) of the duty detection circuit 7 becomes small, so the reference voltage control circuit 8 It operates to lower the identification voltage (reference voltage V) of .3, and when the duty signal reaches a certain value (for example, 50%), the operation becomes balanced and stable. .

また、第2図(C)のようなバイポーラ信号が入力きれ
ると、デユーティ検出回路7の出力電圧が大きくなるの
で、基準電圧制御回路8はラインレシーバ2,3の識別
電EE(基準電圧V、)を上げるように動作し、この場
合も、デユーティが前述の所定の値に達したときに動作
が平衡して安定する。
Furthermore, when the bipolar signal as shown in FIG. ), and in this case as well, the operation becomes balanced and stable when the duty reaches the above-mentioned predetermined value.

第2図(a)の矩形のバイポーラ信号が入力きれたとき
は既にデユーティが50%となっているので、基準電圧
制御回路8の出力電圧■。は一定に保たれる。
When the rectangular bipolar signal shown in FIG. 2(a) is inputted, the duty is already 50%, so the output voltage of the reference voltage control circuit 8 is ■. is kept constant.

(発明の効果) 以上説明したように、本発明によれば、常に最適な符号
識別レベル(基準電圧)を設定できるので、伝送路で帯
域制限を受け、波形のなまったバイポーラ信号に対して
も、誤りなく符号を識別できる効果がある。
(Effects of the Invention) As explained above, according to the present invention, it is possible to always set the optimum code discrimination level (reference voltage), so even bipolar signals whose waveforms are distorted due to band limitations on the transmission path can be set. This has the effect of allowing codes to be identified without error.

また、伝送路でS/N(信号対雑音比)の劣化を受けた
バイポーラ信号を識別する場合にも有効である。
It is also effective in identifying bipolar signals whose S/N (signal-to-noise ratio) has deteriorated on a transmission path.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のバイポーラ符号識別回路の一実施例を
示すブロック図、第2図はバイポーラ符号識別回路に入
力される信号の波形図、第3図は従来例を示したブロッ
ク図である。 1・・・トランス、2,3・・・ラインレシーバ、4゜
5・・・D−フリップフロップ、6・・・クロック抽出
回路、7・・・デユーティ検出回路、8・・・基中電圧
制御回路。
FIG. 1 is a block diagram showing an embodiment of the bipolar code identification circuit of the present invention, FIG. 2 is a waveform diagram of a signal input to the bipolar code identification circuit, and FIG. 3 is a block diagram showing a conventional example. . 1...Transformer, 2,3...Line receiver, 4゜5...D-flip-flop, 6...Clock extraction circuit, 7...Duty detection circuit, 8...Base voltage control circuit.

Claims (1)

【特許請求の範囲】[Claims] 基準電圧を出力する基準電圧制御回路と、該基準電圧と
バイポーラ信号の信号電圧とを比較し該バイポーラ信号
の正極性と負極性を分けてそれぞれに検出する一対のラ
インレシーバーと、該一対のラインレシーバーのパルス
出力に基づいて正極性パルスと負極性パルスを同期して
出力するパルス出力手段と、前記パルス出力のパルス幅
を検出して該パルス幅に相応したデューティ信号を出力
するデューティ検出回路とを設け、該デューティ信号が
小さいとき、前記基準電圧を小さく、該デューティ信号
が大きいとき前記基準電圧を大きく制御することを特徴
とするバイポーラ符号識別回路。
A reference voltage control circuit that outputs a reference voltage, a pair of line receivers that compare the reference voltage and the signal voltage of the bipolar signal and separately detect the positive polarity and negative polarity of the bipolar signal, and the pair of line receivers. a pulse output means that synchronously outputs a positive polarity pulse and a negative polarity pulse based on the pulse output of the receiver; and a duty detection circuit that detects a pulse width of the pulse output and outputs a duty signal corresponding to the pulse width. 1. A bipolar code identification circuit, wherein the reference voltage is controlled to be small when the duty signal is small, and the reference voltage is controlled to be large when the duty signal is large.
JP21781586A 1986-09-16 1986-09-16 Bipolar code identification circuit Pending JPS6373719A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21781586A JPS6373719A (en) 1986-09-16 1986-09-16 Bipolar code identification circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21781586A JPS6373719A (en) 1986-09-16 1986-09-16 Bipolar code identification circuit

Publications (1)

Publication Number Publication Date
JPS6373719A true JPS6373719A (en) 1988-04-04

Family

ID=16710170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21781586A Pending JPS6373719A (en) 1986-09-16 1986-09-16 Bipolar code identification circuit

Country Status (1)

Country Link
JP (1) JPS6373719A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008232685A (en) * 2007-03-19 2008-10-02 Yokogawa Electric Corp Semiconductor testing apparatus
JP4836152B1 (en) * 2011-04-13 2011-12-14 マイクロメーション株式会社 Eyeglass frame slip-off prevention device and eyeglass frame

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008232685A (en) * 2007-03-19 2008-10-02 Yokogawa Electric Corp Semiconductor testing apparatus
JP4836152B1 (en) * 2011-04-13 2011-12-14 マイクロメーション株式会社 Eyeglass frame slip-off prevention device and eyeglass frame

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