JPS6369321A - Semiconductor device - Google Patents

Abstract

PURPOSE:To attain high speed operation by adopting the constitution that the accessing is entered immediately after an internal clock is generated and precharging is finished. CONSTITUTION:An internal clock pulse generating, circuit s receiving a clock pulse being a symmetrical square wave and generating an asymmetrical square wave internal clock pulse CK at the 1st logic level for a time required for precharging and at a 2nd logic level for a time required for access, is provided. The waste time during the precharge cycle is eliminated by generating the internal clock pulse being at a 1st logic level for a time required for precharge and at the 2nd logic level for a time required for accessing thereby applying precharge and accessing in comparison with the precharge/accessing by a symmetrical square wave clock pulse, the high frequency clock pulse is adopted and high speed operation is attained. 1, address register.

Description

[Detailed Description of the Invention] [Summary] The present invention is the same clock! ! ] type programmable logic array (PLA: DrooraIIlo+
In this system, an internal clock is generated and the access operation starts immediately after the bridge 1F-page is completed, thereby realizing high-speed operation.

(Industrial Field of Application) The present invention applies to semiconductor devices, particularly clock-synchronized PLAs.

A PLA configured with 0MO8 often uses a clock synchronization method to cut static ml.

In this clock-same-one PLA, precharging and access are performed sequentially within one cycle of the low clock pulse.

(Prior Art) FIG. 3 shows a circuit diagram of an example of a conventional semiconductor device. In the figure, address register 1 and inverter 2 are shown in Figure 4 (
A clock pulse CK as shown in A) is supplied. The clock pulse GK shown in FIG. 4(C) whose polarity is inverted by the inverter 2 is a P-channel to 10S type transistor Tr+, an N-channel 1-channel MO3 type transistor Trx.
and is applied to each gate of the P-channel MO3 type transistor Trs.

Between the drain of the transistor Tr+ and the drain of the transistor Tr3, n N-channel MO8 type transistors Tr2+ to Tr2Tl are connected as shown in the figure, and each gate of the transistors T'21 to TI'2Tl is connected to an address. N-bit address data is supplied from register 1 in parallel at the timing shown in FIG. 4(B).

The common connection point of both drains of transistors Tr+ and Tr;++ (a node EIj) is connected via an inverter 3 to the gate of an N-channel MO8 type transistor Tra. Transistor Tr+.

Tr21 to Tr2T+ and the inverter 3 constitute an AND array. Transistor T "In total including 41 m
N-channel MO8 type transistors Tr41 to Tr
im has its drains commonly connected to the drain of the P-channel MO8 transistor Trs and the input terminal of the inverter 6, and its sources are grounded. These transistors Tr41 to Tram, Trs, and inverter 6 constitute an OR array, and each gate of the transistors Tr42 to Tr4 is connected to other (m-1) AND arrays via terminals 4.5, etc. An output signal is applied.

In the semiconductor device (i.e. PLA) with the above configuration,
Period tCK)l during which clock pulse CK is at high level
is when transistor Tr+ is on and transistor Trs
is turned off, so the connection point ○ is turned off regardless of the address data.
As shown in FIG. 4<D>, the potential becomes approximately equal to the power supply voltage Voo through the transistor Tr+, and the connection point () is precharged.

This high level voltage is made low level by the inverter 3 and then applied to the gate of the transistor Tr4+,
Turn this off. On the other hand, since the transistor Trs is turned on by the low-level clock pulse GK, the potentials of the transistors Trs and Tr41 to T (common connection point with 4T+1) become as shown in FIG. 4(E). , becomes high level and is precharged when a time tpc has elapsed since the clock pulse CK became high level.

Next, the clock pulse CK becomes low level, and during the low level period tCKL, the transistor Tr+ is off and the transistor Tr3 is on, so the potential of the connection point ◎ is the same as the n-bit address data from the address register 1. When all bits are “1” (7), transistor T
Since rz+~Tr2Tl are each turned on, they become low level, and even 1 bit of address data becomes °゛0'.
', it remains at a high level.

On the other hand, since the transistor Trs is off during this 1 (tcKL), the potential at the connection point ○ becomes high level or low level depending on the address data.The potential at the connection point O is output after the polarity is inverted by the inverter 6. It is output to terminal 7. FIG. 4(F) shows the output signal waveform of this output terminal 7.

Therefore, when clock pulse GK is at low level, GS
Address data of I t CK L is accessed as shown in FIG. 4(F). Therefore, the time jpo required for accessing the PLA must be less than or equal to tcKL, and the time tpc required for precharging must be less than tCKH.
Must be less than or equal to

Further, there is usually a relationship of tPc<tpo between the time tpc required for precharging and the time tPD required for access.

[Problems to be Solved by the Invention] The clock pulse CK and "k" used in the above clock 1411 type PLA are, for example, 20M1.
Due to the high repetition frequency, such as -1z, a symmetrical square wave with a duty cycle of 50% must be used. Therefore, the periods tcK+-1 and tc are equal to each other. On the other hand, from the above-mentioned relationship tpc<ipo,
Generally, the longer tpo is made equal to the low level period tcK of the D clock pulse CK. Therefore, the minimum cycle time tcYcl is tcYc+=2°tCKL Chicken 2tpo>tpo+tpc (1), and the fourth
The interval 1n shown by tpo-tpc in FIG. 1F is a wasted time that is not used for either precharging or access, and this gives time to high-speed operation.

The present invention was created in view of the above points, and an object of the present invention is to provide a semiconductor device that can realize high-speed operation.

[Means for solving problems]

The semiconductor device n of the present invention is supplied with a clock pulse having a symmetrical square wave, and has the same period as the clock pulse, and the time required for precharging is at a first logic level, and the time required for access is at a second logic level. An internal clock generation circuit is provided for generating an asymmetric square wave internal clock pulse.

[Effect]

In a clock-synchronized semiconductor device in which address data is accessed after precharging a predetermined node within each period of a symmetrical square wave clock pulse, an internal clock generation circuit generates a first logic level and a second logic level. An internal clock pulse with a waveform consisting of alternating levels is extracted.

After precharging the predetermined node during a first logic level period, this internal clock pulse causes address data to be accessed continuously during a second logic level period.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the product of the present invention. In the same figure, the same components as those in FIG. In FIG. 1, 8 is an internal clock generation circuit, which includes P-channel MOS transistors Trs,
Tr+o, N-channel MO8 type transistor Tr7+
~Tr7n, Tr6°Tr91~Trstn, inverters 9 and 10, and a two-man power NAND circuit 11.

Between the drain of the transistor Trs and the drain of the transistor Tra, there are n transistors Tr7+ to T.
r7η is connected as shown in the figure, and the transistor Tr
The power supply voltage Voo is always applied to each gate of 7+ to Tr7π together with the source of the transistor Trs, and
r y l to 7r7η are always on. The common connection point between the drains of the transistor T6 and the transistor T91 is connected via an inverter 9 to the gate of the transistor T91.

Transistors Trs, Tr71 to Tr2m, and Tr
6 and an inverter 9 is a transistor T'
+, Tr2+ to TrzT1. A circuit configuration similar to that of the AND array consisting of the TI'3 and the inverter 3 is made by using the same number of transistors. This is because the time tpc required for precharging is made the same for both circuits.

In addition, the drains of the m transistors T91 to Tr9m are commonly connected to each other, and the sources to each other are commonly connected to each other, and the common connection point of each train of transistors Trq+ to Tr9m @
is the drain of the transistor Tree and the inverter 10
(respectively) are connected to the input terminals of the Furthermore, the gates of the transistors 7r 92 to Tr 9tn are grounded and are always turned off. This circuit consisting of the transistors Tr s + to Tr 9 m, 7r I6 and the inverter 10 includes the transistors Tra to Tr
4m.

The circuit configuration is similar to that of the OR array consisting of the Trs and the inverter 6 with the same number of transistors. As in the case above, this is the time t required for precharging.
This is to make pc the same between both circuits.

The two-manufactured NAND circuit 11 generates a signal obtained by performing a NAND with the clock pulses from the inverter 10 and the input terminal 12 as an internal clock pulse CKI. N
The output terminal of the ΔND circuit 11 is the transistor Tr+, Tr
z, Trs, Trs.

Connected to the gates of Tra and Trio, respectively.

Next, the operation of the semiconductor device having the above configuration will be explained. As shown in FIG. 2(A), the address register 1 and input terminal 12 have a symmetrical waveform with a duty cycle of 50%, in which the high level period tcKH' of - period and the low level interval tcKL' of m are equal. Clock pulses GK arrive respectively. As a result, from address register 1, the second
Address data is output at the timing shown in FIG.

During the low level period tCKL' of the clock pulse CK, the output signal of the NAND circuit 11 is at a high level regardless of the output logic level of the inverter 10, so that the transistors Trl, Trs, T
rs and Tr+++ are respectively turned off, while transistors Trs and Tra are respectively turned on. transistor T
Since 71 to ry 71 are always on as described above, the potential of the connection node 9 is low level as shown in Figure 2 (C), so the output signal of inverter 9 is high level. becomes.

As a result, the transistor Tr91 is turned on, and since the transistor Tr+a is off as described above, the potential at the connection point (node) O becomes a low level as shown in FIG. 2(D). The output signal 10 becomes high level as shown in FIG. 2(E).

In this state, the clock pulse CK then becomes high level, so the output signal of the NANO circuit 11 becomes low level. This low level output signal of the NANO circuit 11 is applied to the transistors Tr+, Tr3. Trs,
Trs.

It is applied to each gate of Tra and Tr+, turning on transistors Tr+, Trs, Trs, and Trio, respectively, and turning off transistors Tr3 and Trs, respectively.

As a result, the potential at the connection point ◯ becomes high level as shown in FIG. 2(C), and the transistor Trs+ is turned off via the inverter 9. At this time, transistor Tr+o
is on, the potential at the connection point O becomes high level as shown in FIG. 2(D).Therefore, the output signal of the inverter 10 becomes low level as shown in FIG. 2(E).

From the time when the output internal clock pulse CKI of the NAND circuit 11 shown in FIG. 2(F) becomes low level, the output signal of the inverter 10 becomes low level, and the NAND circuit 1
Until the internal output clock pulse CKI of 1 becomes high level, there is a certain time delay due to the transmission delay time of each transistor, which is shorter than the high level period tCKH' of the clock pulse CK.

Furthermore, when the above-mentioned internal clock pulse CKI becomes low level, the transistor Tr+ turns on and Tr3 turns off, so the potential of the connection QE) changes to the internal clock pulse CKI.
Figure 2 (
As shown in G), it becomes high level and is precharged. Therefore, the time tpc required for this precharge is the second
As shown in Figure (F), it is the time from when the internal pulse CKI becomes low level until it changes to high level.

When the internal clock pulse CKI becomes high level, the transistor Tr+ turns off, and the
Since r3 is turned on, the potential at the connection point ◯ is at a low level only when the n-bit address data of the address register 1 is 1'', and is at a high level otherwise.

In other words, the potential at 8 points (Ei) is the address register 1.
It changes depending on the address data. Here, if all n bits of address data are "1", while the internal clock pulse CKI is at high level ill+H1, the potential of () becomes low level as shown in Figure 2 (G), and ()
The potential at the output terminal 7 changes to a low level as shown in FIG. 2(H), and the potential at the output terminal 7 changes to a high level as shown in FIG. 2(1).

The delay time indicated by tpo in FIG. 2 (1) is the time required for access, and this time tpo is the tp of the conventional PLA.
o, but longer than the low level period tcKL' of clock pulse GK. In this embodiment, the clock pulse G
This is because the time tpo required for access can include a part of the period of 111 high-level questions tCKH' of K.

In this way, according to this embodiment, the transistor Tr immediately after precharging is
+ is turned off and the transistor Tr3 is turned on to start the address data access operation, so the minimum cycle time jcvcz is jcvcz=2°tCKL' tpo+tpc2.

Therefore, the minimum cycle time jcvcz in this example is:
The minimum cycle time tcYcI shown in the above formula (1)
It is shorter because the one wasted interval (tpo-tpc) is eliminated.

As a result, the repetition frequency of the clock pulse GK of this embodiment can be made higher than that of the clock pulse GK of the conventional circuit, and high-speed operation is possible.

(Effects of the Invention) According to the present invention, an internal clock pulse is generated at a first logic level for a time required for precharging and at a second logic level for a time required for access, thereby precharging. Because charging and access are performed, it is possible to eliminate wasted time during the precharge cycle compared to conventional devices that perform precharging and access using symmetrical square wave clock pulses. It has features such as high-speed operation and high-speed operation.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the device of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation of the circuit shown in FIG. 1, FIG. 3 is a circuit diagram showing an example of a conventional device, and FIG. 4 3 is a signal waveform diagram for explaining the operation of the circuit shown in FIG. 3. FIG. In the figure, 1 is an address register, 7 is an output terminal, 8 is an internal clock generation circuit 11, which is a NAND circuit, and 12 is an O-clock pulse input terminal. Agent Patent Attorney Sada Igata - A total of 4 diagrams of the one-cuspid cell A array of the inventive device; -1 quantity Diagram formation explanation 1) ) Group] Zoto 1?ko Figure 3

Claims (1)

[Claims] In a clock-synchronized semiconductor device in which address data is accessed after precharging a predetermined node within each cycle of a clock pulse that is a symmetrical square wave, the clock pulse is supplied and the clock pulse is an internal clock generating circuit that generates an asymmetrical square wave internal clock pulse having the same period as a clock pulse and having a first logic level for the time required for the precharge and a second logic level for the time required for access; 8), and after precharging the predetermined node during the first logic level period of the internal clock pulse, the address data is subsequently accessed during the second logic level period. A semiconductor device characterized by: