JPS6367769A - Dynamic semiconductor storage device - Google Patents

Abstract

PURPOSE:To avoid leakage between trenches by a method wherein a high concentration diffused layer is buried in a trench region of a semiconductor substrate and a low concentration epitaxial layer is formed on it. CONSTITUTION:A hot oxide film 16 is formed on a P-type substrate 1. Then the oxide film 16 is selectively etched by photoetching. After that, an oxide film 17 is formed by hot oxidation to form a protective mask oxide film for ion implantation and boron ions are implanted. The concentration of the implantation is so selected to be the maximum allowable value under the conditions that the concentration is lower than the concentration in the side walls of a trench capacitor and that the junction breakdown strength is higher than the breakdown strength required for a dynamic RAM. After the implanted ions are driven to be diffused, the oxide film is totally removed. Then an epitaxial layer 3 is deposited. At that time, boron ions in the diffused layer 2 are also diffused into the epitaxial layer 3 by solid diffusion. With this constitution, the respective trenches are separated from each other by the high concentration impurity diffused layer so that leakage between cells can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic semiconductor memory device that has a high integration density and a large capacity, and is improved so that malfunctions due to alpha particles are less likely to occur.

[Prior Art] A dynamic semiconductor device (hereinafter referred to as rDRAMJ) in which a 1-bit memory cell is configured by one transistor and one capacitor has a simple structure and a one-bit memory cell.
Since the memory cell area per bit is small, this structure is most suitable for large capacity storage devices. ' However, the DRAM with the above structure has a fatal problem. This is because α particles emitted from a radiation source contained in semiconductor materials can generate hole-electron pairs in the semiconductor substrate, and these electrons may cause soft errors that invert data stored in memory cells. It is. This soft error occurrence rate is more likely to occur as fewer electrons are stored in the capacitor. Therefore, it has been conventionally said that no matter how small the memory cell is, a capacitor with a capacitance of at least 30 fF or more is required.

However, when trying to create a DRAM with a large capacity of 4 megabits or 10 megabits or more, the memory cell size is less than 10 μm2, and to obtain the above capacity with a cell of this size, an extremely thin gate oxide film of less than 100 A is required. becomes. However, it is extremely difficult to obtain a highly reliable gate oxide film of 100 A or less. Therefore,
The thickness of the gate oxide film remains the same as before, but in order to increase the capacitance, we have developed a structure in which the capacitor is formed three-dimensionally.
That is, trench capacitor structures are becoming common.

Trench capacitors are made by, for example, anisotropically etching a silicon substrate, selectively inverting its sidewalls to n-, forming a gate oxide film, and filling the trench with an electrode material such as n-type polysilicon. It will be done. Theoretically, the deeper the groove, the greater the capacitance.

FIG. 2 shows a plan view of an example of a DRAM memory cell having a trench capacitor, and FIG. 3 shows a cross-sectional view thereof. In the figure, 1 is a p-type substrate, 4 is a selective isolation oxide film (S
OP), 5 is a p+ layer for a channel stopper, 6 is a trench, 7 is an n-layer formed on the side wall of the trench, 8 is a first gate oxide film, and 9 is an n-layer polysilicon filling the trench. Gate electrode, 10 is a second gate oxide film for the gate of the transistor, 11 is polycide for the second gate electrode, 12 is an n+ diffusion layer used for the source/drain of the transistor or wiring, 13 is a CVD oxide film, 14
1 is a contact, and 15 is an aluminum wiring.

Next, the operation will be explained. When writing a signal, the second gate electrode 11 of the word line is set to high level, the bit line is selected, and the voltage is set to high or low level to exchange electrons in the n-diffusion layer 7 of the capacitor. When reading a signal, the second gate electrode 11 of the word line is selected and set to high level, the bit line is selected, the electrons accumulated in the capacitor are written to the bit line, and the change in the potential of the bit line is detected by the sense amplifier. to determine whether it is “1” or “0”.

[Problems to be Solved by the Invention] In a DRAM memory cell having a conventional trench capacitor, p! Since the trench is directly formed in the 42 substrate, the deep part of the trench is separated from adjacent cells only by a lightly concentrated impurity. Therefore, leakage that is not dependent on gate voltage and is called a punch-through phenomenon occurs between adjacent cells. In order to prevent leakage due to this punch-through phenomenon, there are methods of increasing the concentration of the p-type substrate or forming a p-type well in the memory cell area on the p-type substrate, but in these methods, the substrate constant of the transistor may become large, resulting in a slow operation speed, or the junction capacitance at the contact portion, in other words, the bit line capacitance may become large, resulting in a failure to operate.

The present invention was made to solve the above-mentioned problems, and is intended to prevent leakage between trenches without adversely affecting transistors or bit lines.

Means for Solving Problem c] The dynamic semiconductor memory device according to the present invention includes a method in which a highly doped diffusion layer is buried in advance in a trench region of a semiconductor substrate, and a lightly doped epitaxial layer is formed thereon. It is something to keep. Then, a memory cell having a conventional trench capacitor structure is formed on such a substrate.

[Function] In the dynamic semiconductor device according to the present invention, since the trench regions are separated by the heavily doped buried diffusion layer, leakage current is reduced even in the deep part of the trench. Also,
Since everything other than the capacitor is formed of an epitaxial layer with the same level of quality as a conventional substrate, there is no adverse effect on transistors, etc., and a device with high speed and a wide operating range can be achieved.

Embodiment of the invention] Hereinafter, an embodiment of the invention will be described with reference to the drawings. 1st
In the figure, 1 is a p-type substrate, 2 is a buried layer with a high concentration of p-type impurities, 3 is a p- epitaxial layer, 4 is a selective isolation oxide film (SOP), 5 is a p-type diffusion layer for a channel stopper,
6 is a trench, 7 is an n diffusion layer selectively formed on the side wall of the trench, 8 is a first gate electrode film, 9 is n+ polysilicon of the first gate electrode, 10 is a second gate oxide film, 11
12 is the polycide of the second gate electrode, 12 is the n+ diffusion layer forming the source and drain of the transistor, and 13 is the CVD
An oxide film, 14 a contact, and 15 an aluminum wiring.

The conventional device is that a p-layer 2 is selectively formed under the capacitor, and a p-epitaxial layer 3 is formed selectively under the capacitor.
The difference is where they are deposited.

FIG. 4 shows a method of forming selectively formed p+ layer 2 and p- epitaxial layer 3. Referring to Figure 4,
A thermal oxide film 16 of 7,000 layers is formed on a p-type substrate l having a thickness of 10 to 20 Ωcm. Next, the oxide film 16 is selectively etched by photolithography. Next, in order to form a protective mask oxide film for ion implantation, an oxide film 17 of 50 OA is obtained by thermal oxidation (FIG. 4(A)).

Next, boron ions are implanted at 50 KeV.

This implantation amount is lower than the concentration formed on the sidewalls of the trench capacitor, and the maximum concentration is selected under the condition that the junction breakdown voltage is higher than the breakdown voltage required for the DRAM. After drive diffusion of the implanted ions, the oxide film is removed from the entire surface (FIG. 4(B)). Next, an epitaxial layer 3 of about 1 to 3 μm is deposited with a thickness of 10 to 20 Ωcm. At this time, the concentration of epitaxial debris formation is between 1000°C and 1
Since the temperature is 150° C., boron in the diffusion layer 2 also diffuses into the epitaxial layer 3 by solid-state diffusion. Further, due to autodoping, the epitaxial layer 3 on the boron layer 2 has a boron concentration higher than that intended for doping. The thickness of the epitaxial layer 3 is selected so that the autodoping layer 18 sufficiently overlaps the p+ layer of the selective isolation oxide film region 4 intended to serve as a channel stopper.

After forming the epitaxial layer 3 described above, a memory cell is formed by a conventional method. Next, the manufacturing method will be briefly explained with reference to FIG.

First, in order to prevent stress when forming the selective isolation oxide film 4, a thermal oxide film of 500A is formed. Next, a 1000A nitride film is deposited. Next, the nitride film is etched by photolithography, and boron ions are implanted to form a channel stopper. Next, field oxide film 4 is formed by selective oxidation. At this time, the channel stopper p+ layer 5 is sufficiently diffused so that it overlaps with the auto-doping layer 18 described above.

Next, trenches 6 are formed by anisotropic silicon etching. Next, for example, AsSO is deposited and driven in to obtain a shallow n-diffusion layer 7. After forming a thin gate oxide film 8 of about 100 Å by thermal oxidation, phosphorus-doped polysilicon is deposited. Next, a resist is applied and etched back to form the first gate electrode 9 buried in the trench. Next, 200
A gate oxide film 10 of a transistor of approximately A size is formed by low-temperature oxidation, and phosphorus-doped polysilicon is deposited.

Next, silicide, for example WSix, is deposited by sputtering, and a polycide gate electrode 11 is formed by photolithography.
form. Next, the polycide gate electrode 11 is self-aligned and arsenic is ion-implanted and annealed.
+ layer 12 is obtained. Next, a CVD oxide film 13 is deposited and contacts 14 are opened. Next, ArLSi is deposited by sputtering, and aluminum wiring 15 is formed by photolithography.

The above is the manufacturing method.

In addition, in the above embodiment, the peripheral circuit is formed of NMO3I-transistors, but even if it is formed of CMOS transistors, it is possible to obtain exactly the same effect as the memory cell structure shown in Fig. 1. It is.

Further, in the above embodiment, only the n-diffused layer is provided around the trench, but a p-layer may be provided at a deeper depth, as in the case of a HiC structure, to increase the capacitance of the capacitor by the junction capacitance.

Furthermore, although the above embodiment shows the case where the bit line is made of aluminum wiring, the above effect is the same even if the bit line is made of polycide as in the 3-poly system.

[Effects of the Invention] As described above, according to the present invention, trench portions are separated by a high concentration impurity diffusion layer, leakage between cells is prevented, and the surface layer of a semiconductor substrate forming a transistor is is formed of an epitaxial layer with a low concentration of impurities, and there is no substrate effect or lightning on the bit line, so it is possible to obtain a dynamic semiconductor memory device that is resistant to soft errors, has high speed, and has a large margin.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a DRAM cell according to an embodiment of the present invention, FIG. 2 is a plan view of a conventional trench capacitor cell, FIG. 3 is a sectional view of FIG. 2, and FIG. 4 is a cross-sectional view of a conventional trench capacitor cell. FIG. 3 is a diagram showing part of the manufacturing process for making the device. In the figure, 1 is a p-type substrate, 2 is a p-type high concentration impurity physical layer, 3 is a p-epitaxial layer, 4 is a selective isolation oxide film,
5 is a p+ layer for a channel stopper, 6 is a trench, 7 is an n diffusion layer formed on the side wall of the trench, 8 is a first gate oxide film, 9 is an n+ polysilicon film, 10 is a second gate oxide film, 11 is a second gate oxide film 2 Polycide of the gate electrode, 12 is an n+ diffusion layer, 13 is a CVD oxide film, 14 is a contact, 15 is an aluminum wiring, 16 is a thick thermal oxide film, 17 is a thin thermal oxide film that serves as a protective film during ion implantation, 18 is an autodoped p-layer. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (3)

[Claims] (1) A dynamic semiconductor memory device having a memory cell consisting of one transistor and one capacitor formed on a semiconductor substrate, in which the capacitance of the capacitor is increased by a trench structure, wherein the semiconductor substrate has a trench structure. A dynamic semiconductor device comprising: a buried diffusion layer of high concentration impurity formed in advance in a region including a capacitor formation portion; and an epitaxial layer of low concentration impurity formed in advance above the buried diffusion layer. type semiconductor memory device. (2) The dynamic semiconductor memory device according to claim 1, wherein the semiconductor substrate is a p-type semiconductor substrate. (3) The buried diffusion layer is formed of boron with a concentration on the order of 10^1^8 cm^-^3, and the epitaxial layer is formed with a concentration of 3 to 8 x 10^1^5 cm^-
Formed by ^3 order boron, and 1 to 3μ
3. The dynamic semiconductor memory device according to claim 2, wherein the dynamic semiconductor memory device has a thickness of m.