JPS6367053A - Receiver for serial data - Google Patents

Abstract

PURPOSE:To simplify a constitution by providing a counter to which a receiving clock is supplied, and a memory means for writing a serial data in a bit position where a parallel data is decoded by the output of said counter. CONSTITUTION:When a receiving clock signal is supplied to a serial clock terminal 10, the counted value of a counter 100 is varied, and by following it up, the bit position of a random access memory 300 is also switched, and written in the data memory 300 from a serial input terminal 20. When the value of the counter 100 goes to 0000, an interruption request signal is sent out to an interruption output terminal 30, and a microprocessor 300 reads a parallel data through a data bus 200.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a serial data receiving device, and provides a receiving device that has an extremely simple configuration yet can handle advanced communications, and is particularly suitable for microprocessors. The purpose of this is to realize a device that is

Conventional technology Conventionally, one-chip microb C1-1 = '7 ・
A serial data communication device, which is widely used in the industry, is composed of a shift register, a shift counter, and a buffer register, and a typical example thereof is disclosed in Japanese Patent Publication No. 60-58482 (hereinafter abbreviated as Document 1). ) is shown.

Problems to be Solved by the Invention Incidentally, since the device shown in Document 1 is mainly composed of random logic circuits, the number of wires between each circuit block is large, and the circuit configuration becomes complicated. Therefore, when communicating a large amount of data at once, it is necessary to rely on the software for much of the processing.In order to perform more advanced communication or high-speed data transfer, It was necessary to change the circuit configuration each time.

Means for Solving the Problems In order to solve the above-mentioned problems, in the serial data receiving device of the present invention, a receiving clock is supplied to a counter (J(), parallel data is sent to a data bus, The communication means includes a memory to which data at a bit position decoded by the output of is supplied from a serial input terminal.

Operation According to the present invention, a serial data receiving device can be realized with an extremely simple configuration using the above-described configuration.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration diagram when a serial data receiving device according to an embodiment of the present invention is applied to a microprocessor. counter 1
00 and parallel data is sent to the data bus 200 of the microprocessor, and the data at the bit position decoded by the output of the counter 100 supplied via the counter bus 150 is supplied from the serial input terminal 20. The main part is constituted by the memory 300. Further, the output of each bit of the counter 100 is supplied to a D flip-flop 400,
The output signal of Frisobufronb 400 is passed to NO gate 41
0 and an interrupt output terminal 30 to serve as an interrupt request signal to the microprocessor. Further, the reset terminal 40 and the clear terminal 50 are connected to the non-launch type conversion capo-I- of the microprocessor and are supplied with a reset signal by rough 1 software, and the interrupt disable terminal 60 is connected to the latch type output port of the microprocessor. It is connected and used for interrupt control by software. In addition, the rung J and the processor connected to the access memory 300
A select signal for activating the parallel output section of the random access memory 300 is supplied to one terminal 70.

The operation of the receiving apparatus configured as described above will be explained based on the configuration diagram in FIG. 1 and the timing chart of the main parts shown in FIG. 2.

First, FIG. 2A shows the clock signal waveform supplied to the serial clock terminal 10, and FIGS.
, D show the output signal waveforms of each bit of the counter 100, and E, F, G, H, I, J in FIG.
, , and L all show output signal waveforms of the bit position switching decoder configured inside the random access memory 300, and FIG. 2M shows changes in serial data sent to the serial input terminal 20. This shows the situation.

In order to receive serial data using the device shown in FIG. Every time an edge arrives, the count value of the counter 100 becomes (111).

[11,0)...C001), C000
), and accordingly, the bit position of the random access memory 300 that receives data from the serial input terminal 20 is also switched, as shown in FIG. 2 EL. When the count value of the counter 100 reaches (000), the level of the D terminal of the D flip-flop 400 shifts to "1", and the output of the D flip-flop 400 occurs at the trailing edge of the clock signal supplied to the serial clock terminal IO. The level shifts to °1 and an interrupt request signal is sent to the interrupt output terminal 30. As a result, the microb starts an interrupt processing routine, and this interrupt processing routine causes the random access memory 300 to It is only necessary to read and count parallel data from the data bus 200 from the data bus 200.

In this way, the serial data receiving device shown in FIG. 1 can receive serial data in the same way as the conventional device; however, as can be seen from the configuration of FIG. While the serial data receiving device of the present invention requires both a shift register and a shift 1 counter, the serial data receiving device of the present invention does not require a shift register.
As a result, the circuit configuration has been simplified and the ratio of rung J and logic circuits has decreased, making it possible to
It is easy to layout when configuring an ff-tub LSI, and is suitable for LSI inspection in the production process.

Furthermore, since the received data is configured to be read directly from the serial input terminal 20 without going through a shift register, it is also possible to process a large amount of data at higher speed. That is, random access memory 300
Increase the address of and create a multi-stage buffer configuration.
Counter 1 that increases the number of bits to select that address
By using the upper bits of 00, more information can be handled at once, and advanced communication becomes possible.

Note that FIG. 3 is a circuit wiring diagram showing a specific example of the configuration of the random access memory 300, in which a unit memory cell is composed of an inverter 301 and a 3-state inverter 302, and an AND) gate 303 is a counter shown in FIG. It constitutes a part of a decoder that decodes a count value of 100 into a corresponding bit position. For example, when the level (SCK) of the serial clock terminal 10 in FIG. 1 is "0", the output level of the inverter 350 is “It becomes 1°,
If the output level of the AND gate 303 is also 1, the 3-state inverter 304 becomes active and the data (SDA) at the serial input terminal 20 is written into the memory cell. Further, when reading parallel data, the three-state inverter 305 becomes active.

Effects of the Invention As is clear from the above description, the serial data receiving device of the present invention includes a counter 100 to which a reception clock is supplied via the serial terminal 10, and a counter 100 in which parallel data is sent to the data bus 200 and 5. Memory means (in the embodiment, rung 1 and access memory 300 are used, but a lunch-type memory is also used) to be written to pins 1 to 300 positions decoded by the output of the counter. ), it is possible to realize a serial data receiving device with an extremely simple configuration, and by applying the present invention, a communication device that can perform advanced processing relatively easily. You can also get it, and it has great effects.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a serial data receiving device according to an embodiment of the present invention, FIG. 2 is a timing chart of the main parts of FIG. 1, and FIG. 3 is a circuit connection diagram showing an example of the configuration of a random access memory. It is. 20... Serial input terminal, 100...
···counter. 200...Data bus, 300...Random access memory.

Claims (2)

[Claims] (1) A serial data receiving device comprising a counter to which a reception clock is supplied, and a memory means to which parallel data is sent to a data bus and data at a bit position decoded by the output of the counter is supplied from a serial input terminal. . (2) A random access memory having a block select terminal and in which parallel data is sent to a data bus when the block select terminal is activated. Serial data receiving device described in Section 1.