JPS6366647A - Inhibiting circuit for replacement of cache memory - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] In a device in which a plurality of processors each have a dedicated cache memory and access the main memory, when another processor rewrites the main memory, the data in the cache memory is made to match. Therefore, when investigating a fault, etc., when another processor reads the cache memory and writes it to main memory, the cache memory is not rewritten. I,
Although data may be destroyed, a circuit was installed to prohibit this rewriting, making it easier to investigate the cause of the failure.

[Industrial application field]

The present invention relates to an information processing device in which a plurality of processors access main memory and communicate with each other via a common bus, and in particular, when each processor is independently equipped with a cache memory, data collection in the cache memory is performed. The present invention relates to a cache memory update prohibition circuit that prevents data update in a cache memory when performing a cache memory update.

Multiple processors with independent cache memory
2. Description of the Related Art Information processing apparatuses, such as office computers, that access main memory via a common bus to perform a given job are becoming more and more popular.

, a processor with a cache memory is
When reading data, send the address to access the main memory, and if there is a corresponding address in the cache memory,
Data is read from the cache memory, and if the data does not match, the cache memory takes in the data from the main memory, and then this data is successively retrieved and supplied to the processor.

The same goes for writing data to the main memory; data is once written to the cache memory, and then written to the main memory each time from the cache memory, or after being written in a certain amount of data.

Therefore, there is no guarantee that the data existing in the main memory always matches the data in each cache memory. Therefore, when a failure occurs in a certain processor and its cache memory, it is necessary to be able to transfer the data in the cache memory to the main memory without destroying the data.

[Conventional technology]

FIG. 2 is a block diagram illustrating a conventional technique.

A processor 3 equipped with a cache memory 2 sends an address to the cache memory 2 to exchange data. The cache memory 2 uses the address bus 10 and the data bus 1 to access and take in data that does not exist in the cache memory 2, and sends it to the processor 3.

Further, the cache memory 2 accesses the main memory 1 and writes the data written to the cache memory 2 each time or when the data is collected to a certain extent.

The processor 9 also stores necessary data from the main memory 1 in a cache memory (not shown), and rewrites the data in the raw memory@1 as necessary.

When the data in the main memory 1 is rewritten, the data copied from the main memory 1 to the cache memory of each processor 3 or processor 9 will be different, so The data rewriting operation is monitored, and when the data in the main memory 1 is rewritten, the data rewriting operation at the same address in the cache memory is performed.

The monitoring circuit 4 includes a write data register (WDR) 5, a write address register (WAR) 6, a tag memory 7,
The comparison circuit 8 monitors the data rewriting operation of the processor 9 in the main memory 1.

That is, the cache memory 2 is the main memory 1 in the tag memory 7.
It holds the address of the main memory 1 of the data copied from the write address register 6, and compares the address to access the main memory 1 of the processor 9 taken in and sent by the write address register 6 with the address held in the tag memory 7 by a comparison circuit 8. If they match, a write permission signal is sent to the cache memory 2 through step (3).

The cache memory 2 is the address sent by the write address register 6 via ■, and the address sent by the write data register 5 is
The data to be sent out is taken into the cache memory 2.

[Problem that the invention seeks to solve]

As described above, conventionally, when another processor 9 rewrites data in the main memory 1, the monitoring circuit 4 sends a rewrite permission signal for data at the same address in the cache memory 2. When the processor 9 reads the contents of the cache memory 2 and writes them to a certain area of the main memory 1 in order to detect a fault, etc., if the same address as the address of a certain area of the main memory 1 exists in the tag memory 7. , the monitoring circuit 4 stores in the cache memory 2,
The data at this address is permitted to be written into the cache memory 2 again.

FIG. 3 is a diagram illustrating an example of writing data in the cache memory 2 to the main memory 1.

It is assumed that the range shown by ■ in the main memory 1 has been copied to the cache memory 2. Since this copying is performed by the hardware of the cache memory 2, the processor 9
I don't know the extent of this copied ■.

Therefore, when the processor 9 reads data from the cache memory 2 and writes it to the main memory 1, it writes to a specific area ■ of the main memory l prepared in advance for failure detection, for example, but a part of this area ■ If the data in the cache memory 2 has been copied to the cache memory 2, the data in the area ■ of the cache memory 2 that is the same as the address in the area ■ will be rewritten.

Since the data written in this area (2) is the data in area (2) of the cache memory 2, there is a problem in that the data in area (2) of the cache memory 2 is destroyed.

[Means for solving problems]

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention.

In FIG. 1, a decoder 12, a flag register 13, a NOT circuit 14, and an AND circuit 15 are added to FIG.

The decoder 12 decodes the address of the flag register 13 sent by the processor 9 and enables the flag register 13. The flag register 13 is the processor 9
is set by the bit sent by , and sends “l” to the NOT circuit 14 .

Since the NOT circuit 14 sends “O”, the AND circuit 1
5 blocks the write permission signal sent by the monitoring circuit 4 via ``2'', and prohibits the cache memory 2 from taking in the write data sent from the monitoring circuit 4 via ``2''.

[Effect]

The flag register 13 has a NOT circuit 14 and an AND circuit 15.
At the same time, the write permission signal sent by the monitoring circuit 4 is blocked, and when the processor 9 writes data of the cache memo IJ 2 to the main memory 1, the cache memory 2 is prohibited from taking in the written data. The data in the memory 2 is not destroyed, making it easy to search for failures, etc., and by having the processor 9 take over the work that should be done by the processor 3, degenerate operation can be performed.

〔Example〕

In FIG. 1, the flag register 13 sends "0" to the NOT circuit 14 when it is not set. Therefore, the AND circuit 15 sends to the cache memory 2 the write permission signal that the monitoring circuit 4 sends via (2).

Therefore, the cache memory 2 can operate in the same manner as shown in FIG.

When an operator instructs the processor 9 to search for a fault, etc., the processor 9 sends the address of the flag register 13 to the address bus 10, and also sends a bit to set the flag register 13 to the data bus 1). The decoder 12 decodes the address of the flag register 13 inputted via the address address 10, and
3 is enabled.

Therefore, the flag register 13 is set and "1" is set to N.
In order to send to the OT circuit 14, the NOT circuit 14 is connected to the AN
Sends “0” to the D circuit 15. Therefore, AND circuit 1
5 blocks the write permission signal sent by the monitoring circuit 4 via 3, so that even if the processor 9 writes data to the main memory 1, the cache memory 2 does not take in the data.

Therefore, the processor 9 can write all the contents of the cache memory 2 to the main memory 1 without being destroyed.

〔Effect of the invention〕

As explained above, in the present invention, even if the contents of the cache memory are successively accessed by other processors and stored in the main memory, the data in the cache memory is not destroyed. In addition, by allowing a normal processor to perform processing for a faulty processor, degenerate operation is possible and a highly reliable device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a circuit showing an embodiment of the present invention, FIG. 2 is a block diagram explaining a conventional technique, and FIG. 3 is an example of writing data from cache memory to main memory. It is a diagram. In the figure, 1 is the main memory, 2 is the cache memory, 3.9 is the processor, 4 is the monitoring circuit, 5 is the write data register, 6 is the write address register, 7 is the tag memory, 8 is the comparison circuit, 10 is the address bus, 1) is a data bus, 12 is a decoder, 13 is a flag register, 14 is a NOT circuit,
15 is an AND circuit. The main memory is Gini 2 of Cashme 71 (two people also have a special combination of Ichiryu and Kogi; number 3)

Claims (1)

[Claims] A plurality of processors (3) each have a dedicated cache memory (2), and another processor (9) monitors rewriting of the main memory (1), and the cache memory (2) When data is rewritten in main memory (1) at the same address as the data copied to the cache memory (2),
In a device that accesses the main memory (1) via a common bus, the monitoring circuit (4) provides a rewrite permission signal to a processor (3), and instructs the cache memory (2) of a certain processor (3) to be prohibited from being rewritten. A flag register (13) whose flag is set by another processor (9), and a decoder (13) which decodes the address of the flag register (13) and enables the flag register (13).
12), and means (14) and (15) for blocking the rewrite permission signal sent by the monitoring circuit (4), and the other processor (9) sends out the address of the flag register (13), A cache memory update inhibition circuit characterized in that by setting a flag in the flag register (13), the rewriting permission signal sent from the monitoring circuit (4) included in a certain processor (3) is blocked.