JPS6365784A - Crt display device - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of the computer system by providing a 1st clock system synchronizing an external synchronizing signal with a computer synchronizing signal and a 2nd clock system controlling the access timing of a video RAM. CONSTITUTION:The 1st clock system 10 comprises the 1st clock frequency division circuit 12, a horizontal/vertical synchronizing signal generating circuit 14 and a synchronizing matching circuit 16. The 2nd clock system 20 comprises a, 2nd clock frequency division circuit 22, FFs 1, 2 and gate circuits G1, G2. Since the circuit 22 is in operation even with the synchronizing period between the computer synchronizing signal and the external synchronizing signal by the system 10, the CPU accesses the video RAM. The circuit 22 is stopped for the phase difference between the 1st and 2nd clocks to inhibit the access from the CPU. The phase difference is within one cycle of both the clocks, then the period inhibiting the access is slight.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a CRT display device, and particularly to a video RA display device.
The present invention relates to a CRT display device having a superimpose function for superimposing a computer image written in tα and a television broadcast image.

(Prior art) In this type of CRT display device, in order to prevent disturbances in the superimposed image, it is necessary to match the timing of the video signal from the television receiver and the video signal from the personal computer system. There is. To do this, the phase difference between the external synchronization signal from a television receiver, etc. and the computer synchronization signal is determined, and the clock oscillation circuit is stopped for the period of the difference, thereby synchronizing both synchronization signals. .

FIG. 3 is a block diagram schematically showing the structure of a synchronous coupling circuit of such a conventional CRT display device, and FIG. 4 is an operating waveform diagram thereof. The operation of the conventional example will be described below with reference to FIGS. 3 and 4.

The synchronization circuit 8 is supplied with an external horizontal synchronizing signal τ■ (see FIG. 4 (al)) and an external vertical synchronizing signal τ■ (see FIG. 4 (see dl)) from a television receiver or the like. The output of the clock frequency divider circuit 2 is given to the horizontal/vertical M signal generation circuit 4.The horizontal synchronization signal PH (see Fig. 4 fbl), which is a computer synchronization signal output from the horizontal/vertical synchronization signal generation circuit 4, and The vertical synchronization signal PV (see FIG. 4 (el)) is given to the synchronization circuit 8. As a result, the synchronization circuit 8 outputs the external synchronization signal πTr,
Phase difference signal ■lower y according to the phase difference between Tn and computer synchronization signals PH and PV (see Figure 4 (C1, ffl))
is output. Are these phase difference signals ITy the clock stop side of the clock frequency divider circuit 2? 11 terminal CT, the phase difference signal "TT is active ('
(LJ level), the output of the clock frequency divider circuit 2 is prohibited. In this way, the computer synchronization signals PH, PV
By adjusting the phase of the computer synchronizing signals PH, PV, the computer synchronizing signals PH, PV are synchronized with the external synchronizing signals τ■, τ■.

However, in the conventional example described above, the clock frequency dividing circuit 2
Since the timing of the video RAM access circuit 6 is controlled by the output of the phase difference signal yTY
If the output of the clock frequency divider circuit 2 is prohibited while the clock frequency dividing circuit 2 is active, access to the video RAM access circuit 6 is also prohibited during that period. If the CPLI (not shown) accesses the video RAM access circuit 6 and access is prohibited during the process, the CPU will have to wait for a very long time until the access is prohibited, and the computer system will be This causes problems such as a significant drop in processing efficiency.

(Object of the Invention) The present invention has been made in consideration of the above-mentioned circumstances, and is designed to minimize the access prohibition period of the video RAM when synchronizing the computer synchronization signal and the external 1tJl signal. , which aims to improve the processing efficiency of computer systems.

(Structure of the Invention) In order to achieve the above object, the present invention has the following structure.

That is, the present invention is a CRT display device that uses a superimposition method to superimpose a computer image stored in a video RAM and a television broadcast image, and a CRT display device that uses a superimposition method to superimpose a computer image stored in a video RAM and a television broadcast image. 1 clock system and a second clock system that controls access timing of the video RAM, and the first clock system includes a first clock system that divides a clock pulse and outputs a first clock.
a clock frequency divider circuit; a horizontal/vertical synchronization signal generation circuit that generates a computer synchronization signal based on the first clock; and a clock frequency dividing circuit that generates a computer synchronization signal based on the first clock; a synchronization circuit that synchronizes both synchronization signals by outputting a first phase difference signal and stopping a first clock frequency dividing circuit during an active period of the first phase difference signal, and synchronizing the two synchronization signals; The system includes: a second clock frequency divider circuit that divides the frequency of the clock pulse and outputs a second clock; and a logic circuit that is supplied with the second clock and the first phase difference signal, and the logic circuit includes: , after the active period of the first phase difference signal ends, a second phase difference signal corresponding to the phase difference between the first clock and the second clock is output, and during the active period of the second phase difference signal, the second phase difference signal is outputted. The second clock is synchronized with the first clock by stopping the clock frequency dividing circuit.

Next, the present invention having the above-described configuration will be explained in detail.

Even during the period when the computer synchronization signal and the external synchronization signal are being synchronized by the first clock system, the second clock frequency dividing circuit of the second clock system is operating.
The CPU can access video RAM. In addition, in order to synchronize the first clock and the second clock, between the phase difference between the first clock and the second clock, the second clock
The clock frequency divider circuit is stopped and access from CPtJ is prohibited. However, the phase difference between the first clock and the second clock is the same as the first clock. Since it is within one cycle of the second clock, the period during which access to the video RAM is prohibited is short.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing the configuration of a synchronization coupling circuit in a CRT display device according to an embodiment of the present invention.The feature of this embodiment is that in addition to the first clock system IO for synchronization signals, The second clock system 20 for RAM access control is provided.

The first clock system 10 is a clock system for synchronizing an external synchronization signal and a computer synchronization signal, and includes a first clock frequency dividing circuit 12 and a horizontal/vertical synchronization signal generation circuit 14.
and a synchronization circuit 16.

The second clock system 20 is a clock system provided for accessing a CRT control clock such as a video RAM (not shown) in synchronization with the second clock frequency dividing circuit 2.
2. Flip-flop FF1, FF2, gate circuit G1
．． It is composed of G2. Flip-flop FF1.
FF2, gate circuits Gl, and G2 correspond to the logic circuits described in the section of the configuration of the invention. The output of the second clock frequency divider circuit 22 is provided to a video RAM access circuit 30.

Next, the operation of the embodiment having the above-mentioned configuration will be explained with reference to FIG.

The external synchronization signal τ■ shown in Fig. 2 fbl and Fig. 2 (C
If there is a phase difference between the computer synchronization signal PH shown in FIG. While the signal "T7" is active, the first clock a, which is the output of the first clock frequency dividing circuit 12, stops (
FIG. 2 (see al) The phases of both synchronization signals are matched. The operation of the first clock system 10 is similar to the operation of the conventional example shown in FIG.

On the other hand, the second clock frequency dividing circuit 22 of the second clock system 20
The second clock e which is the output of is shown in FIG. During the period when the first phase difference signal n is active, the flip-flop FFI is freshened and its output f
is at the r I-I J level. Then, when the stop period of the first clock a ends, a trigger is applied at the next rising edge of the first clock a, and the output r becomes 'LJ level. The output f and the first phase difference signal MT1go are connected to the gate circuit G.
1, the output g remains at the "L" level for a period jII1 from when the stop of the first clock frequency divider circuit 12 is released until the next first clock a rises (see Fig. 2). g+).On the other hand, the flip-flop FF
2 is triggered at the rising edge of the second clock e and latches the state g ('LJ level) of the first phase difference signal MIXI. As a result, the output e of the flip-flop FF2 becomes as shown in FIG. 2 (hl). By applying this output e and the output g of the gate circuit CI to the gate circuit G2, the output of the gate circuit G2 The output is as shown in FIG.
2 control terminal CT. As a result, the second black,
The frequency dividing circuit 22 stops while the phase difference signal yT7 is active. Then, the second clock frequency dividing circuit 2
By canceling the stop of 2 in synchronization with the first clock a, the first clock a and the second clock e are synchronized. In FIG. 2, a period T1 indicates a period during which the first clock frequency dividing circuit 12 is stopped, and a period T2 indicates a period during which the second clock frequency dividing circuit 22 is stopped. During the T2 period, the CPU is prohibited from accessing the video RAM.

In this way, the first clock system 10 and the second clock system 2
The reason for synchronizing the clock with 0 is as follows. The first clock a is used not only to obtain a computer synchronization signal, but also to specify the refresh address of the video RAM. During the period when the first clock a is at the 'HJ level, the contents of the video RAM are It is now time for it to be read and displayed. On the other hand, since access from the CPU is prohibited during the display period, the CPU
is accessed while the output a is at the 'LJ level. Therefore, the LJ level period of the second clock e controlling the video RAM access circuit 30 (
video RAM access period) and the first clock a'
If there is a time lag between the LJ level period and the LJ level period, the video RAM will be accessed during the display period, which is inconvenient. Therefore, in order to eliminate such a time lag between the two clocks, the first clock a and the second clock e are synchronized.

(Effects of the Invention) As is clear from the above description, the CRT display device according to the present invention has a first clock system that synchronizes an external synchronization signal and a computer synchronization signal, and a first clock system that controls access timing of the video RAM. Equipped with 2 clock system,
Even when the first clock is not output for synchronizing the synchronization signals, the video RAM can be accessed by the second clock. During the period when the clock frequency dividing circuit is stopped, the first. ] cycle of the second clock.

Therefore, compared to the conventional example in which access to the video RAM is prohibited during the period of synchronization between the computer synchronization signal and the external synchronization signal, the video RAM of the device of the present invention is
The access prohibition period is short, and the processing efficiency of the CPU can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a synchronous coupling circuit in a CRT display device according to an embodiment of the present invention, FIG. 2 is an operating waveform diagram of the embodiment shown in FIG. 1, and FIG. 3 is a block diagram of a conventional example. FIG. 4 is an operational waveform diagram of the conventional example shown in FIG. DESCRIPTION OF SYMBOLS 10... First clock system, 12... First clock frequency dividing circuit, 14... Horizontal/vertical equal 1 signal generation circuit, 1
6... Synchronization circuit, 20... Second clock system,
22...Second clock frequency divider circuit, FFI, FF2...
・Flimp flop, C1, G2...gate circuit, 3
0...Video RAM access circuit. Figure 3 (K-if block 4)
Figure (Operation waveform diagram of conventional example) (c) Like (f) Satsuma α

Claims (1)

[Scope of Claims] A CRT display device that uses a superimposition method to superimpose a computer image stored in a video RAM and a television broadcast image, the CRT display device being a CRT display device that uses a superimposition method to superimpose a computer image stored in a video RAM and a television broadcast image, and a CRT display device that synchronizes an external synchronization signal and a computer synchronization signal. 1 clock system and a second clock system that controls access timing of the video RAM, and the first clock system includes a first clock system that divides a clock pulse and outputs a first clock.
a clock frequency divider circuit; a horizontal/vertical synchronization signal generation circuit that generates the computer synchronization signal based on the first clock; and a clock frequency dividing circuit that generates the computer synchronization signal based on the first clock; outputting a corresponding first phase difference signal; during the active period of the first phase difference signal;
a synchronization circuit that synchronizes both synchronization signals by stopping the first clock frequency dividing circuit, and the second clock system includes a second clock that divides the frequency of the clock pulse and outputs a second clock. a frequency divider circuit; and a logic circuit that is provided with the second clock and the first phase difference signal, and the logic circuit receives the first clock and the second phase difference signal after the active period of the first phase difference signal ends. The second clock is synchronized with the first clock by outputting a second phase difference signal corresponding to the phase difference with the clock and stopping the second clock frequency dividing circuit during the active period of the second phase difference signal. A CRT display device characterized by: