JPS6364439A - Common memory management system - Google Patents

Abstract

PURPOSE:To contrive to improve the utilizing efficiency of a common memory in a packet switch by controlling number of times of write/read to/from the common memory in response to the speed of an input/output line through the use of a control memory. CONSTITUTION:In giving input information to an input line control section 1-i, the necessity of storage to a common memory field 3-j is discriminated and a common memory field number is written and displayed in a memory 4 by number of times s/v(where S is a cyclic speed to the common memory and (v) is the speed through the input line 11-i) only when the storage is allowed. Addresses, from O to P of the memory 4 are designated in order at the speed (s) and the information is written, in the memory field 3-j. After all the input information is written, the common memory field number is written while being read and displayed from the memory at an equal interval by number of times of s/v(where (v) is the speed in the output line 12-k and (s) is the cyclic speed of the memory 4). Then addresses, from O to P of the memory 4 are designated in order at the speed (s) and the data is sent to the line 12-k from the memory field 3-j.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a common memory management system, and particularly to a common memory management system in a high-speed packet switch that exchanges packet information at high speed.

[Conventional technology]

Conventionally, in a packet switch that exchanges data using a common memory for multiple input lines and output lines with different speeds, the maximum speed of the input line and output line is multiplied by the number of input/output lines. It was necessary to access common memory, and high-speed common memory was required.

Therefore, a high-speed common memory is required even for low-speed lines.

[Problem that the invention seeks to solve]

1. In the prior art, a high-speed common memory is required even for low-speed lines, so there is a problem that the number of lines that can be accommodated is limited.

The main purpose of the present invention is to solve the conventional problems such as 2 and to access the common memory at a speed corresponding to the line speed
The object of the present invention is to create a common management system that can effectively use Jt memory across many lines.

[Means for solving problems]

In order to solve the above problems, the present invention accumulates input information from a plurality of input lines with different speeds in a common memory, and based on the address information included in the input information, a plurality of corresponding In a packet switch that outputs information to output lines with different speeds, a control memory is provided that instructs writing from the input line to the common memory and reading from the common memory to the output line during a fixed cycle, and the control memory allows the input line to Another feature is that the number of times of writing to and reading from the common memory is controlled according to the speed of the outgoing line.

[Effect]

By controlling the access order to the common memory according to the input/output line speed using a control memory that controls access to the common memory for multiple input/output lines with different speeds, the usage efficiency of the common memory in the packet switch is improved. Towards.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a packet switch showing an embodiment of the present invention.

In FIG. 1, 11-1 to 11-j are a plurality of input lines (i=] to n) with different speeds, 12-1 to 1.2-
has a plurality of output lines (k-1 to m) with different speeds, 1-
1 to 1-1 are input/output line control units (i-1 to n
), 2-1 to 2-k are output line control units (k-1 to m) that control the output of input information stored in the memory, and 3-1
~3-1j is a common memory surface (j-1 to Q) that stores information from the input line 1l-i (j = 1 to n), 4 is a common memory surface 3-j (, i = 1 to Q) This is a control memory that controls the order of access to the memory.

FIG. 2 is a detailed view of the control memory 4 in FIG. 1, and shows line number 4], write/read display 42 . A common memory surface number 43 is written. To operate this, when input information is input to the input line controller 1-i (j=] to n), it is determined whether or not this information should be stored in the common memory surface 3-j (j=1 to Ω). It is determined that the information should be input, and the input line 1l-i
(j = 1 to n) speed ■, control memory 4 at equal intervals s / v times for the circulation speed S of the control memory 4
Write and display the common memory surface number. Speed S
Specify the addresses of the control memory 4 in order from 0 to P, and transfer the input information from the input line 1l-j (i = I to n) to the specified common memory surface 3-j (j = 1 to Q). Write.

Once all the input information has been written, the output line 12-k (k = 1 to m) line speed V to be output and the circulation speed S of the control memory 4 are equally spaced by the number of s/v times. Read display and write the common memory surface number to the control memory 4. Specify the addresses of the control memory 4 in order from O to P at the speed S, and write the common memory surface 3-j(,i=]~Q
) is extracted from the output line 12-k (k=1
~m) outputs the data. That is, the counter 20 and the clock 21 sequentially designate addresses O to P in the control memory 4, and read 1 (Jl, designation 42. Mesensu surface number 42). According to this, in the case of writing, the input line 1l-4 (i=
] to n), the common memory plane 3-.
1 (j=l~Q). In the case of reading, common memory plane 3-j (j=l
~Q) and sends it to the specified output line 12-k.
(k = 1 to m). The designation of the input/output line is controlled from the control memory 4 by the number of accesses corresponding to the clock speed while changing from the address O to the address P of the control memory 4.

With this structure, memory access can be performed in accordance with the input/output line speed. In addition, the control memory 4
By simply changing the contents of , it is possible to easily accommodate a wide variety of input/output speed combinations.

〔Effect of the invention〕

As explained above, according to the present invention, access to the common memory can be optimally allocated according to the speed of the input/output line control unit, so that memory access can be performed effectively for combinations of different input/output line speeds. It has the advantage of being able to

[Brief explanation of drawings]

FIG. 1 is a block diagram of a packet switch showing an embodiment of the present invention, and FIG. 2 is a detailed block diagram of the control memory shown in FIG. 1=i-input line control ll1 (i=1~n), 2-
To: Output line control unit (k=1 to m), 11-i: Input line (j-1 to n), To 1.2-: Output line (k=1 to
rn), 3-'': common memory surface (j=1 to Ω), 4: control memory, 41: line number, 42: write/read display, 43: common memory surface number. Figure 1

Claims (1)

[Claims] (1) Input information from multiple input lines with different speeds is accumulated in a common memory, and information is output from the common memory to multiple corresponding output lines with different speeds based on the address information included in the input information. In a packet switch that
A control memory is provided that instructs writing from the input line to the common memory and reading from the common memory to the output line during a fixed cycle, and the control memory allows writing to the common memory and instructing the reading from the common memory to the output line in accordance with the speeds of the input line and the output line. A common memory management method characterized by controlling the number of reads from a common memory.