JPS6360578B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmit inhibit circuit, and more particularly to a transmit inhibit circuit that inhibits signal transmission if a logic gate is not connected to a gate pulse source when it is connected to a power source and is in an operative state.

Electronic devices such as communication devices and computers are
It is usually constructed by installing a plug-in type unit inside the rack. Interconnection between each unit is accomplished through wiring within the rack via connectors provided on each unit. When such electronic equipment is often installed with a new unit while it is powered on and in operation, and when a new unit is installed, protective measures are required to ensure that the operation of the equipment is not adversely affected. There are many.

1 and 2 are a block diagram and a time chart showing an example of an object to which the present invention is applied.
Figure 1 shows the main parts of a pulse code modulation (PCM) terminal equipment. This device performs pulse code modulation on input signals 1 to m of m channels (m is a predetermined positive integer), respectively, and then time-division multiplexes and transmits the signals. The conversion unit 1-1 includes a conversion circuit 13-1 that pulse code modulates the input signal 1, and a NAND gate 1 that sends a pulse code modulation signal (PCM signal) to the bus line in response to the gate pulse 1.
4. Conversion unit 1-2 or 1
-m also has the same configuration as the above conversion unit 1-1. Each conversion unit 1-1 to 1-m is a plug-in type that can be attached to and removed from the rack, and the connector for mutual connection between the conversion unit 1-1 and the outside includes a terminal 10-1 for receiving and connecting input signal 1, a gate It includes a terminal 11-1 for receiving and connecting the pulse 1 and a terminal 12-1 for sending the PCM signal to the bus line (other than the conversion unit 1-1 are not shown). For example, when the conversion unit 1-1 is mounted on a rack and is in operation, the conversion circuit 13-1 receives the input signal 1 sent through the terminal 10-1, modulates the input signal 1, and modulates the input signal 1. Send the unipolar PCM signal to the NAND gate 14-1. The NAND gate 14-1 is a transistor-transistor logic (TTL) circuit composed of bipolar elements, and its output circuit is an open collector type, and the output end is connected to the bus line via the terminal 12-1. Ori,
Furthermore, the DC voltage V _D is applied through the pull-up resistor _R1 .
is applied, and a so-called wired logic connection is performed. The signal sent out by the conversion unit 1-1 is
Only when the gate pulse 1 is a high level H voltage and the PCM signal is an H voltage combination, it becomes a low level L voltage, and in other combinations does it become an H voltage.
Since gate pulses 1 to m are pulses indicating the timing (time slot) of sequential transmission of conversion units 1-1 to 1-m, respectively, on the bus line, the PCM signal of the conversion unit whose transmission timing is instructed is set to H voltage. Only when the voltage becomes L, the voltage of each conversion unit 1-1 to 1-m
A multiplexed signal is obtained by time-division multiplexing the PCM signals. This multiplexed signal is sent to the multiplexing circuit 2,
It is sent out after undergoing predetermined signal processing including unipolar/bipolar conversion.

By sending the multiplexed signal unified via the bus line to the multiplexing circuit 2, each conversion unit 1
Compared to the case where the signals sent by -1 to 1-m are not combined and sent individually to the multiplexing circuit 2, the number of input lines to the multiplexing circuit 2 can be reduced. The device can be miniaturized without requiring extra space for the connection means. However, in such equipment, it is often necessary to install a new conversion unit to expand the communication path without interrupting the operating state, and when installing a conversion unit, it is necessary to ensure that the existing communication path is not adversely affected. To do so, additional protection measures are required. FIG. 2 exemplifies a case where a conversion unit 1-m is newly installed to add a communication path while the apparatus shown in FIG. 1 is operating without the conversion unit 1-m installed. Conversion unit 1-
When the unit is installed, the input signal, gate pulse, bus wire, as well as the power supply and ground are connected to the circuit inside the unit via each terminal of the connector, but there are some differences depending on the insertion angle when the unit is installed, the dimensions of each terminal of the connector, etc. Due to some variation, the probability that all connections will complete at the same time is extremely low. A particular problem that must be considered in terms of the effect on the existing communication path is when the power supply and ground connections precede the gate pulse connections. In Figure 2,
When the unit is installed, the power supply and ground connections are first completed at time t ₁ , and when the gate pulse m connection is completed at time t ₂ , the existing multiplexed signal from time t ₁ to time t ₂ is connected. A signal sent out by the newly installed conversion unit 1-m is superimposed on the time slot of the communication path. In other words, the conversion circuit and NAND gate of conversion units 1-m
From time t ₁ to time t ₂ , the gate pulse m operates without being connected. During this time, the conversion circuit generates a PCM signal and sends it to one input of the NAND gate. At this time, the other input terminal of the NAND gate is in an open state with zero current, so as shown by the dotted line in FIG. 2, the state is equivalent to the state where the gate input m of that input terminal becomes an H voltage. Therefore, from time _t1 to time _t2 , conversion unit 1-m
The PCM signal generated by the conversion circuit continues to be sent to the bus line. During this time, the time slot of the existing communication path of the multiplexed signal is
PCM signal (S ₁ or S ₂ ) and conversion unit 1-
A signal (S ₁ + _{N n or} S ₂ +N _n ) superimposed with the PCM signal N n sent from m is sent to the multiplexer 2 . Such signal superposition causes noise in the received sound when the input signal of the existing communication channel is a voice signal, and causes malfunction of the exchange system when it is a supervisory signal.
Alternatively, in the case of data signals, code errors may occur, adversely affecting existing communication channels.

In this way, if the unit is a plug-in type equipped with a logic gate that sends out a signal in the time slot indicated by the gate pulse, and if the gate pulse is supplied from outside the unit, the , a transmission inhibiting means is required to prevent the logic gate from transmitting a signal between the time when the power supply and ground are connected to the circuit including the logic gate and the time when the gate pulse is connected to the logic gate.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a means for meeting the above-mentioned needs, namely, a transmission inhibit circuit which inhibits signal transmission unless a logic gate is connected to a gate pulse supply source when the logic gate is powered on and in operation. .

The circuit of the present invention includes a plurality of NAND gates that output multiplexed signals in response to a received signal applied to a first input terminal and a gate pulse applied to a second input terminal indicating transmission timing, respectively; The voltage at the second input terminal is predetermined to be maintained at a value that prohibits the NAND gate from outputting the multiplexed signal when the NAND gate receives power supply and is not connected to the source of the gate pulse. The device includes a plurality of resistors each having a resistance value and connected to the second input terminal, and a transmitting means for multiplexing the multiplexed signal and transmitting the multiplexed signal to one bus line.

Next, the present invention will be explained in detail with reference to the drawings.

3 and 4 are a block diagram and a time chart, respectively, showing one embodiment of the present invention. The circuit in FIG. 3 is similar to the NAND gates 14-1 to 14-m of the circuit in FIG.
One end of the resistor R _L is connected to the terminal for applying the gate pulse among each pair of input terminals of the gate 14-1 (other than gate 14-1, illustrations are omitted), and each resistor R _L
The other end is grounded. NAND gate 1
4-1 to 14-m are logic gates for sending out signals from the conversion units 1-1 to 1-m in FIG. 1, respectively, and the respective conversion circuits 13--
PCM signals sent from 1 to 13-m,
At the time slots indicated by gate inputs 1 to m, they are sent to the bus line via terminals 12-1 to 12-m, respectively. Each gate input 1 to m
is from an external gate pulse source to terminal 11-1.
11-m to both ends of the resistor R _L , respectively. Resistor R _L is used to prevent the terminals of the connector that connects the circuit inside the unit and the circuit outside the unit from being connected at the same time when the unit is installed in an operating device, and the power and ground connections are gated. It is provided to hold the gate input at the L voltage when it precedes the connection of the pulse. For example, when the conversion unit 1-m shown in Fig. 1 is installed in an operating device, the power supply and ground connections are completed at time _t1 as shown in Fig. 4, and then the gate pulse m is connected at time _t2 . Suppose it is completed. From time t ₁ to time t ₂ , the terminal 11-m is in an open state with no gate pulse m connected, and no current flows through the terminal 11-m, but the gate transistor in the NAND gate 14-m Current flows from through resistor R _L. The resistance value R _L is set so that the voltage across the resistor R L at this time is lower than the threshold voltage for identifying the high or low voltage level of the gate input m _.
By selecting the value of in advance, as shown by the dotted line in Figure ₄ , _the
This is equivalent to a state in which the gate input m of the NAND gate 14-m becomes an L voltage. Therefore, the NAND gate 14-m prohibits signal transmission from time _t1 to time _t2 , regardless of the presence or absence of the PCM signal sent from the conversion circuit 13-m.

In this way, each NAND gate 14-1 or 1
By connecting a resistor R _L to each of the gate pulse input terminals of 4-m, the gate pulse input terminal from the power supply and ground connection to the gate pulse connection is maintained in a state equivalent to when the L voltage is applied. During this time, signal transmission can be prohibited. Therefore, the multiplexed signals on the bus line are signals S1 to _Sn , which are time-division multiplexed PCM signals corresponding to the time slots indicated by gate pulses ₁ to m, and are different from conventional signals when the unit is installed. No overlap occurs. That is, in this embodiment, the transmission inhibit circuit is realized by simply connecting one resistor to each logic gate, and the circuit can be manufactured compactly and economically.

In this embodiment, the NAND gates 14-1 to 14-m are TTL circuits, but
It is clear that the same effect can be obtained with the same connection in the case of a MOS type logic circuit.

As is clear from the above description, the present invention includes a transmission prohibition circuit that prohibits the logic gate from transmitting signals when the logic gate is connected to a power source and is in an operating state but is not connected to a gate pulse supply source. In particular, when applied to a device that time-division multiplexes signals of a plurality of channels, the number of input lines of the multiplexed signal processing section can be reduced and the device can be miniaturized, which is a remarkable effect.

[Brief explanation of drawings]

1 and 2 are a block diagram and a time chart, respectively, for illustrating an object to which the present invention is applied, and FIGS. 3 and 4 are a block diagram and a time chart, respectively, for illustrating an embodiment of the present invention. 1-1 to 1-m...conversion unit, 13-1...conversion circuit, 14-1 to 14-m...NAND gate,
11-1 to 11-m, 12-1 to 12-m...terminal, 2...multiplex circuit, _R1 , R _L ...resistance.

Claims (1)

[Claims] 1 A plurality of NAND gates each transmitting a signal to be multiplexed in response to a reception signal applied to a first input terminal and a gate pulse applied to a second input terminal indicating transmission timing; the gate pulse having a predetermined resistance value such that the voltage at the second input terminal is maintained at a value that inhibits the output of the multiplexed signal of the NAND gate when the gate pulse is not connected to the source of the gate pulse; A transmission inhibiting circuit comprising: a plurality of resistors respectively connected to second input terminals; and transmitting means for multiplexing the multiplexed signals and transmitting the multiplexed signals to a single bus line.