JPS6355799A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To effectively allow device discrimination codes to work even when repairing is executed by writing the data of a device discrimination code in two or more column repair lines beforehand. CONSTITUTION:A device discrimination code storage element 2a is connected to a transistor Tr 1 for the device discrimination code connected to the bit lines B1-Bm of a memory cell array 2. A device discrimination code storage element for repair 20a in which the codes of the same content with the device discrimination code is provided in a redundant circuit 20. When the bit line B1 is defective, the circuit 20 is made to select a column repair line BS1 instead of the line B1 so far selected. As the data of the same device code with a Tr 3 are written in a Tr 5, the data of accurate device code are read out. In a case where the line Bm is defective, by selecting a column repair line BS2 similarly, an accurate maker code is read out since the data of the same maker code with a Tr 4 are written beforehand in a Tr 6.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device equipped with a redundant circuit.
In particular, it relates to a semiconductor memory device having a device identification code.

[Conventional technology]

What is the device identification code? Manufacturer of semiconductor memory device, 2 types of pin arrangement, capacity, write voltage (for EF'R0M)
It is a code written in advance in the storage device so that it can be used without any problem even if the user has no knowledge about the semiconductor storage device.This code is used, for example, as follows. . That is, if the semiconductor memory device having a device identification code is an EFROM, R
When writing, the OM writer reads the device identification code from the EFROM and applies the appropriate write voltage for the type of 8G ROM to the required pins without error. To stably and reliably write information to a ROM even when there is no knowledge.

Figure 2 shows a conventional EP RO with a device identification code.
M (Erasable Programmable
FIG. 2 is a circuit diagram showing a memory structure (Read Only Memory). In the figure, 1 is a transistor for a device identification code, 2 is a memory cell array main body having a memory cell transistor 2a, 20 is a redundant circuit having a repair transistor 20a, 3.4 is a transistor in which a device code is written, and a manufacturer code. (device identification code storage element)
, Bl+ Bz, Bi, . . . , B are bit lines, W l, W t, W :l, . . . 4. W and l represent word lines, and BS3 and BS4 represent column repair lines.

Note that a mechanism for selecting a predetermined address based on address input from the outside and a mechanism for replacing a defective bit in the memory cell array body with a repair transistor among the redundant circuits are not shown.

Next, the operation will be explained. In FIG. 2, when reading a device code, the data of the device code can be read by selecting WS of the word lines and selecting B1 of the bit lines. Also, when reading the manufacturer code, WS of the word line
By selecting , and selecting 81 of the bit lines, the manufacturer code data can be read.

If there is a defective bit in the main body of the memory cell array, the redundancy function will remove the defective bit line from column repair line BS3. Alternatively, the column repair line BS3.BS4 is repaired, and after the repair, the column repair line BS3. or BS4
is selected.

[Problem that the invention seeks to solve]

Conventional EFROMs with device identification codes are configured as described above, so if a defect occurs in the bit line to which device identification code data is written, repair can be performed to replace the defective bit line. is accessed, so there is a problem that the data of the device identification code cannot be read at all.

This invention was made to solve the above-mentioned problems.If a defect occurs in the bit line to which the device identification code data is written, the device identification code data cannot be read even after repair. The purpose of this invention is to obtain a semiconductor memory device that can perform the following steps.

[Means for solving problems]

The semiconductor memory device according to the present invention is provided with two or more column repairs in advance, and device identification code data (device code, manufacturer code) is assigned to each column repair, and if the bit line to which the device code data is written is defective, If the bit line to which manufacturer code data is written is defective, repair can be performed to the column repair line to which the manufacturer code is written.

[Effect]

In this invention, since two or more column repairs are provided in advance and device identification code data (device code, manufacturer code) is assigned to each column repair, the bit line to which device identification code data is written becomes defective. In this case, by replacing the bit line with a column repair line in which device identification code data is written, i.e., if the bit line in which device code data is written is defective, repair it with the column repair line in which device code is written. If the bit line to which the manufacturer code data is written is defective, the device identification code data can be effectively used by repairing it to the column repair line to which the manufacturer code is written.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a semiconductor memory device according to an embodiment of the present invention, and in the figure, the same reference numerals as in FIG. 2 indicate the same parts. 5.
6 is a transistor for repairing the device code, a transistor for repairing the manufacturer code (repair device identification code storage element), BS1 is a column repair line in which device code data is written, and BS2 is a column repair line in which manufacturer code data is written. This is a column repair line.

In FIG. 1, when the bit line B1 to which device code data is written is defective, the redundancy circuit selects the column repair line BSI instead of the bit line B1 that had been selected. Since data of the same device code as transistor 3 is written in the transistor 5 in advance, accurate device code data can be read out.Also, if the bit line Bm where the manufacturer code data is written is defective, the bit line Bm where the manufacturer code data is written is defective. Line B
Instead of selecting m, column repair line BS2 may be selected. Since data of the same manufacturer code as the transistor 4 is written in advance in the transistor 6, an accurate manufacturer code can be read out.

In the above embodiment, there is one column repair line each for the device cord and the manufacturer cord, but there is no problem even if the number of column repair lines is greater than that. Moreover, in the above embodiment, EP
Although we have explained the case of ROM, EPROMSSRA
Needless to say, the present invention can be applied to all types of semiconductor memory devices such as M-DRAM.

Furthermore, although only the manufacturer code and device code are shown as device identification codes, it goes without saying that other conceivable codes may be used.

〔Effect of the invention〕

As described above, according to the semiconductor memory device according to the present invention,
Since the device identification code data is configured to be written in advance to two or more column repair lines, even if there is a defect in the bit line to which the device identification code data has been written, it can be read by column repair.
This has the effect that the device identification code can be used effectively even after repair.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the memory structure of an EPROM according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing the memory structure of a conventional EPROM. In the figure, 1 is a device identification code transistor, 2 is a memory cell array body, 2a is a memory cell transistor, 20 is a redundant circuit, 20a is a repair transistor, 3.4 is a transistor in which device code data is written, Transistor (device identification code storage element) in which manufacturer code data is written, 5
．． 6 is a transistor for repairing the device code, a transistor for repairing the manufacturer code (repair device identification code storage element), Wt, Wt, Ws, . . . Wa is a word line, WS is a word line for device identification code, B l, B z, B ! ,...+BI
I is a tote line, BSI is a column repair line where device code data is written, BS2 is a column repair line where manufacturer code data is written, B
S3. BS4 indicates a column repair line. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a semiconductor memory device equipped with a redundant circuit, a device identification code storage element connected to a bit line of a memory cell array main body and written with a device identification code; and a device identification code storage element connected to a bit line of the redundant circuit and written with a device identification code; 1. A semiconductor memory device comprising: a repair device identification code storage element in which a code with the same content is written.