JPS6351551B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor MOS capacitance that can improve lead bonding strength.

Generally, as shown in FIG. 1, a semiconductor MOS capacitor 1 has two transistor chips in the same package, such as a high-frequency, high-output transistor.
It incorporates a capacitor chip with a MOS structure and is used for internal matching. On the other hand, in order to achieve higher output and higher efficiency in the transistor, internal matching is of course provided,
Since the transistor chip 2, base, and emitter each have multiple lead bonding pads, in order to reduce stray impedance, the distance between the lead wires from the pads to the lead terminals on the exterior should be kept as short as possible, and each lead wire should be kept as short as possible. The lengths must be the same length. For this reason, an emitter lead bonding relay terminal is provided within the semiconductor MOS capacitance. The metallization of this emitter lead bonding relay terminal has a structure in which it makes ohmic contact with the silicon semiconductor substrate and is connected to a common ground terminal. In Fig. 1, 3 is the base lead, 4 is the collector lead, and 5 is the base lead.
is an emitter lead (common ground terminal), and 6 is an Au wire.

As the cross section of the conventional semiconductor MOS capacitor is shown in FIG. 2, an oxide film 8 is formed on a silicon semiconductor substrate 7, and after forming a desired pattern, electrodes 9 and 10 are provided, and a MOS capacitance portion 11 and an emitter are formed. A ivy lead bonding relay terminal portion 12 is formed. At this time, in order to make ohmic contact with the emitter lead bonding relay terminal portion 12 on the silicon semiconductor substrate 7, a platinum silicide layer is formed on the entire surface, and a gold layer is formed through a barrier metal layer. . In addition, in FIG. 2, 13 is a back electrode connected to an emitter lead on the exterior.

However, in the conventional semiconductor MOS capacitance, there is a problem that the capacitor peels off from the interface between the silicon and the electrode layer during lead bonding in the assembly process. This has the disadvantage that the area of the platinum silicide layer is large and the crystal structure is in a state where it is easy to cleave, and automatic lead bonding methods that use ultrasonic waves are even more problematic.

Therefore, an object of the present invention is to provide a semiconductor MOS which increases the adhesive strength with a silicon semiconductor substrate and prevents electrode peeling during lead bonding.
It provides capacitance.

In order to achieve such an object, the present invention includes an oxide film formed in a desired pattern on the surface of a silicon semiconductor substrate, a MOS capacitance portion formed by metallization on one oxide film, and an oxide film formed on another oxide film. An emitter lead bonding relay terminal portion formed so that a portion of the formed metallization makes electrical contact with the silicon semiconductor substrate is provided in the same chip, and will be described in detail below using examples.

FIG. 3 is a sectional view showing an embodiment of the semiconductor MOS capacitance according to the present invention, and FIG.
-FIG. 4D are process-by-step cross-sectional views showing the manufacturing process. In the figure, reference numeral 14 indicates an electrode 1 between the silicon semiconductor substrate 7 and the emitter lead bonding portion 12.
This is an oxide film provided between a part of 0 and a part of 0.

Next, the manufacturing process of the semiconductor MOS capacitance having the above structure will be explained with reference to FIGS. 4A to 4D. First, as shown in Figure 4A,
An oxide film 15 is formed on the surface of the N-type silicon semiconductor substrate 7.
form. Next, as shown in FIG. 4B, the unnecessary oxide film 15 other than the MOS capacitance part 11 and the emitter lead bonding part 12 is removed by a well-known photolithography technique, and a desired oxide film 8 is formed.
and 14. Next, as shown in FIG. 4C, in order to establish ohmic contact between the electrode 10 of the emitter lead bonding part 12 and the silicon semiconductor substrate 7, platinum is deposited by vapor deposition or sputtering to form a silicide layer. , a gold layer is formed on the entire surface through a barrier metal layer, and predetermined electrodes 9 are formed using photolithography.
and form 10. Next, as shown in FIG. 4D, after wrapping the back surface of the silicon semiconductor substrate 7 to a predetermined thickness, a back electrode 13 is formed to complete the process.

As mentioned above, the method of forming an electrode directly under the bonding pad through an oxide film is not suitable for semiconductors.
Of course, it can be widely applied not only to MOS capacitance but also to other semiconductor devices.

As described in detail above, according to the semiconductor MOS capacitance according to the present invention, a silicon oxide film is left directly under the bonding pad portion of the emitter lead bonding relay terminal to improve the lead bonding strength. ,
It has the effect of eliminating lead bonding defects, which are a fatal defect in products, and is particularly suitable for use in reducing stray impedance caused by lead bonding of high frequency, high output transistors.

[Brief explanation of the drawing]

Fig. 1 is a schematic perspective view showing the relationship between a transistor chip that achieves internal matching and semiconductor MOS capacitance, Fig. 2 is a sectional view showing a conventional semiconductor MOS capacitance, and Fig. 3 is a semiconductor according to the present invention.
A cross-sectional view showing an example of MOS capacitance,
4A to 4D are semiconductor MOS shown in FIG. 3.
FIG. 3 is a step-by-step sectional view showing a capacitance manufacturing process. 1...Semiconductor MOS capacitance, 2...Transistor chip, 3...Base lead, 4...
Collector lead, 5... Emitsuta lead, 6...
Au wire, 7... Silicon semiconductor substrate, 8... Oxide film, 9 and 10... Electrode, 11... MOS capacitance section, 12... Emitter lead bonding relay terminal, 13... Back electrode, 14 and 1
5...Oxide film. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. An oxide film formed in a desired pattern on the surface of a silicon semiconductor substrate, a MOS capacitance portion formed by metallization on this one oxide film, and a part of metallization formed on another oxide film are formed on the silicon semiconductor substrate. A semiconductor MOS capacitor characterized in that an emitter lead bonding relay terminal portion formed to make electrical ohmic contact is provided within the same chip.