JPS6351383B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to an improvement in a semiconductor device having a fuse-type PROM element.

In recent years, attempts have been made to provide a PROM element in a MOS type LSI to realize a programming means for a MOS type circuit, and a redundancy circuit for relieving defects using the PROM circuit or programming.

By the way, fuse elements have conventionally been programmed into (a) current blowing type, (b) laser cutting type, and (c)
A current (laser) short circuit type, in which both ends are shorted by current or laser, is known. However, MOS type using these fuse elements
LSI had the following two main drawbacks.

First, since fuse elements are often blown out, disconnected, or short-circuited while the MOS LSI is powered on, fuse elements 3 are provided on a semiconductor substrate 1 with a field insulating film 2 interposed therebetween as shown in FIG. Due to the heat generated during programming, one carrier of the electron e and hole h pair generated in the semiconductor substrate 1 near the fuse element 3 diffuses into the MOS type provided on the substrate near the fuse element 3. It is to interfere with the operation of the circuit. In particular, in the case of current type fuse elements, if a MOS type drive circuit is used for programming, programming may not be performed reliably, so it is necessary to install the MOS type drive circuit at a sufficient distance from the fuse element. It becomes an obstacle to development.

Second, due to the high temperature heat generated when the fuse element is blown or short-circuited, a large amount of contaminant ions are generated on or in the insulating film 2 near the fuse element 3, as shown in FIG. That's true. Known examples of these contaminating ions include alkali ions such as sodium ions and potassium ions, and metal ions such as copper ions. These contaminant ions move in or on the insulating film near the fuse element, forming a parasitic MOS transistor between the source and drain of the MOS transistor or between the diffusion wiring layer, and significantly reducing the reliability of the MOS type LSI. For this reason, it is necessary to provide the MOS type circuit at a sufficient distance from the fuse element, which, as in the case described above, becomes an obstacle to higher density.

The present invention has been made to solve the above-mentioned drawbacks.
The present invention aims to provide a semiconductor device that prevents adverse effects on MOS type circuit operation and defects caused by contaminant ions after programming.

Hereinafter, the present invention will be explained in detail based on the embodiment shown in FIGS. 2a and 2b.

FIG. 2a is a plan view of a main part of a semiconductor device having a fuse element of the present invention, and FIG.
FIG. 3 is a sectional view taken along line B'. In the figure, 11 is an n-type silicon substrate containing donor impurities such as phosphorus, arsenic, or antimony with an impurity concentration of, for example, 10 ¹⁵ cm ^-3 , and on the surface of this substrate 11 is a field insulating film 12 ₁ made of, for example, a silicon oxide film. 12 ₂ are provided. Note that the field insulating film 12 ₁ ,
12 ₁ and 12 ₁ are connected to each other, while the field insulating film 12 ₂ has an island shape. On the surface of the island-shaped substrate region surrounded by the field insulating film ₁₂₁ , P ⁺ type sources electrically isolated from each other,
Drain regions 13, 14 are provided. A substrate 11 between these source and drain regions 13 and 14
For example, a sheet resistor 15 is formed on the top through a gate insulating film 15 made of silicon oxide with a thickness of 500 Å, for example.
A gate electrode 16 made of polycrystalline silicon of Ω-cm and 5000 Å thick is provided. The source and drain regions 13 and 14, the gate insulating film, the gate electrode 16, and the like constitute a p-channel MOS transistor. Further, on the island-shaped field insulating film ₁₂₂ , a width of, for example, 2 μm and a length of 2 μm is provided.
Fuse element 1 made of 6μm polycrystalline silicon
A polycrystalline silicon layer 18 having a width wider than that of the fuse element 17 is provided at both ends of the fuse element 17.
₁ and 18 ₂ are integrally connected. Note that fuse element 17 and polycrystalline silicon layers 18 ₁ and 18 ₂
is formed in the same process as the polycrystalline silicon gate electrode 16. A p-type impurity region 19 having a conductivity type opposite to that of the substrate 11 and having a depth of 8 μm is buried under the island-shaped field insulating film 12 ₂ . That is, a p-type impurity region 19 is buried in the surface of the substrate 11 below the fuse element 17. This p-type impurity region 19 contains an acceptor impurity such as boron at a concentration near the surface of 10 ¹⁶ cm ^-3 . Further, the surface of the substrate 11 around the p-type impurity region 19 has, for example, a boron concentration of 10 ²⁰ cm ^-3 and a depth.
A p ⁺ type guard ring region 20 of 0.5 μm is buried. Note that this guard ring area 20 is
It is formed in the same process as the p ⁺ type source and drain regions 13 and 14 of the MOS transistor. Said n
The surface of the mold silicon substrate 11 has a surface concentration, for example.
An n ⁺ type region 21 with a thickness of 10 ²⁰ cm ⁻³ and a depth of 0.3 μm is buried.

Furthermore, the gate electrode 16 and the fuse element 1
The entire surface of the substrate 11 including the substrate 7 and the like is covered with an interlayer insulating film 22 made of CVD-SiO ₂ or the like. On this interlayer insulating film _{22 , p} ⁺
The source extraction Al wiring layer 24 connected to the type source region 13 is connected to the contact holes 25 ₁ , 25 ₂ , 2
A drain lead-out Al wiring layer 26 connected to the p ⁺ type drain region 14 via 5 ₃ . . . is provided, respectively. This drain extraction Al wiring layer 26 has an extended Al wiring layer 26a extending toward the fuse element side.
This wiring layer 26a is connected to a polycrystalline silicon layer 18 ₁ connected to one end of the fuse element 17 via a contact hole 27 ₁ opened in the interlayer insulating film 22. Further, the interlayer insulating film 2
2 is connected to the polycrystalline silicon layer 18 ₂ at the other end of the fuse element 17 through a contact hole 27 ₂ opened in the insulating film 22 _{, and} p ⁺ An Al contact layer 29 is provided which is connected to the guard ring region 20 of the mold. A reverse bias voltage is applied to the substrate 11 from the Al contact layer 29 to the p ⁺ type guard ring region 20 . Furthermore, the interlayer insulating film 2
1 through the contact hole 30 ^.
A power supply line 31 connected to the mold region 21 is provided. Incidentally, a window 32 is opened in a portion of the interlayer insulating film 22 on the fuse element 17 for heat radiation.

In order to blow out the fuse element 17 with a current, for example, in the semiconductor device having the above-described structure, the Al wiring layer 29 connected to the polycrystalline silicon layer 18 ₂ at the other end of the fuse element 17 via the contact hole 27 ₂ is set to a ground potential (OV). Then, the source lead-out Al wiring layer 24 is set to Vcc potential (5V), and a voltage of about -15V is applied to the gate electrode 16 of the p-channel MOS transistor. At this time, p channel
The channel width of the MOS transistor is 500μm,
If the channel length is set to 2.5 μm, a current of about 60 mA flows between the source and drain regions 13 and 14. Therefore, a fuse is formed between the polycrystalline silicon layer 18 ₁ connected to the extended wiring layer 26a of the drain extraction Al wiring layer 26 via the contact hole 27 ₁ and the polycrystalline silicon layer 18 ₂ connected to the Al wiring layer 29. A current of approximately 60 mA flows through the element 17, melting the fuse element 17, and allowing it to be cut further.

Therefore, the minority carriers among the carriers generated in the silicon substrate 11 during programming by current blowing of the fuse element 17 are dissipated into the peripheral circuit. However, the lower part of the fuse element 17 is a field insulating film 12 ₂ and a p-type impurity region 1.
9 is separated from the n-type silicon substrate 11, and the p-type impurity region 19 is biased to the ground potential, so the minority carriers among the pair of carriers generated are absorbed by the p-type impurity region 19 and transferred to the peripheral circuit. It can prevent it from spreading.

Furthermore, the heat generated when the fuse element 17 is blown out releases alkali ions and metal ions that have been trapped in the field insulating film 12 ₂ etc. due to the getter effect and contaminates the surrounding insulating film. However, the contaminated field insulation film 12 ₂
A p-type impurity region 19 is provided below, and this impurity region 19 is biased to the ground by an Al wiring layer 29 connected to a guard ring region 20 on the outer periphery, so that the contaminating ions are absorbed into the p-type impurity region 19 or It does not diffuse outward from the insulating film on the guard ring region 20, but remains in or on the insulating film on the p-type impurity region 19 or the guard ring region 20. Therefore, according to the present invention, even if the fuse element and the peripheral MOS type circuit are provided close to each other, it is possible to prevent an adverse effect on the operation of the MOS type circuit, and to ensure reliability after programming. High density can be achieved.

In the above embodiment, only the current blowing type was explained as a programming method for the fuse element, but the same effects as in the embodiment can be obtained even when applied to laser cutting, current short circuit, and laser short circuit.

Furthermore, although an n-type silicon substrate was used in the above embodiment, a p-type silicon substrate or the like may also be used.

As described in detail above, according to the present invention, it is possible to prevent adverse effects on the operation of neighboring MOS type circuits when programming a fuse element, as well as to prevent defects due to contaminant ions after programming, and as a result, a highly reliable semiconductor device with a high density ratio can be prevented. can be provided.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view for explaining problems during programming of a semiconductor device having a conventional fuse element, FIG. is a cross-sectional view taken along the line BB' in figure a. 11... n-type silicon substrate, 12 ₁ , 12 ₂ ...
Field insulating film, 13... p ⁺ type source region,
14...p ⁺ type drain region, 16...gate electrode, 17...fuse element, 19...p type impurity region, 20...p ⁺ type guard ring region, 22
...Interlayer insulating film, 23 ₁ to 23 ₂ , 25 ₁ to 25 ₃ ,
27 ₁ , 27 ₂ , 28 ₁ to 28 ₇ , 30... Contact hole, 24... Source extraction Al wiring layer, 2
6...Drain extraction Al wiring layer, 29...Al wiring layer.

Claims (1)

[Scope of Claims] 1. A semiconductor device comprising a semiconductor substrate of one conductivity type on which a MOS transistor is provided, and a fuse element provided on the surface of the substrate with an insulating film interposed therebetween, in which a semiconductor under the fuse element is provided. 1. A semiconductor device characterized in that an impurity region is provided in a base portion, the impurity region having a conductivity type opposite to that of the base and to which a reverse bias is applied to the base. 2. The semiconductor device according to claim 1, wherein the fuse element is of a current blowing type. 3. The semiconductor device according to claim 1, wherein the fuse element is of a laser cutting type or a laser shorting type. 4. The semiconductor device according to claim 1, wherein the impurity region has an impurity concentration and depth comparable to that of a well region in which a MOS transistor is formed on the surface. 5. The semiconductor device according to claim 1, wherein the fuse element is made of the same material as the gate electrode material of the MOS transistor. 6. The semiconductor device according to claim 1, wherein the insulating film has a thickness sufficiently larger than that of a gate insulating film of a MOS transistor.