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JPS6351370B2 - - Google Patents

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Publication number
JPS6351370B2
JPS6351370B2 JP56152680A JP15268081A JPS6351370B2 JP S6351370 B2 JPS6351370 B2 JP S6351370B2 JP 56152680 A JP56152680 A JP 56152680A JP 15268081 A JP15268081 A JP 15268081A JP S6351370 B2 JPS6351370 B2 JP S6351370B2
Authority
JP
Japan
Prior art keywords
single crystal
oxide film
silicon layer
polycrystalline silicon
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56152680A
Other languages
Japanese (ja)
Other versions
JPS5853823A (en
Inventor
Seiichiro Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56152680A priority Critical patent/JPS5853823A/en
Publication of JPS5853823A publication Critical patent/JPS5853823A/en
Publication of JPS6351370B2 publication Critical patent/JPS6351370B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に係り、特に半
導体基板の一部に形成した絶縁膜と半導体基板上
に多結晶膜を形成し、該多結晶膜をレーザアニー
ルして単結晶化する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular includes forming an insulating film on a part of a semiconductor substrate and a polycrystalline film on the semiconductor substrate, and annealing the polycrystalline film with a laser. Concerning a method for single crystallization.

従来、多結晶をCVD法（Chemical Vapor
Deposition）法によつて基板上に形成し、レーザ
アニールによつて単結晶領域を形成したり、真空
蒸着によつて単結晶シリコン基板上に形成した非
晶質シリコン層にパルスレーザーを照射し、非晶
質膜を単結晶化している。 Conventionally, polycrystals were produced using the CVD method (Chemical Vapor
A pulse laser is irradiated onto an amorphous silicon layer formed on a substrate using a deposition method, a single crystal region is formed using laser annealing, or an amorphous silicon layer is formed on a single crystal silicon substrate using vacuum evaporation. The amorphous film is made into a single crystal.

上述の如きレーザアニールに於て、第１図に示
すように半導体基板１として単結晶シリコン基板
上に絶縁膜即ち熱酸化膜（SiO2）２が形成され、
これら単結晶シリコン基板（Single−Si）及び熱
酸化膜２上にCVD法により0.2〜0.6μｍ厚程度の
多結晶シリコン層３（Poly−Si）を形成し、CW
レーザ４等を照射し、矢印ａ方向にレーザを走査
することで多結晶シリコン層３を溶融して単結晶
化がなされる。 In the laser annealing described above, an insulating film, that is, a thermal oxide film (SiO 2 ) 2 is formed on a single crystal silicon substrate as a semiconductor substrate 1, as shown in FIG.
A polycrystalline silicon layer 3 (Poly-Si) with a thickness of about 0.2 to 0.6 μm is formed on these single-crystal silicon substrates (Single-Si) and thermal oxide film 2 by the CVD method, and
By irradiating with a laser 4 or the like and scanning the laser in the direction of arrow a, the polycrystalline silicon layer 3 is melted and made into a single crystal.

上述の様なレーザアニール技術で多結晶シリコ
ン層３を単結晶化する場合に、酸化膜２上の多結
晶シリコン層３ａと単結晶シリコン基板１上の多
結晶シリコン層３ｂをレーザアニールにより溶融
する時に溶融に要するレーザエネルギーが異な
り、単結晶シリコン基板１上の多結晶シリコン層
３ｂを溶融する方が酸化膜２上の多結晶シリコン
層３ｂを溶融するより多くのエネルギーを必要と
する。 When polycrystalline silicon layer 3 is single-crystallized using the laser annealing technique as described above, polycrystalline silicon layer 3a on oxide film 2 and polycrystalline silicon layer 3b on single-crystal silicon substrate 1 are melted by laser annealing. Sometimes, the laser energy required for melting differs, and melting polycrystalline silicon layer 3b on single-crystal silicon substrate 1 requires more energy than melting polycrystalline silicon layer 3b on oxide film 2.

これは、酸化膜２の熱伝導率が、0.014W／cm，
degであるのに対し単結晶シリコン基板１の熱伝
導率が1.5W／cm，degと約２桁の差があることに
起因するものと考えられる。 This means that the thermal conductivity of oxide film 2 is 0.014W/cm,
This is thought to be due to the fact that the thermal conductivity of the single crystal silicon substrate 1 is 1.5 W/cm, which is about two orders of magnitude different from the thermal conductivity of the single crystal silicon substrate 1.

即ち、単結晶シリコン基板１の熱伝導率が大き
いためにレーザエネルギーがより多く逃げるため
である。 That is, since the thermal conductivity of the single crystal silicon substrate 1 is high, more laser energy escapes.

上述の如く照射するレーザエネルギーが異るこ
とにより次の如き弊害が生ずる。 As described above, the following disadvantages occur due to the difference in irradiation laser energy.

即ち、酸化膜２上の多結晶シリコン層３ａが充
分に溶融するようなレーザエネルギーを照射する
と単結晶シリコン基板１上の多結晶シリコン層３
ｂを溶融させることが出来ず、一方単結晶シリコ
ン基板１上の多結晶シリコン層３ｂを充分に溶融
させるレーザエネルギーを照射すると酸化膜２上
の多結晶シリコン層３ａにとつてはパワーが強す
ぎてはがれの生ずる原因となる。 That is, when laser energy is irradiated to sufficiently melt the polycrystalline silicon layer 3a on the oxide film 2, the polycrystalline silicon layer 3a on the single crystal silicon substrate 1 melts.
On the other hand, if the laser energy to sufficiently melt the polycrystalline silicon layer 3b on the single crystal silicon substrate 1 is irradiated, the power is too strong for the polycrystalline silicon layer 3a on the oxide film 2. This may cause peeling.

いずれにしても、この様な半導体装置の基板で
レーザアニールを例えば、ａ方向走査すると単結
晶シリコン基板１と酸化膜２の境界付近で吸収エ
ネルギーのミスマツチングが起つて単結晶シリコ
ン基板１からの単結晶化が困難となる欠点を有す
る。 In any case, when laser annealing is performed on the substrate of such a semiconductor device, for example, by scanning in the a direction, mismatching of absorbed energy occurs near the boundary between the single crystal silicon substrate 1 and the oxide film 2, resulting in a loss of energy from the single crystal silicon substrate 1. It has the disadvantage that crystallization is difficult.

本発明は上述の如き欠点を除いた半導体装置の
レーザアニーリングを提供するものであり、本発
明の特徴とするところは、多結晶シリコン層３上
に厚さの異なるキヤツプをかぶせ単結晶シリコン
基板１と酸化膜２上の多結晶シリコン層が常に同
じ吸収エネルギーを吸収する様にし、境界のミス
マツチング現象を避けることで半導体基板上の多
結晶シリコン層をレーザアニーリングにより単結
晶化するものである。 The present invention provides laser annealing for semiconductor devices that eliminates the above-mentioned drawbacks.The present invention is characterized by covering the polycrystalline silicon layer 3 with caps of different thicknesses and forming the monocrystalline silicon substrate 1. The polycrystalline silicon layer on the semiconductor substrate is made into a single crystal by laser annealing by making sure that the polycrystalline silicon layer on the oxide film 2 always absorbs the same absorbed energy and avoiding the boundary mismatching phenomenon.

以下、本発明の実施例を図面を参照して説明す
る。 Embodiments of the present invention will be described below with reference to the drawings.

第２図は本発明を得る過程を説明する為の半導
体基板の断面図を示すものであり、単結晶シリコ
ン基板１上に5000〜6000Åの酸化膜２を形成し、
その上に4000Åの多結晶シリコン層３上にCVD
法又は熱酸化によつてSiO2即ち第２の酸化膜５
を1μｍの厚みでキヤツプとして堆積させたもの
に、CW−Arレーザ４を照射して酸化膜２上の多
結晶シリコン３ａを溶融させて単結晶化させると
きのレーザパワーは10W（10cm／s500℃・60μφ）
である。 FIG. 2 shows a cross-sectional view of a semiconductor substrate for explaining the process of obtaining the present invention, in which an oxide film 2 of 5000 to 6000 Å is formed on a single crystal silicon substrate 1,
On top of that, CVD on 4000 Å polycrystalline silicon layer 3
SiO 2 , that is, the second oxide film 5, is formed by
is deposited as a cap with a thickness of 1 μm and is irradiated with a CW-Ar laser 4 to melt the polycrystalline silicon 3a on the oxide film 2 and turn it into a single crystal.The laser power is 10W (10cm/s at 500°C).・60μφ)
It is.

これに対して単結晶シリコン基板１上の多結晶
シリコン層３ｂを溶融させて単結晶化させるとき
のレーザパワーは14W（同一条件）であつた。 On the other hand, the laser power when melting the polycrystalline silicon layer 3b on the single crystal silicon substrate 1 to form a single crystal was 14 W (under the same conditions).

これらを考慮するとレーザパワーに４割の差が
あるので、この差をなくす為の上記第２の酸化膜
５の厚みをコントロールすることでエネルギー吸
収率をコントロールすることが出来る。 Taking these into consideration, there is a 40% difference in laser power, so the energy absorption rate can be controlled by controlling the thickness of the second oxide film 5 to eliminate this difference.

即ち、第３図に示す線に酸化膜２上の多結晶シ
リコン層３ａ上に1μｍの第２の酸化膜５ａを好
ましくはCVD法により厚みt1がコントロール出
来る様に形成し、同じく単結晶シリコン基板３上
の多結晶シリコン層３ｂの上にCVD法で形成す
る第２の酸化膜５ｂの厚みt2を約9000Åと成るよ
うにする。 That is, a second oxide film 5a having a thickness of 1 μm is formed on the polycrystalline silicon layer 3a on the oxide film 2 along the line shown in FIG. 3, preferably by CVD method so that the thickness t1 can be controlled. The thickness t 2 of the second oxide film 5b formed by the CVD method on the polycrystalline silicon layer 3b on the substrate 3 is about 9000 Å.

この様な厚みにすると上記1μｍの厚みの第２
の酸化膜（SiO2）３ａでは反射率が38％、吸収
率が62％となり、9000Åの厚みの第２の酸化膜３
ｂでは反射率が13％吸収率87％となり、単結晶シ
リコン基板１上の多結晶シリコン３ｂの上の第２
の酸化膜５ｂには、酸化膜２上の多結晶シリコン
層３ｂの上の第２の酸化膜５ａに比べて40％多く
のレーザエネルギーを吸収するようになる。 With such a thickness, the second layer of the above 1 μm thickness
The second oxide film (SiO 2 ) 3a with a thickness of 9000 Å has a reflectance of 38% and an absorption rate of 62%.
In b, the reflectance is 13% and the absorption rate is 87%, and the second layer on the polycrystalline silicon 3b on the single crystal silicon substrate 1 is
The oxide film 5b absorbs 40% more laser energy than the second oxide film 5a on the polycrystalline silicon layer 3b on the oxide film 2.

一般に第２の酸化膜５ａ，５ｂの厚さを横軸に
縦軸に反射率をとると、それらの関係は第４図に
示す如く周期函数となるので上述したように反射
率の差が40％になるような第２の酸化膜の選択方
法は複数個所あり、本発明ではこれらのどの点を
選択してもよいが、好ましくは第２の酸化膜５ａ
の反射率をSiO2の最高の38％の反射率に選択し、
それから40％反射率の少ない第２の酸化膜５ｂ点
を選択すればよい。 Generally, when the thickness of the second oxide films 5a and 5b is plotted on the horizontal axis and the reflectance is plotted on the vertical axis, the relationship between them becomes a periodic function as shown in FIG. %, and in the present invention, any of these methods may be selected, but preferably the second oxide film 5a
The reflectance of SiO2 is selected to be the highest 38% reflectance of SiO2,
Then, a point 5b of the second oxide film having a 40% lower reflectance may be selected.

本発明は上述の如く第２の酸化膜の反射率に着
目したので冒頭に述べた単結晶シリコン基板と酸
化膜上に形成した多結晶シリコン層をレーザアニ
ールする際にレーザ照射エネルギーを一様にして
インターバルエピタキシヤル成長を行うことが出
来て境界のミスマツチを防止し得るものである。 As mentioned above, the present invention focuses on the reflectance of the second oxide film, so when laser annealing the single crystal silicon substrate mentioned at the beginning and the polycrystalline silicon layer formed on the oxide film, the laser irradiation energy is made uniform. This allows interval epitaxial growth to be carried out using the same method, thereby preventing boundary mismatches.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装置基板の側断面図、第
２図は本発明の半導体装置基板の発明原理を導く
ための側断面図、第３図は本発明の半導体装置基
板の一部を断面とする側断面図、第４図は本発明
の説明に供する反射率と酸化膜の厚みの関係を示
す線図である。 １……単結晶シリコン基板、２……酸化膜、３
……多結晶シリコン層、４……レーザ光、５……
第２の酸化膜。 FIG. 1 is a side sectional view of a conventional semiconductor device substrate, FIG. 2 is a side sectional view for explaining the inventive principle of the semiconductor device substrate of the present invention, and FIG. 3 is a partial cross-sectional view of the semiconductor device substrate of the present invention. FIG. 4 is a diagram showing the relationship between the reflectance and the thickness of the oxide film, which is used to explain the present invention. 1... Single crystal silicon substrate, 2... Oxide film, 3
... Polycrystalline silicon layer, 4 ... Laser light, 5 ...
Second oxide film.

Claims (1)

【特許請求の範囲】 １ 単結晶半導体基板上の一部に第１の絶縁膜を
形成し、該単結晶半導体基板と該第１の絶縁膜上
に非単結晶半導体層を形成し、エネルギー線を照
射して該非単結晶半導体層を単結晶化する半導体
装置の製造方法に於て、該第１の絶縁膜上に形成
した多結晶半導体層と、単結晶半導体基板上に形
成した多結晶半導体層上に互いに反射率を異にす
る第２の絶縁膜を形成してエネルギー線を照射す
ることを特徴とする半導体装置の製造方法。 ２ 前記第２の絶縁膜の反射率の差を略40％とす
ることを特徴とする特許請求の範囲第１項記載の
半導体装置の製造方法。[Claims] 1. A first insulating film is formed on a part of a single crystal semiconductor substrate, a non-single crystal semiconductor layer is formed on the single crystal semiconductor substrate and the first insulating film, A method for manufacturing a semiconductor device in which the non-single crystal semiconductor layer is made into a single crystal by irradiation with a polycrystalline semiconductor layer formed on the first insulating film and a polycrystalline semiconductor formed on the single crystal semiconductor substrate A method for manufacturing a semiconductor device, comprising forming second insulating films having different reflectances on the layers and irradiating the layers with energy rays. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the difference in reflectance of the second insulating film is approximately 40%.
JP56152680A 1981-09-26 1981-09-26 Manufacturing method of semiconductor device Granted JPS5853823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56152680A JPS5853823A (en) 1981-09-26 1981-09-26 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56152680A JPS5853823A (en) 1981-09-26 1981-09-26 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5853823A JPS5853823A (en) 1983-03-30
JPS6351370B2 true JPS6351370B2 (en) 1988-10-13

Family

ID=15545760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56152680A Granted JPS5853823A (en) 1981-09-26 1981-09-26 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5853823A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0611035B2 (en) * 1983-04-15 1994-02-09 ソニー株式会社 Thin film heating method
JPS63215035A (en) * 1987-03-04 1988-09-07 Agency Of Ind Science & Technol Protective film for recrystallization treatment
JPS6423521A (en) * 1987-07-20 1989-01-26 Agency Ind Science Techn Protective film for recrystallization treatment

Also Published As

Publication number Publication date
JPS5853823A (en) 1983-03-30

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