JPS6350738B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to access devices.

A common bus system in which processors, memories, and input/output devices are connected via a common bus is widely used in computer systems because it is easy to connect and has excellent expandability. In the common bus method, each processor and each input/output device can access memory independently, so the processor only needs to give the input/output device the starting point and length of the memory range, and then the input/output device and memory So-called DMA transfer, in which data is transferred only between However, in recent computer systems, the unique address space required by a processor, etc. does not necessarily correspond to the same address as the physical address space of memory, and techniques such as segmentation and paging have made it possible to separate the address blocks of the processor, etc. It corresponds to the physical address space of memory. In such a case, the processor issues the DMA transfer command to the input/output device, gives the start point address and length, and the input/output device transfers data directly to the memory, but the input/output device cannot handle data within this range. The memory address specified by the address does not necessarily correspond to a series of physical addresses in memory, and if these addresses are discretely associated, the input/output device will be operated in order from the starting address. Since memory accesses are made to memory addresses, memory addresses are treated as non-existent memory addresses at the end of the memory correspondence. This kind of situation is relatively easy to deal with in the case of a single bus system, but in a so-called multiple bus system that combines two or more buses, it is possible to handle DMA transfer commands across the memories on each bus. If you do, a big problem will occur. For example, when issuing a DMA transfer command from a processor on one bus to an input/output device on the other bus, if the memory on both buses is handled contiguously from the processor's perspective, then the Since the address boundary of the address boundary is not known, a DMA transfer command for a memory range spanning two buses will be issued. Furthermore, in this case, if the memory addresses on both buses correspond to each other discretely when viewed from the side of the input/output device on the other bus, there is a problem that such memory addresses will be treated as absent memory addresses.

In conventional access devices, before issuing a DMA transfer command, the processor checks whether the memory address boundary spans both buses. However, in the case of the above-mentioned multiple bus system, etc., there is a drawback that the burden on the processor side increases because the system configuration cannot be known until it is investigated.

The object of the invention is to provide an access device which eliminates the above-mentioned drawbacks.

The access device of the present invention has a common bus system in which the unique address space required by each device corresponds discretely with the physical address space of the memory on the common bus, and is arranged on the common bus within a predetermined range. a detector that detects that an access to a memory address is requested and holds the state of the access at the time of the detection; a responder that responds to the detection; an address converter that performs translation into a physical address space of a memory predetermined in accordance with the state; and an address converter that performs translation into a physical address space of a memory determined in advance according to the state; The present invention is characterized in that it includes a proxy device that performs the following operations.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an access device showing one embodiment of the present invention. The detector 1 inputs an access request 101 coming from the common bus 10, requesting access to a memory address in a predetermined range, that is, an address of an absent memory resulting from crossing a discretely associated address boundary. The state of the access request 101 at the time of detection is then held and a holding output 105 is output. When the responder 3 receives the detection output 104, it sends a response 102 to the common bus 10 and outputs a response output 106. On the other hand, when the address converter 2 receives the held output 105, it converts the held output 105 into a corresponding physical address of a predetermined memory and outputs an address translation output 107. Also, the proxy device 4 has a response output of 10
6, a proxy access 103 is made to the common bus 10 in order to access the memory address corresponding to the address translation output 107 in accordance with the holding output 105. As mentioned above, an access request 101 for unavailable memory issued from a certain device
is temporarily accepted, the address is converted, and the address is correctly transmitted to the actual memory in the form of proxy access 103.

FIG. 2 is a block diagram showing an example of the configuration of the detector 1 shown in FIG. The address table 21 receives a start signal 202 indicating the arrival of the access request 101.
The address part 203 of the access request 101 by
is input, it is checked whether the address field 203 matches a value set in advance in the address table 21, and a detection output 104 is output only when the result is a match. Next, when the holder 22 receives the detection output 104, it holds the state of the access request 101 at the time of the detection and outputs a holding output 105.

FIG. 3 is a block diagram showing an example of the configuration of the transponder 3 shown in FIG. 1. When the response circuit 31 receives the start signal 202 and the detection output 104, the response circuit 31 generates a response 1.
Outputs the approval output 301 of 02 and outputs the response output 106 at the same time. When the start signal 202 is canceled, the approval output 301 and the response output 106 are canceled.

FIG. 4 is a block diagram showing an example of the structure of the address converter 2 shown in FIG. 1. By inputting the physical address of the memory in advance to its contents, the address translation memory 41 obtains the address translation output 107 as read data when the address part 401 of the holding output 105 is input.

FIG. 5 is a block diagram showing an example of the configuration of the proxy device 4 shown in FIG. 1. The control circuit 51 has a response output 10
When 6 is input, a use request 501 is issued to the common bus 10, and when a use approval 502 is subsequently input, a start signal 202 and a gate output signal 505 are output.
Next, when the gate circuit 52 receives the gate output signal 505, the address conversion output 107 is input to the common bus 1.
0 address 503, and further holds output 1
The access state 508 constituting 05 is transferred to the common bus 1.
It outputs to the access state 506 of 0 and specifies a write or read request to the memory.
On the other hand, when the gate circuit 53 receives the gate output signal 505, the data section 50 constituting the holding output 105
7 is output to the data section 504 of the common bus 10, and when writing to the memory, the write data is transmitted to the memory, and when reading, the address of the device that made the read request first is transmitted to the memory as is. Next, when the control circuit 51 receives the approval output 301 from the common bus 10, it receives a use request 501 and a start signal 20.
2 and the gate output signal 505 are released to end the operation of the proxy access 103.

According to the present invention, even if an access request using a unique address issued from each device exceeds the physical address boundary of discretely associated memory, this request can be made to a non-existent memory address. The access is correctly transmitted to the memory by detecting the access request and returning a response once to make it valid, while converting the address and delegating the access to the memory at the actual corresponding physical address. Since the access to the absent memory can be relieved, the burden on the processor is reduced and an efficient access device can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an access device showing one embodiment of the present invention, and FIGS. 2 to 5 are block diagrams showing respective configuration examples of the detector, responder, address converter, and agent in FIG. 1. It is a diagram. 1...Detector, 2...Address converter, 3...
Responder, 4... Acting device, 10... Common bus, 21
...address table, 22...retainer, 31...
...Response circuit, 41...Address conversion memory, 51
...Control circuit, 52, 53...Gate circuit.

Claims (1)

[Claims] 1 Access to memory addresses in a predetermined range on the common bus of a common bus system in which the unique address space requested by each device corresponds discretely with the physical address space of the memory on the common bus. a detector that detects that a request has been made and holds the access state at the time of the detection; a responder that responds to the detection; an address translator that performs translation into a predetermined physical address space of memory; and a proxy device that accesses the memory indicated by the translated address in response to the response in accordance with the maintained access state. An access device comprising: