JPS6350139A - Sequence signal generator - Google Patents

Abstract

PURPOSE:To obtain an easily changeable sequence signal generating device by a simple circuit constitution, by converting the number of bits in one frame and the number of frames to binary signals, and transferring them as synchronizing signals to a frame number counting means and a frame signal converting means. CONSTITUTION:A bit number counting means (a) inputs a data string to be sent and received to and from a communication line L1 and counts the number of bits of one frame, and a frame number counting means (b) counts the number of frames. Subsequently, a bit signal converting means (c) converts a counting value obtained by the bit number counting means (a), to a binary signal. A counting value obtained by the frame number counting means (b) is converted to a binary signal for showing the output timing of a flag, by a frame signal converting means (d), and by a transfer means (e), the binary signal obtained from the bit signal converting means (c) is transferred as a synchronizing signal to the frame number counting means (b) and the frame signal converting means. Also, the binary signal for showing whether it is effective or ineffective and the binary signal for showing the output timing are outputted as sequence signals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sequence signal generation device for transmitting and receiving data strings having a multi-frame structure, and particularly to
The present invention relates to a sequence signal generating device used in a gateway switch (hereinafter referred to as a G/W device) that connects a local area network (N) and a public communication line to perform packet switching.

[Prior Art] In recent years, advances in semiconductor technology have made it easier to receive so-called packet switching services. This packet exchange means to send a data string to a predetermined length, for example, 12
8 hides) and sends each piece of data with a destination address and an order code indicating the order of the data as a packet, and the exchange that receives this packet stores it in its memory. , the destination address, etc., and delivers the packet to the destination terminal indicated by that address.

The specifications of this packet switching system are described in detail in Recommendation No. 25 of CCITT (Commission International Telegraph and Telephone Inquiry).

FIG. 9 shows an example of the configuration of a line including a G-HA device in a conventional example.

In FIG. 9, LANI is the first local area
network, terminal adapter 26-1.26-2
．． 26-3 to the packet form terminal 27-1゜27-
2.27-3 is connected. In addition, the G/W device 23
-1.23-2 is also connected to the same network LANI. 29 is a digital dedicated line, and 30 is a DDK packet switching network. 24-1.24-2 is a digital service unit (DSll) for connecting the digital dedicated line 29 and a normal line, and 24-3.24-4
is a DSU for connecting the DDK packet switching network 30 and a normal line. Further, the digital dedicated line 29 and the host 28 are connected via the DSU'24-2.

LAN2 is a second local area network, and is connected to DD×packet switching network 30 via G/W device 23-3 and DSU 24-4. Also,
A terminal adapter 26-4 and a packet type terminal 27-4 are connected to the LAN2.

For example, packet exchange between the terminal 27-1 and the host 28 will be explained.

First, a packet transmitted from the terminal 27-1 is attached with a LANI header by the terminal adapter 26-1, and
It is sent to the G/W device 23-1 via ANI. G/W
The receiving device 23-1 removes the LANI header from the received packet, corrects the destination address, and then sends it to the host 28 via the DSU 24-1. The host 28 is a digital dedicated line 29, DSt1
24-2.

Conversely, a packet originating from the host 28 is processed in the opposite manner to that described above and reaches the terminal 27-1.

Next, for example, a case will be described in which a packet for which a call has failed is sent from the terminal 27-1 to the terminal 27-4.

The packet sent from the terminal 27-1 is sent to the terminal adapter 2.
At step 6-1, a header for LAN l is attached and sent to network L via Nl to G/W device 23-2.

In the G/W device 23-2, the LANI ladder is deleted from the packet. Next, after writing the extension address of the terminal 27-4 in a predetermined place in the packet,
The packet is sent to the DDK packet switching network 30 according to the procedure shown in CITT x, 25.

Eventually, the packet is sent to the G/W via the DSU24-4.
It is sent to device 23-3. The G/W device 23-3 analyzes the extension address of the packet, obtains the address of the destination terminal, adds a ladder for LAN2 to the packet, and then sends the packet to the network LAN2. Terminal adapter 26-4, which receives the packet from network LAN2, deletes the LAN2 header from the packet and sends it to terminal 27-4. The packets sent from the terminal 27-1 according to the procedure described above arrive at the terminal 27-4 in exactly the same format.

On the other hand, if the packet is sent from the terminal 27-4, it will arrive at the terminal 27-1 using the reverse procedure as described above.

FIG. 1θ shows an example of the internal configuration of a conventional G/W device.

In CCTTT's X, 25 protocols (communication regulations),
O5T (0'pe) defined by 150 (International Organization for Standardization)
n SysLemsInterconnection)
Among the seven layers of the reference model, Layer 2 defines the method of transmitting and receiving data, error control, window control, etc. according to HDLC (High Level Data Link Control Procedure), and calling when connecting with a communication partner. It stipulates Layer 3, which defines procedures, order control, etc.

Regarding Layer 1, which defines the connector shape, pin number, electrical characteristics, etc., an appropriate protocol can be selected from several protocols depending on the type of line to be connected.

For example, a digital leased line is X,21, an analog leased line is X,21biS, and a DDK packet switching network is X,21,
The telephone line can be selected such as V, 27ter, etc.

On the public line side of Figure 1, 1 is x, DTE for 21
(terminal equipment)/DCE (line termination equipment) interface circuit; 2 is an X, DTE/DCE interface circuit for 21bis; 3 is a high-speed digital interface circuit. Reference numeral 7 denotes a control circuit (MP(:C)) that performs frame-by-frame transmission and reception according to the above-mentioned IIDLc (high-level data link control procedure) regulations.

The interface circuits 1.2 and 3 are connected to connectors 4.5 and 6, respectively, which comply with ISO standards 154903 and 152, respectively.
110 and 154903, 15 bins each;
25 bins and 15 bins.

A microprocessor (Mpu) 9 operates according to a program written in a ROM (read only memory) (not shown) connected to the pass line 19, and controls each device connected to the pass line 19. 10 is a RAM (random access memory) for temporarily storing packets. 8 is a DMA controller (DMAC) for controlling DMA (direct memory access) transfer of data between the MPCG 7 and IIAMIO.

12 is a liquid crystal display (L(: DJ); 13 is an interface circuit for key matrix scanning;
4 is an interface circuit for human output of a toggle switch and an LED (light emitting diode).

The operation section (front panel) is composed of these interface circuits 13, 14, LEDs, toggle switches, a key matrix, and the LCD 12. Commands entered from the key matrix and toggle switches are processed and the results are displayed on the LCD 12 and LEDs.

Also, on the LAN (local network) side, 1
8 is an interface circuit for IEEE standard 802.4, and 17 is a control circuit (MPCG) that performs transmission and reception in units of frames. 16 is a DMA controller, and 15 is a microprocessor (MPII) that controls each device connected to the pass line 20.

Further, data is received and transferred between the public line side and the LAN side via a dual port RAM (D-RAM) 11.

For example, packets received from the public line side are MPC
D to nAMlo by control of DMAC8 via G7
MA is transferred. Read from RAMIQ
The packet whose header has been analyzed by 9 is sent to DMA again.
8, the data is transferred to the D-RAM 11.

Also, on the LAN side, the packet sent to the D-R Mll is added with a LAN header by the MPU 15, and then, under the control of the DMAC 16, the MPCG 17
and sent to the LAN.

Furthermore, packets received from the LAN side are sent to the public line side by the reverse procedure to that described above.

il1 diagram is 1. An example of a frame structure format of a conventional high-speed digital transmission service is shown.

The high-speed digital transmission service using the Gateway switch provided by NTT (Nichi-Telegraph and Telephone Corporation) uses three types of frame configurations depending on the data transmission speed. seconds, 154
There are three types: 4 bits/second and 6312 bits/second, and the frame configurations of each are significantly different. For example, in order to receive a service at a transmission rate of 192 bits/second, only the necessary portion of the information frame is extracted from the data string sent at a transmission rate of 1544 bits/second and used.

In FIG. 11, X is a 1-bit control bit,
Violation bit with this bit.

5END, IJNR, S, onR<z, etc. are divided into multiple frames and transmitted.

C111 to CI+24 are information bits, but when receiving 192 bits/second service, C11l to C
Using information bits up to 113, C114 to Cl24
is an invalid empty bit that is not used, and one transmission unit is constituted by a set of 24 frames having this structure.

[Problems to be solved by the invention] However, when using conventional NTT high-speed high-speed digital transmission, its frame structure is complex and the transmission speed is high. ) 11 to C) 13) and a complex and large-scale logic sequence circuit must be realized to extract the control bits The problem was that it was not easy to change.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a sequence signal generating device which eliminates the above-mentioned drawbacks, has a simple circuit configuration, and can be easily modified.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides data with a multi-frame structure in which one frame consists of a plurality of bit numbers and one transmission unit consists of a plurality of frames. In a gateway exchange that transmits and receives strings, there are bit number counting means for inputting a data string and counting the number of bits in one frame, and frame number counting means for inputting a data string and counting the number of frames within one transmission unit. , a bit signal conversion means for converting the count value obtained by the bit number counting means into a binary signal indicating whether the signal is valid or invalid, and a bit signal conversion means for converting the count value obtained by the frame number counting means into a binary signal indicating the output timing of the flag.
A frame signal converting means for converting into a value signal, and a pit 48
a transmission means for transmitting a binary signal obtained from the signal conversion means as a synchronization signal to the frame number counting means and the frame signal conversion means, and a sequence signal using a binary signal indicating validity or invalidity and a binary signal indicating output timing It is characterized by the occurrence of

[Operation] According to the present invention, a data string with a multi-frame structure is input, the number of bits in one frame and the number of frames in one transmission wheel position are counted, and the counted number of bits is used to determine whether a signal is valid or invalid. Converts the counted frame number into a binary signal indicating the output timing of the flag, and transmits the binary signal indicating validity or invalidity to the frame number counting means and the frame signal converting means as a synchronization signal. As a result, it is possible to realize a sequence signal generating device that has a simple circuit configuration and can be easily modified for other different frame structures.

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the basic configuration of an embodiment of the present invention.

In FIG. 1, L is a communication line that transmits a data string having a multi-frame structure. a is a bit number counting means,
The number of bits in one frame is counted by inputting a data string without sending or receiving data through a communication line. Reference numeral b denotes a frame number counting means, which counts the number of frames by inputting a data string to be exchanged with the communication line. C is a bit signal converting means, which converts the count value obtained by the bit number counting means into a binary signal that does not indicate whether the signal is valid or invalid.

d is a frame signal conversion means, and the count value obtained by the frame number counting means is used to indicate the flag output timing.
Convert to value signal. Reference numeral e denotes a transmitting means, which transmits the binary signal obtained from the bit signal converting means C to the frame counting means and the frame signal converting means as a synchronizing signal.

Further, a binary signal indicating validity or invalidity and a binary signal indicating output timing are output as a sequence signal.

FIG. 2 shows the overall configuration of a gateway exchange (hereinafter referred to as G/W device) according to an embodiment of the present invention.

In Figure 2, 18 is the line interface part, and the main part is 11: CITT Recommendation No. X, 2517)
Data is exchanged according to the IIDLc procedure, and since control methods differ depending on the type of line, these multiple types of lines are controlled in a unified manner.

In the embodiment of the present invention, the line interface section 48 is configured in accordance with C (: ITT's X, 21, X, 21 bcs recommendations or NTT's high-speed digital interface).

Reference numeral 49 denotes a line side processor section, which performs packet analysis and data transfer according to x and 25.

Reference numeral 50 denotes a key and display processor section, which performs operations of scanning and reading key switches arranged in a matrix (key matrix) and displaying characters on a liquid crystal display. Further, this key and display processor section 50 are connected to the line side processor section 4.
9 and the R5232C interface 41 perform asynchronous communication.

51 is a LAN side processor section, which complies with IEEE802.
It performs packet analysis and data transfer according to 4 standards. The interface between the LAN side processor section 51 and the line side processor section 49 is a dual port RAM.
This is done through shared memory (Random Access Memory).

52 is a LAN interface section, which is IEEE80
The token bus method is used in accordance with the 2.4 standard.

Since this token bus method is a data duram service (connectionless), it is possible to constantly communicate with the other terminal.

FIG. 3 shows a detailed configuration of the embodiment of the invention shown in FIG.

In FIG. 3, the same numbers are given to the components of the stud as in the conventional example of FIG. 1O, and detailed explanation thereof will be omitted.

In FIG. 3, 33 and 34 are switching circuits;
It is used to switch the input from the 5-bin socket 4 between the X, 21 interface 1 and the high-speed digital interface 3.

35 is a multiplexer (MPX), which is a circuit for selectively using any one of the 10,000 interface circuits 1 and 2. 36 is a FIFO (first-in, first-out) memory that reads data in the order in which it is stored, and is used to absorb the difference between the data transfer speed on the line side and the processing speed of the MPCC 7.

60 is a digital data extraction circuit (DDS);
S60 includes the sequence signal generator of the present invention, and uses DDS60 to extract only the effective portion in the frame of high-speed digital transmission.

The LCD (liquid crystal display) 12, key matrix interface circuit 13, LED and toggle switch human output interface circuit 14 are directly connected to the pass line I9 in the conventional example shown in FIG. 1θ, but these 12.13.
In the embodiment of the present invention, 14 is a pass line 40, a serial interface (ACIA) 38, and R52:12.
(It is connected to the path line 19 via an interface 41 and an ACI 83. A microprocessor (MPU) 39 controls each device connected to the path line 40.

45 is a DMA (direct memory access) interface circuit, which is an interface circuit for connecting the DMAC 8 which does not have an inter-memory data transfer function from one memory to another memory.

The D-RAM II, LAN-side DMAC 16, LAN-side MPU 15, LAN-side MPCC 17, and LAN-side interface circuit 18 are the same as those in the conventional example shown in FIG. 1O, and perform similar operations.

For example, if a packet is sent from the public line side through a high-speed digital communication line, connector 4. Each frame is taken into the DDS δO via the switching circuit 34 and the high-speed digital interface 3. Next, the valid information stored in the DDS 80 is 1
D
Temporarily stored in R to Ml[l under the control of MAC8.

At this time, the information of the DDS 60 is read out on average in synchronization with the transfer rate of the DiAAC 8.

In RAM10, the packet whose header has been analyzed is
DRAM is transferred via the DMA interface circuit 45 by -J control of the DMAC 8, which does not have a transfer function between memories.
Sent to II.

Since the operation on the LAN side is the same as that of the conventional example shown in FIG. 1O, the explanation thereof will be omitted.

Furthermore, packets sent from the LAN side are sent to the 00560 memory 36 by the reverse procedure to that described above, and sent from there in accordance with the specifications of the public line side.

FIG. 4 shows an example of a detailed configuration of 00560 in the embodiment of FIG. FIG. 5 shows the timing of the person's output.

In FIG. 4, 85 is a high-speed digital interface module IC (i-product circuit, for example, Motorola's MC68652 is used.87-1 to 8) having the same function as the high-speed digital interface 3 shown in FIG.
7-3 and 91-1 to 91-3 are 8-bit shift registers, such as Texas Instruments' 5
N74LS165A is used.

88, 89, 92 and 93 are NAND gates (negative AND circuits). Further, 90 and 94 are OR gates (logical sum circuits). Further, 86 is a sequence signal generating device (sequencer) in the present invention, the details of which will be described later.

First, the reception operation when receiving a data string from a public line will be explained.

A clock (R1, CK in Fig. 5) whose phase is synchronized with the received signal is output from the R-C terminal of module IC85, and R
Received data (no in FIG. 5) is output from the -D terminal.

When a synchronization signal indicating the start of a frame is detected, the R-F terminal becomes "H" (high level) (R-F in Figure 5).
, then the received signal R-D is followed by the valid information bits Cl11, G112 and C113.

At this time, the RD-IN terminal of the sequencer 86 is
I(3 becomes °゛H゛', and the clock signal R(:LK
Since 24 pulses are sent to shift registers 87-1 to 87-3, the effective information bits (8 bits x 3 = 24 bits) are transmitted to shift registers 87-1.87-2.87-
3 in series.

Next, the signal of the RD-011T terminal of the sequencer 86 (
Figure 5) RD-OLIT) is C)14. C) 112
And since it becomes "H" at the C)120 (7) position, the 24-bit data taken into the shift register 85 becomes C)14.

CH12, [:) 120 positions are shifted by 8 bits, and M as C old', CH2', CH3'.
It is sent to the power of Rx5I (Rx51 in Figure 5) of P(:C7).

That is, as shown in FIG. 5, the positions of CH4, CH12, and CH2O are at equal intervals in time, so when the MPU 9 or DMAC 8 reads these C) 14, etc. 1 byte (8 bits) at a time, high-speed digital communication is performed. If the transmission rate of the line is, for example, 1544 Kbit/s, the data transmission rate is 24 puffs of 8 seconds, or 19
Averaged to 2 bits/sec.

Conversely, transmission can be performed by executing the same processing procedure as the above-described receiving operation.

Next, FIG. 6 shows the sequencer of the present invention shown in FIG. 4! ll
An example of a detailed circuit configuration of i is shown.

In FIG. 6, 96.97 is a counter, 98. Q
9 is ROM (read only memory), 10
0 and lot are latches, and 102 and 103 are NOR gates (negative OR circuits).

The counter 96 corresponds to the bit number counting means of the present invention,
The counter 97 corresponds to the frame number counting means of the present invention. Further, the ROM 98 corresponds to the bit signal converting means of the present invention, and the ROM 99 corresponds to the frame signal converting means of the present invention.

ROM 98 and 99 are, for example, Fujitsu's MB711.
8 is used, and the contents of the data written there are shown in (8) and (B) of FIG.

"0'° and °" shown in Figure 7 (A) and (B)
1′.

is input A of ROM 98. ~A7 or ROM 99 inputs A and -A5 are respectively binarized.
(low level) and "°H" (high level), and "-" indicates don't care (undefined).

OI~03 and O1~06 are each ROM 9
8 output OI ~ 03 is 1'', ROM 99 output 0, ~
This is the case where 06 becomes °゛1'', for example, as shown in Figure 7 (A)
The condition for 0 to become "1°" is input A.
Each bit of ``ooooo------'' or ``'
00010---'' holds true.

Counters 96 and 97 are part of module I shown in FIG.
The counters 96 and 97 are counted up in synchronization with the reception clock RCLK of the C85, and the counters 96 and 97 are, for example, two 5N74LS163 manufactured by Texas Instruments Inc. connected in series and used as an 8-bit counter and a 5-bit counter, respectively.

Further, 104 is a transmission means of the present invention.

When the synchronization signal R-F (violation pit) shown in FIG. 5 is input to the R-F terminal, counters 96 and 97 are cleared, and then the counter 96 receives one clock pulse of the RCLK signal shown in FIG. Count up every time,
The output selects address line Ao-A of ROM 98. As is clear from FIG. 7(A), the output 03 of the ROM 98 is when the output of the counter 98 is [1
92] When it becomes lo (the subscript 10 indicates the lO base number), it becomes "1", so the counter 96 is cleared via the NOR gate 102. Therefore counter 96 is 19
Operates as a ternary counter.

RO at the same time! When 03 of 1198 becomes "1", the counter 97 is incremented via the transmission means 104. In other words, the counter 97 operates as a frame counter that counts once every 193 bits, and
Since output 06 of 99 is returned to the clear input via NOR gate 103, counter 97 operates as a 24-base counter as shown in FIG. 7(B).

Figure 8 shows the frame structure and ROM for a transmission speed of 1544 Kbits/sec in the "Technical Reference Materials for Using High-Speed Digital Transmission Services" published by the former Nippon Telegraph and Telephone Public Corporation.
98.99 is a diagram showing the correspondence with 98.99.

When ROM 98.99 is allocated as shown in Fig. 8, each information of F, DNn, IINR, S and 5END is output from ROM 99 as [0] 10+ [
16] 10+ [tel lo.

[20]+o and [22]10, and ROM
When the output of ROM 98 is [192] and O, the specified information can be obtained by setting the respective corresponding outputs of ROM 99 to °'1". Therefore, as the contents of ROM 99, (B) in FIG. 7 is obtained. It will be done.

Similarly, from the timing chart in Figure 5 to the timing chart in Figure 7 (
8) is obtained.

Here, as an example, a 193-decimal counter 96 and a 24-decimal counter 96 are used.
A forward counter 97 is provided to realize the sequence using an independent ROM, but this takes advantage of the periodicity of the frame structure.As a more general-purpose circuit, counters 96 and 9
It goes without saying that it can be configured by combining 7 into one and using a 4632 binary counter and 4632 bytes of ROM.

Furthermore, ROMs 98 and 99 can be used, for example, using Monolithic Memories' PAL (programma
Equivalent functionality can be achieved by replacing it with BLE arraylogic) or the like.

Although FIG. 6 shows only the receiving sequencer, the transmitting sequencer can also be realized using the same circuit configuration, so a description thereof will not be provided.

[Effects of the Invention] As described above, according to the present invention, a data string with a multi-frame structure is input, and the number of bits in one frame and the number of frames in one transmission A1 are counted. The number of bits is converted into a binary signal that indicates whether the signal is valid or invalid, and the counted frame number is converted into a binary signal that indicates the output timing of the flag.
Since the binary signal is converted into a value signal and does not indicate valid or invalid and is transmitted as a synchronization signal to the frame number counting means and the frame signal converting means, the circuit configuration is simple and it can be used with other different frame structures. It is possible to realize a sequence signal generating device that can be easily changed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of an embodiment of the present invention; FIG. 2 is a block diagram showing the overall configuration of an embodiment of the present invention; FIG. 3 is a block diagram showing a detailed configuration of an embodiment of the present invention; 4 is a block diagram showing the detailed configuration of the DDS 60 in FIG. 3, FIG. 5 is a timing chart showing the human output timing of the embodiment of the present invention in FIG. 4, and FIG. 6 is a detailed diagram of the sequencer 86 in FIG. 4. A block diagram showing the configuration of the ROM 98 and I in FIG. 6 is shown in FIG.
A diagram showing the correspondence between the contents of tOM 99 and the output. Figure 8 shows the transmission speed 1 in high-speed digital transmission service.
544 bits per second frame structure and nOM in Figure 6
98 and RO to 199, FIG. 9 is a block diagram showing the configuration of a network system in a conventional example, FIG. 10 is a block diagram showing the configuration of a gateway exchange in a conventional example, and FIG. 11 is a conventional example FIG. 2 is a format diagram showing a frame structure of a signal in FIG. 60...Digital data extraction circuit (DDS), 86.
...Sequencer, 96, 97...Counter, 98, 99...Read-only memory (ROM),
100.101...Latch, 102.103...N0II Kate.

Claims (1)

[Scope of Claims] 1) a) In a gateway exchange that transmits and receives data strings with a multi-frame structure in which one frame is composed of a plurality of bits and one transmission unit is composed of a plurality of the frames, b. ) bit number counting means for inputting the data string and counting the number of bits in the one frame; c) frame number counting means for inputting the data string and counting the number of frames within the one transmission unit; d) bit signal conversion means for converting the count value obtained by the bit number counting means into a binary signal indicating validity or invalidity of the signal; and e) bit signal conversion means for converting the count value obtained by the frame number counting means into a flag output timing. f) transmitting means for transmitting the binary signal obtained from the bit signal converting means to the frame number counting means and the frame signal converting means as a synchronization signal; A sequence signal generating device, comprising: generating a sequence signal using the binary signal indicating validity or invalidity and the binary signal indicating the output timing.