JPS6349389B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a semiconductor integrated circuit device having a memory cell in which information is written by accumulating charges on a floating semiconductor substrate by charge pumping.

Conventionally, the type of semiconductor integrated circuit device shown in FIG. 1 has been known.

In the figure, 1 is a single crystal insulating substrate such as sapphire, 2 is an epitaxially grown p-type silicon semiconductor layer, 3 is a gate insulating film of silicon dioxide, and 4 is a silicon dioxide gate insulating film.
5 is a gate electrode, 5 is an n ⁺ type source region, 6 is an n ⁺ type drain region, and V _G is a power source.

To write information in this device, the source is grounded, a positive voltage V _DD is applied to the drain, and then a positive voltage equal to or higher than the threshold voltage V _th is applied to the gate electrode 4 to close the gate insulating film 3. Semiconductor layer 2 below
A channel is formed on the surface of the gate electrode, and then the gate voltage is suddenly lowered below the threshold voltage V _th . Then,
Due to the charge pumping effect, some of the electrons in the channel enter the semiconductor layer 2, which is in an electrically floating state, and stay there. The voltage applied to the gate electrode 4 is preferably applied repeatedly in a pulsed manner. By the above operation, the floating semiconductor layer 2 is biased negatively with respect to the source region 5. Since the bias at this time is a reverse bias with respect to the p-n junction between the semiconductor layer 2 and the source region 5, the inside of the semiconductor layer 2 is maintained as being negatively biased with respect to the source region 5. . In this state, a back gate bias is applied to the MIS FET and the threshold voltage V _th becomes high.
When the voltage V _DD is applied to the drain and the flowing current is detected, the amount of current is lower than when the floating semiconductor layer 2 is at the same potential as the source region 5, that is, compared to the state before charge pumping. do. Therefore, this indicates that information "1" or "0" has been written.

Further, in order to erase the written information, the negative bias of the semiconductor layer 2 may be removed. Specifically, the reverse leakage current of the p/n junction is increased by increasing the temperature of the semiconductor integrated circuit device or by irradiating it with light. These measures are
Effective in erasing all information stored in the device's memory cell array. In addition, a positive voltage is applied to the gate electrode 4 to collect negative charges in the floating semiconductor layer 2 in the channel region, and then the voltage applied to the gate electrode 4 is slowly lowered to zero. Then, charge pumping does not occur and the electric charge disappears. Further, a high voltage is applied to the drain region 6 or the source region 5 to cause avalanche breakdown,
Information can also be erased by injecting electrons into the semiconductor layer 2. These means are effective for erasing information stored in specific memory cells making up a memory cell array.

Semiconductor integrated circuit devices having memory cells as described above can be manufactured at low cost using the same method as conventional MIS/FETs, and the memory cells can also be rewritten, but there are still improvements to be made. It leaves a lot of room.

The present invention provides a semiconductor integrated circuit device in which not only the memory cell array as described above but also the characteristics of its peripheral circuits are improved, and this will be explained in detail below.

In the memory cell described with reference to FIG. 1, it is necessary that the following condition be satisfied. That is, t≧x _dnax (V _sub =0) ...(1) t: Thickness of the epitaxially grown semiconductor layer x _d : Width of the depletion layer under the gate V _sub : Substrate potential This is the memory shown in Figure 1.・Cell is charged・
This is natural since it utilizes changes in the threshold voltage V _th due to pumping.

On the other hand, in peripheral circuits such as decoders and sense amplifier circuits, it has been found that t<x _dnax (V _sub =0) (2) is desirable for stable logic operation. That is, in the peripheral circuit, it is preferable that the threshold voltage V _th does not change even if the substrate (semiconductor layer) potential changes, so the above conditions need to be satisfied as a matter of course, and these will be explained in more detail. do.

As is well known, the threshold voltage V _th of the MIS field effect transistor is: V _th = V _FB +2φ _FP −Q _B /C ₀ V _FB : Flat band voltage φ _FP : Fermi band voltage of p-type semiconductor substrate Potential Q _B : Charge per unit area in the depletion layer under the gate C ₀ : k _Sip2 ε ₀ /x _OX k _Sip2 : Relative dielectric constant of SiO _{2 ε 0} : Dielectric constant of vacuum x _OX : Gate oxide film thickness Expressed by the formula.

In the case of a normal bulk MIS field effect transistor, the charge per unit area in the depletion layer under the gate
Q _B is, Q _B = −qN _A・x _jnax q: elementary charge k _S : relative dielectric constant of semiconductor V _SUB : given by the substrate bias voltage between the source and the semiconductor substrate (in short, “Physics and Technology of Semiconductor” by ASGrove
Devices”, John Wiley and Sons, 1967 No. 11
(see “Disability”).

Here, x _dnax , Q _B , and V _th when V _SUB = 0 are
If x _dnax,0 , Q _B,0 , and V _th,0 , then x _dnax,0 <x _dnax |Q _B,0 |<|Q _B |V _th,0 <V _th .

However, in the case of a MIS field effect transistor fabricated on an insulating substrate as shown in Figure 1, when the thickness of the semiconductor substrate (semiconductor layer) is t, the magnitude of t and x _dnax,0 is There are two types of relationships:

(i) When t<x _dnax,p Even if the Si・SiO ₂ interface is inverted, the width of the depletion layer under the gate cannot become larger than t, so Q _B = −qN _A・t, and V _th is constant regardless of V _SUB (in short, "N.Sasaki and R.Togei,
“Effect of Silicon Film Thickness on
"Threshold Voltage of SOS-MOSFETs",
Solid−State Electronics, Vol.22, pp417−
421 (April 1979)'').

(ii) When t>x _dnax,0 When V _SUB = 0, Q _B = −qN _A・x _dnax,0 When V _SUB ≠ 0, Q _B = −qN _A・t (t<x _dnax ) Q _B = -qN _A・x _dnax (t>x _dnax ) By the way, in the memory cell part, in order to read information, V _th must change depending on V _SUB , so the above (ii) ) must be satisfied, and in the peripheral circuit section,
Since it is undesirable for V _th to change, the above (i)
It is preferable if the conditions explained in .

In order to meet both of the above requirements, the semiconductor integrated circuit device of the present invention is designed so that the memory cell array portion of the semiconductor wafer satisfies the condition (1) above, and the other peripheral circuit portions satisfy the condition (2). ensure that the conditions are met. For this purpose, the impurity concentration of the semiconductor layer 2 may be appropriately selected, or the layer thickness may be appropriately selected.

FIG. 2 is a sectional side view of a main part of an integrated circuit device for explaining a specific embodiment of the present invention.

In this embodiment, a p-type silicon semiconductor layer 12 is epitaxially grown on an insulating single crystal substrate 11 made of sapphire or garnet, and a buried thick insulating film 13 (for example,
After that, a gate insulating film 14, a gate electrode 15 of polycrystalline silicon,
An n ⁺ type source region 16, an n ⁺ type drain region 17, etc. are formed, and the following conditions are attached to each part.

Impurity concentration of memory cell partial semiconductor layer 12 2×10 ¹⁶ [cm ^-3 ] Same thickness 1 [μm] Thickness of insulating film 13 1.2 [μm] Depth of source region 16 and drain region 17
Xj = 0.3 [μm] Same formation method As ions are implanted at an energy of 150 [KeV] and a dose of 4×10 ¹⁵ [cm ^-2 ] to form impurities in the peripheral partial semiconductor layer 12 of 1×10 ¹⁵ [cm ^-3 ] Same thickness 0.5 [μm] Depth of source region 16 and drain region 17
Xj = 0.3 [μm] As can be seen from the above explanation, according to the present invention, charge is accumulated in the electrically floating semiconductor layer by charge pumping, and the threshold voltage is
In a semiconductor integrated circuit device having a memory cell that takes advantage of the fact that V _th changes and the current flowing through the channel changes, the semiconductor layer for storing charge is formed thickly in the memory cell array portion, or The impurity concentration is high, and in the peripheral circuitry, the semiconductor layer is formed thin or the impurity concentration is low to suit the operation of the memory cell array. The peripheral circuit portions can also operate stably.

[Brief explanation of drawings]

FIG. 1 is a side cross-sectional view of the main part for explaining a memory cell used in the present invention, and FIG. 2 is a side cross-sectional view of the main part for explaining a specific example of the device. In the figure, 11 is a substrate, 12 is a floating semiconductor layer, 13 is an insulating film, 14 is a gate insulating film, 15 is a gate electrode, 16 is a source region, 17
is the drain region.

Claims (1)

[Claims] 1. A gate electrode is provided on a semiconductor layer formed in an island shape on an insulating substrate via an insulating film, and impurities are introduced into the semiconductor layer portions on both sides to form source/drain regions. A semiconductor element is used as a memory element, and when writing information, information is written by injecting minority carriers into the semiconductor layer of the memory element by charge pumping, and when reading information, the information is written by injecting minority carriers into the semiconductor layer of the memory element, and when reading information, information is written by injecting minority carriers into the semiconductor layer of the memory element, and when reading information, information is written by injecting minority carriers into the semiconductor layer of the memory element. In a semiconductor integrated circuit device that reads written information by detecting a threshold voltage change of a storage element, in the region where the storage element is to be formed, the thickness t of the semiconductor layer and the thickness of this semiconductor layer are The thickness t of the semiconductor layer and the impurity concentration of the semiconductor layer are selected so that the maximum thickness x _dnax of the depletion layer when the potential is equal to the source/drain region of the element satisfies the relationship t≧x _dnax . In addition, in a region where a semiconductor element constituting a peripheral circuit for driving the memory element is to be formed, the thickness of the semiconductor layer is t.
and the semiconductor layer in the peripheral circuit forming region so that the maximum thickness x _dnax of the depletion layer when this semiconductor layer is at the same potential as the source/drain region of the semiconductor element in the peripheral circuit satisfies the relationship t<x _dnax . The thickness of the layer is formed to be thinner than the thickness of the storage element forming region, or
A semiconductor integrated circuit, characterized in that the impurity concentration of the semiconductor layer in contact with the insulating film under the gate electrode of the semiconductor element of the peripheral circuit is lower than the impurity concentration of the semiconductor layer in contact with the insulating film under the gate electrode of the memory element. circuit device.