JPS6349112Y2 - - Google Patents
Info
- Publication number
- JPS6349112Y2 JPS6349112Y2 JP16413282U JP16413282U JPS6349112Y2 JP S6349112 Y2 JPS6349112 Y2 JP S6349112Y2 JP 16413282 U JP16413282 U JP 16413282U JP 16413282 U JP16413282 U JP 16413282U JP S6349112 Y2 JPS6349112 Y2 JP S6349112Y2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- transistor
- resistor
- circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Dc-Dc Converters (AREA)
- Control Of Voltage And Current In General (AREA)
Description
【考案の詳細な説明】
本考案はリンギングチヨークコンバータ
(Ringing chcke Converter)に関するもので特
に入力コンデンサの突入電流を抑制すると共にコ
ンバータ出力の立上り時間を容易に調整し得るコ
ンバータを提供するものである。以下図面を用い
て本考案を詳細に説明する。第1図は本考案の一
実施例回路図で図においてACは交流電源、SW
は電源入切用スイツチ、RFは全波整流器、R1及
びSは並列接続されてなる抵抗及びサイリスタで
直流電源(整流出力間)と入力用コンデンサC1
間に接続され、該コンデンサC1の突入電流を防
止する。次にT1は出力トランスで、その1次巻
線N1はスイツチングトランジスタQ1と直列接続
され、該コンデンサC1の両端(直流出力端)に
接続される。NSはトランスT1の補助巻線で、一
端を前記1次巻線N1の一端子に接続され、他端
をダイオードD1、抵抗R2を介して前記サイリス
タSのゲートGに接続されて、該サイリスタSの
ゲート回略を形成している。NBはベース巻線で
電流制限抵抗R3を介してトランジスタQ1のベー
ス・エミツタ間に接続されている。N2は2次
(出力)巻線D2,C2は出力整流用ダイオード及び
コンデンサ、次にR4,R5は該トランジスタQ1の
起動用分圧回路を形成する抵抗で前記コンデンサ
C1の一端とトランジスタQ1のベース間に接続さ
れる。C3は補助コンデンサで前記抵抗R4,R5の
分圧点と該コンデンサC1の他端間に接続され、
該抵抗R4と共に時定数回路を形成する。なお、
R6は補護用抵抗である。以上で本考案回路を構
成する。上記構成において、スイツチSWが投入
されるとコンデンサC1は抵抗R1により突入電流
を防止され、該抵抗R1により制限されながら充
電を開始する。そこで該コンデンサC1の充電が
完了する以前に起動用分圧回路を介して起動電流
が流れトランジスタQ1が動作を開始すると電源
スイツチSW−抵抗R1−1次巻線N1−トランジ
スタQ1の経路に電流が流れ又補助巻線NSにも該
1次巻線N1と同極性の電圧が生じてサイリスタ
Sにゲート信号を与え、これを導通せしめる結
果、該抵抗R1の両端は該サイリスタSにより短
絡状態になる。従つて該トランジスタQ1のスイ
ツチング動作時に該コンデンサC1には突入電流
が流れて電源スイツチSWの入り切りを頻繁に行
うと突入電流により電源スイツチの劣化及びコン
デンサC1の劣化を来たし、寿命を短くする等の
問題を生じる。このため、従来はサイリスタSの
点弧を遅らせるための遅延信号を外部より導入し
たり或は他の遅延回路を設ける等の方法が採用さ
れていたが、これでは装置が複雑、高価となる難
点がある。然し乍ら本考案によれば簡単な回路を
付加することにより上記の欠点を一挙に解消した
ものである。即ち起動用分圧抵抗R4,R5の一端
に補助コンデンサC3を接続したことによりトラ
ンジスタQ1の抵抗R4,R5を介す起動電流は抵抗
R4及びコンデンサC3の充電時定数(時間)、該コ
ンデンサC3により側路されてこの間トランジス
タQ1の起動が遅延される。このため、抵抗R4及
びコンデンサC3の充電時定数即ちトランジスタ
Q1の動作遅延時間を予め該コンデンサC1が完全
に充電する時間付近に設定すればスイツチング動
作開始時該コンデンサ1は完全な充電状態である
ので該コンデンサC1の突入電流は防止でき、し
かも充電電圧がほぼ一定状態であり、起動時のス
イツチング動作は安定すると同時に突入電流によ
るコンデンサC1の劣化を防止でき、又この充電
時定数を任意設定することによりコンバータの出
力の立上り時期を容易に調整できる。トランジス
タQ1の起動後はトランスT1の作用によりベース
巻線NBを介してベース電流が供給され、トラン
ジスタQ1のコレクタ電流は直線的に増加するが
ベース電流は所定値に制限されるために該トラン
ジスタQ1は飽和に至つた後不導通(CFF)状態
になりそれまでトランスT1に蓄積されたエネル
ギーをダイオードD2及びコンデンサC2を介して
出力VO1を発生する周知の動作を行う。なお、コ
ンデンサC3の充電電荷はトランジスタQ1のオフ
時抵抗R5を介して放電し次の起動動作に備える。
第2図a,bは本考案の他の実施例回路図及びそ
の動作説明図でこの実施例は本考案を多出力用コ
ンバータに適用した例を示すものでサイリスタS
及び抵抗R1より成る突流防止回路を共通にした
他のコンバータユニツトCNVを付加し、又そ
の出力VO2を第1コンバータユニツトの出力電圧
VO1より高い値に設定されている。そして抵抗
R41及び補助コンデンサC31の充電時定数(t=
C31・R41)は第1コンバータの時定数(t=
C3・R4)より長く設定されている。このためス
イツチSWを投入すると第2図bに示すように先
ず時間t1遅延の後、第1コンバータの出力電圧
VO1が立上り、更に時間t2遅延の後第2コンバー
タCNVの出力電圧VO2が立上がる所謂多出力
電源における出力立上りシーケンスが容易に達成
できる利点がある。以上の実施例では、2出力コ
ンバータの例について説明したが出力を更に多出
力形してもよくこの場合コンバータユニツトの
夫々時定数回路の時定数を立上りシーケンスに応
じて設定すればよく、又単位コンバータの容量を
揃えて並列運転することもできる。以上の説明か
ら明らかなように本考案によれば構成簡単にして
コンデンサの突入電流を防止できるので動作が安
定化すると同時にコンデンサ或は他の構成部品を
保護でき更に多出力電源等に適用して各出力段の
立上りシーケンスが容易に達成できる等実用上の
効果は大きい。[Detailed description of the invention] The present invention relates to a ringing chcke converter, and in particular provides a converter that can suppress the rush current of the input capacitor and easily adjust the rise time of the converter output. . The present invention will be explained in detail below using the drawings. Figure 1 is a circuit diagram of one embodiment of this invention. In the figure, AC is an alternating current power supply, and SW
is a power on/off switch, RF is a full-wave rectifier, R1 and S are resistors and thyristors connected in parallel, and are a DC power supply (between the rectified outputs) and an input capacitor C 1
The inrush current of the capacitor C1 is prevented. Next, T1 is an output transformer, the primary winding N1 of which is connected in series with the switching transistor Q1 , and connected to both ends (DC output ends) of the capacitor C1 . NS is an auxiliary winding of the transformer T1 , one end of which is connected to one terminal of the primary winding N1 , and the other end connected to the gate G of the thyristor S via the diode D1 and resistor R2 . , forming the gate circuit of the thyristor S. NB is a base winding connected between the base and emitter of transistor Q1 via current limiting resistor R3 . N2 is a secondary (output) winding D2 , C2 is an output rectifier diode and a capacitor, and R4 and R5 are resistors forming a voltage divider circuit for starting the transistor Q1, and are connected to the capacitor.
Connected between one end of C 1 and the base of transistor Q 1 . C3 is an auxiliary capacitor connected between the voltage dividing point of the resistors R4 and R5 and the other end of the capacitor C1 ,
A time constant circuit is formed together with the resistor R4 . In addition,
R 6 is a supplementary resistor. The circuit of the present invention is configured as described above. In the above configuration, when the switch SW is turned on, the capacitor C1 is prevented from inrush current by the resistor R1 , and starts charging while being limited by the resistor R1 . Therefore, before the charging of the capacitor C 1 is completed, a starting current flows through the starting voltage divider circuit and the transistor Q 1 starts operating, and the power switch SW - resistor R 1 - primary winding N 1 - transistor Q 1 Current flows through the path of the resistor R1, and a voltage with the same polarity as the primary winding N1 is generated in the auxiliary winding NS, giving a gate signal to the thyristor S and making it conductive.As a result, both ends of the resistor R1 Thyristor S causes a short circuit. Therefore, when the transistor Q1 switches, an inrush current flows through the capacitor C1 , and if the power switch SW is turned on and off frequently, the inrush current causes deterioration of the power switch and the capacitor C1 , shortening its life. This may cause problems such as For this reason, conventional methods have been adopted such as introducing a delay signal from the outside to delay the firing of the thyristor S or providing another delay circuit, but this method has the disadvantage of making the device complicated and expensive. There is. However, according to the present invention, the above-mentioned drawbacks are solved at once by adding a simple circuit. In other words, by connecting the auxiliary capacitor C 3 to one end of the starting voltage dividing resistors R 4 and R 5 , the starting current flowing through the resistors R 4 and R 5 of the transistor Q 1 is reduced by the resistance.
The charging time constant (in time) of R 4 and capacitor C 3 is bypassed by capacitor C 3 during which activation of transistor Q 1 is delayed. Therefore, the charging time constant of resistor R 4 and capacitor C 3 , i.e. the transistor
If the operation delay time of Q 1 is set in advance around the time when the capacitor C 1 is fully charged, the capacitor 1 will be fully charged when the switching operation starts, so inrush current of the capacitor C 1 can be prevented. Since the charging voltage is almost constant, the switching operation at startup is stable, and at the same time, it is possible to prevent deterioration of capacitor C1 due to inrush current.Also, by setting this charging time constant arbitrarily, the rise timing of the converter output can be easily adjusted. Can be adjusted. After starting the transistor Q 1 , the base current is supplied through the base winding NB due to the action of the transformer T 1 , and the collector current of the transistor Q 1 increases linearly, but the base current is limited to a predetermined value. After the transistor Q 1 reaches saturation, it becomes non-conducting (CFF) and performs the well-known operation of transferring the energy previously stored in the transformer T 1 through the diode D 2 and the capacitor C 2 to generate an output VO 1 . . Note that the charge in the capacitor C 3 is discharged through the resistor R 5 when the transistor Q 1 is turned off to prepare for the next startup operation.
Figures 2a and 2b are circuit diagrams and explanatory diagrams of other embodiments of the present invention. This embodiment shows an example in which the present invention is applied to a multi-output converter.
Another converter unit CNV having a common rush current prevention circuit consisting of a resistor R1 and a resistor R1 is added, and its output VO2 is set to the output voltage of the first converter unit.
VO is set to a value higher than 1 . and resistance
Charging time constant of R41 and auxiliary capacitor C31 (t=
C31・R41) is the time constant of the first converter (t=
C3/R4) is set longer. Therefore, when the switch SW is turned on, as shown in Figure 2b, after a delay of time t1 , the output voltage of the first converter is
There is an advantage that an output rise sequence in a so-called multi-output power supply in which VO 1 rises and, after a delay of time t 2 , the output voltage VO 2 of the second converter CNV rises can be easily achieved. In the above embodiments, an example of a two-output converter has been explained, but the output may be even more multi-output. It is also possible to run the converters in parallel by matching their capacities. As is clear from the above explanation, the present invention has a simple structure and can prevent inrush current in the capacitor, thereby stabilizing the operation and protecting the capacitor or other components.Furthermore, it can be applied to multi-output power supplies, etc. This has great practical effects, such as the ability to easily achieve the rising sequence of each output stage.
第1図、第2図は本考案の一実施例回路図であ
る。図においてACは交流電源、SWは電源スイ
ツチ、RF1は全波整流器、Sはサイリスタ、R1,
R2,R3,R4,R5,R6,R31,R41,R51,R61は抵
抗、T1,T2は出力トランス、N1,N2,NB,
NSは1次巻線、2次巻線ベース巻線及び補助巻
線、Q1,Q11はスイツチングトランジスタ、D1,
D2,D21は整流用ダイオード、C1,C11,C2,C3,
C31はコンデンサ、VO1,VO2は出力電圧、CNV
はコンバータユニツトである。
1 and 2 are circuit diagrams of one embodiment of the present invention. In the figure, AC is an alternating current power supply, SW is a power switch, RF 1 is a full-wave rectifier, S is a thyristor, R 1 ,
R 2 , R 3 , R 4 , R 5 , R 6 , R 31 , R 41 , R 51 , R 61 are resistors, T 1 , T 2 are output transformers, N 1 , N 2 , NB,
NS is the primary winding, secondary winding base winding and auxiliary winding, Q 1 , Q 11 are switching transistors, D 1 ,
D 2 , D 21 are rectifier diodes, C 1 , C 11 , C 2 , C 3 ,
C 31 is the capacitor, VO 1 and VO 2 are the output voltage, CNV
is a converter unit.
Claims (1)
介してコンデンサを接続すると共に該コンデンサ
端子間に出力トランスの1次巻線及び変換用トラ
ンジスタを直列接続してなるリンギングチヨーク
コンバータにおいて、該コンデンサの一端と前記
トランジスタのベース間に該トランジスタ起動用
抵抗分圧回路を接続し、又前記分圧回路の分圧点
と該コンデンサの他端間に第2コンデンサを接続
して前記抵抗と共に時定数回路を形成し前記時定
数回路に該トランジスタの起動電流を側路せしめ
て該トランジスタの起動を前記時定数時間遅延せ
しめて前記コンバータ出力の立上りを制御するよ
うにしたことを特徴とするリンギングチヨークコ
ンバータ。 In a ringing chain converter, in which a capacitor is connected between DC power sources through a parallel circuit of a resistor and a thyristor, and a primary winding of an output transformer and a conversion transistor are connected in series between terminals of the capacitor, one end of the capacitor A resistor voltage divider circuit for starting the transistor is connected between the base of the voltage divider circuit and the base of the transistor, and a second capacitor is connected between the voltage divider point of the voltage divider circuit and the other end of the capacitor to form a time constant circuit together with the resistor. A ringing-choke converter, characterized in that the start-up current of the transistor is bypassed through the time constant circuit to delay the start-up of the transistor by the time constant period, thereby controlling the rise of the converter output.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16413282U JPS5969686U (en) | 1982-10-29 | 1982-10-29 | Ringing choke converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16413282U JPS5969686U (en) | 1982-10-29 | 1982-10-29 | Ringing choke converter |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5969686U JPS5969686U (en) | 1984-05-11 |
JPS6349112Y2 true JPS6349112Y2 (en) | 1988-12-16 |
Family
ID=30359927
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16413282U Granted JPS5969686U (en) | 1982-10-29 | 1982-10-29 | Ringing choke converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5969686U (en) |
-
1982
- 1982-10-29 JP JP16413282U patent/JPS5969686U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5969686U (en) | 1984-05-11 |
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