JPS6346549A - Debug device - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution together with its easy operation by storing en bloc the using section information on a memory space of a program to be debugged into a memory circuit and giving an access to this memory circuit to read out the using section information. CONSTITUTION:When the using section information is set to all addresses, the programs in a memory 220 and a substitution memory 32 are executed by an emulation CPU 310. In this case, an operator switches an address switching circuit 342 by an address switch signal so that the circuit 342 selects the address given from a CPU 310 and gives it to a using section information memory circuit 340. As a result, an address if outputted from the CPU 310 via an address bus (a) is always applied to the circuit 340 via the circuit 342. The circuit 340 consists of a RAM and therefore the data on a single byte stored in a given address, that is, the using section information is read out of the circuit 340.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a debugging device, and particularly to a debugging device suitable for program development in a microcomputer.

(Conventional technology) For program development on microcomputers, etc.,
Debug equipment is used. This debug device has a special CPU for emulation and has a function of detecting errors in the program. Generally, this type of debugging device is equipped with replacement RAM memory for debugging, and the memory in the device to be debugged is RO.
Even if the memory is non-rewritable, such as M memory, the contents of this ROM can be copied to the replacement memory and a program can be run, so it can be rewritten as appropriate.

A typical error in a program is an error related to the usage division of memory space. This occurs, for example, when accessing a prohibited memory space or writing into a write-protected memory space.

An example of a conventional general debugging device is shown in FIG. Here, the components on the right side of the dashed-dotted line are the components of this debugging device 100, and the components on the left side are the components of the device 200 to be debugged. The device 200 has a CPU 2 i o and a memory 220, which are connected by an address bus A1, a data bus D1, and a control bus C. However, during debugging, the CPU 210 is removed and the debugging device 100 is connected instead. FIG. 2 shows the state during debugging.

This debug device 100 includes an emulation CPU 1
10 and a replacement memory 120, which are connected to an address bus A1, a data bus d1, and a roll bus C to a controller 1. Further, the address bus a is connected to the address bus A via the address bus buffer 131, the data bus d is connected to the data bus D via the data bus buffer 132, and the control bus C is connected to the control bus buffer 13.
3, the emulation CPU 110 is connected to the control bus C via the memory 2.
20 and replacement memory 120 can be accessed. Since the replacement memory 120 is composed of a RAM, even if the memory 220 is a ROM, its contents are stored in the replacement memory 120 by the emulation CPU 11.
Rewriting is possible by copying through 0.

This debugging device 100 includes a write detection circuit 141, a write error signal generation circuit 142, and a write prohibited area setting in order to detect an error when writing to a write prohibited memory space, that is, a write error. The circuit 143 is reduced. In addition, this debug device 10
0 is an access detection circuit 151, an access error signal generation circuit 152, and an access prohibited area setting circuit 15 in order to detect an error when accessing a prohibited memory space, that is, an access error.
It has 3. Further, this debugging device 100 includes a memory selection detection circuit 161 and a replacement signal generation circuit 1 in order to switch between the memory 220 and the replacement memory 120.
62, replacement area setting circuit 163, and inverter 16
It is equipped with 4.

The operation of this debugging device 100 is as follows.

First, the operator inputs the lie 1-prohibited area setting circuit 143.
Set the address value that should be a write-prohibited area. For example, an address used as a work area by another program is designated as this write-prohibited area. Subsequently, the operator sets an address value to be set as an access-prohibited area in the access-prohibited area setting circuit 153. for example,
Addresses of memory spaces for which no memory devices are actually prepared are designated as access-prohibited areas. Furthermore, the operator sets in the replacement area setting circuit 163 an address value at which the replacement memory 120 should be accessed. As mentioned above, from the IE memory 220 to the replacement memory 12
The address area to be copied to 0 and used is designated as a replacement area.

When each address setting is completed in this way, the emulation cpuiio is used to store the memory 220 or @
The program in replacement memory 120 is executed. At this time, (2) When an access command is output from the simulation CPU 110 via the control bus C, the memory selection detection circuit 161 supplies a memory selection detection signal 165 to the replacement signal generation circuit 162. The replacement signal generation circuit 162 is
When this memory selection detection signal 165 is received, the address given from the emulation cpui1o via the address bus a is compared with the address set in the replacement area setting circuit 163, and it is determined whether the address currently being accessed is a replacement area or not. to judge. And if it is a replacement area, '0'',
If it is not a replacement area, a replacement signal 166 indicating "1n" is generated.

If it is a replacement area, the replacement signal 166 passes through the inverter 164 to activate the replacement memory 120, and
The replacement memory 120 is accessed. If it is not a replacement area, the replacement signal 166 indicates the data bus buffer? 132 is made active, and the memory 220 is accessed. In this way, memory switching is performed as set.

Further, when an access command is output from the emulation cpuiio via the control bus C, the access detection circuit 151 provides an access detection signal 154 to the access error signal generation circuit 152. When the access error signal generating circuit 152 receives this access detection signal 154, the access error signal generating circuit 152 generates the address and the access prohibited area 111 which are given from the CPUIIO via the address bus a.
1 setting circuit 153, determines whether access to the address currently being accessed is prohibited, and generates an access error signal 155 indicating the result. The operator can detect this access error signal 155 and recognize that an access error has occurred.

On the other hand, when the emulation CPL 110 outputs a write command via the control bus C, the write detection circuit 141 supplies a write detection signal 144 to the write error C generation circuit 142. When the write error signal generation circuit '142 receives this write detection signal 144,
The address given from the emulation CPU 110 via the address bus a and the line l-inhibited area il! ! It compares it with the address set in the setting circuit 143, and determines whether the address to which writing is currently being attempted is prohibited or not, and generates a write error signal 145 indicating the result. The operator can detect this write error signal 145 and recognize that a write 1 error has occurred. The write 1~] signal 145 is also applied to the controller 1-roll bus control j71ζ33 to execute the write command. Therefore, it is possible to prevent error rewriting of memory.

(Problems to be Solved by the Invention) However, the conventional debugging device has a problem that the circuit configuration is complicated and the operation by the operator is complicated. That is, as shown in FIG. 2, one stage for detecting write errors, means for detecting access errors, and means for memory selection are each independently provided. Therefore, the A operator must make settings for each means separately. Also, in terms of circuit configuration, each signal generation circuit 142, 152, 162 must be provided with an independent comparator, so
It was getting very complicated. In order to deal with particularly detailed address settings, the comparator must be constructed from a huge number of logic elements. Furthermore, as the size of the memory space increases, the number of logic elements forming the comparator also increases.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a debugging device that has a simple circuit configuration and is easy to operate by an operator.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides a debugging device including: an emulation CPU for debugging a program; a usage classification information storage circuit that stores information indicating the usage classification of memory space used by the program; An address setting circuit generates an address for accessing the usage classification information storage circuit, and either an address generated by the emulation CPU or an address generated by the address setting circuit is selected and sent to the usage classification information storage circuit. an address switching circuit that accesses by giving an address, a data setting circuit that generates data to be written to the accessed address when the usage classification information storage circuit is accessed by an address generated by the address setting circuit, and a usage classification information storage circuit. and a processing circuit that performs the processing necessary for debugging based on the data read from the accessed address when accessed by an address generated by the emulation CPU, simplifying the circuit configuration and facilitating operation. This is what I did.

(Function) In the debugging device according to the present invention, usage classification information regarding the memory space of a program to be debugged is stored all at once in a storage circuit, and the usage classification information is read out by accessing this storage circuit. Therefore, there is no need to provide a number of comparators for verifying addresses as in conventional devices, and the circuit configuration can be simplified and operation can be facilitated.

(Example) The present invention will be explained below based on an actual MPAk shown in the drawings.

FIG. 1 is a block diagram of a debugging device according to an embodiment of the present invention. One point here! The components on the right side of the 4th line are the components of this debugging device 300, and the components on the left side are the components of the device 200 to be debugged. The device 200 is a CP
It has an LI 210 and a memory 220, which are connected by an address bus A1, a data bus D1, and a control bus C. However, when debugging, the CPU210
is removed, and a debug device 300 is connected in its place. FIG. 1 shows the state during debugging.

This debugging device fW300 is an emulation CPU
310 and a replacement memory 320, which are connected by an address bus A1, a data bus d1, and a control bus C. Further, the address bus a is connected to the address bus A via the address bus buffer 331, the data bus d is connected to the data bus D via the data bus buffer 332, and the control bus C is connected to the control bus buffer 33.
3, the emulation CPU 310 is connected to the control bus C via the memory 2.
20 and replacement memory 320 can be accessed. Since the replacement memory 320 is composed of a RAM, even if the memory 220 is a ROM, its contents are stored in the replacement memory 320 by the emulation CPU 31.
Rewriting is possible by copying through 0.

This debugging device 300 includes a usage classification information storage circuit 340 that stores information indicating the usage classification of memory space used by a program to be debugged, and an address that generates an address for accessing this usage classification information storage circuit 340. Setting circuit 341 and emulation CPU
Address generated at 310 or address setting circuit 3
an address switching circuit 342 that selects one of the addresses generated in step 41 and supplies it to the usage classification information storage circuit 340 for access; and a usage classification information storage circuit 340.
The data setting circuit 343 generates data to be written to the accessed address when accessed by the address generated by the address setting circuit 341. Furthermore, this debugging device 300 includes an operation detection circuit 351 that detects a predetermined operation in response to a command output from the emulation CPU 310 via the control bus C, and an output from the usage classification information storage circuit 340 and an operation detection circuit 351. and an operation comparison circuit 352 that generates a predetermined error signal based on the detection signal.

The operation of this debugging device 300 is as follows.

First, the operator uses the address switching signal 344 to switch the address switching circuit 342 to select the address from the address setting circuit 341 and apply it to the usage classification information storage circuit 340. If such switching is performed, since the usage classification information storage circuit 340 is composed of RAM, the operator can set the address in the usage classification information storage circuit 340 specified by the address setting circuit 341 using the data setting circuit 343. Data can be written. The address space of the usage classification information storage circuit 340 is mapped to the address space of the device 200 to be debugged. When making the most detailed correspondence between addresses, it is sufficient to make a one-to-one correspondence. That is, memory 2
Classification information storage circuit 340 uses exactly the same storage capacity as 20.
It is secured within. If you want to reduce the storage capacity of the usage classification information storage circuit 340, 1:16.1:2
56, etc., so that only the upper addresses have a one-to-one correspondence. Now, for the sake of explanation,
Let us consider a case where the two have a complete one-to-one correspondence. Therefore, any 1-byte address in memory 220 corresponds to a 1-byte address in usage classification information storage circuit 340. The operator stores usage classification information indicating the usage classification of the address space of the memory 220 in the usage classification information storage circuit 3.
40 will be stored.

In this embodiment, the usage classification information includes: ■ Information indicating whether the address is write-prohibited, ■ Information indicating whether the address is access-prohibited, and ■ Information indicating whether the address is allocated to the replacement memory 320 during emulation. It consists of three pieces of information: information indicating whether it is a memory space allocated to the memory 220 or a memory space allocated to the memory 220. Each of these pieces of information can be expressed with 1 bit, so a total of 3 bits of memory is sufficient, but since access is generally performed in 1-byte units, it is not necessary to record the usage classification information for one address. 1 byte of memory is used. In this way, for example, in order to obtain usage classification information for address X of memory 220, it is sufficient to read data at address X of usage classification information storage circuit 340. In addition, in order to set such usage classification information, the operator does not need to set it for each address.
For example, three pieces of information can be set all at once over a certain memory area, such as: 1000 to 2000 are (1) write-prohibited, (2) accessible, and (2) an area allocated to the replacement memory 320. Therefore, the operator's effort is reduced compared to conventional devices.

When the setting of usage classification information for all addresses is completed as described above, the program in the memory 220 or the replacement memory 320 is executed by the emulation CPU 310. At this time, the operator switches the address switching circuit 342 to select the address from the emulation CPU 310 and apply it to the usage classification information storage circuit 340 using the address switching signal 344. Therefore, when an address is output from the emulation CPU 3107) 1 via the address bus a, this address is always given to the usage classification information storage circuit 340 via the address switching circuit 342. As mentioned above, since the usage classification information storage circuit 340 is constituted by a RAM, 1 byte of data stored at a given address, ie, usage classification information, is read out.

Of this 1-byte read data, valid data is as described above: ■ Inhibit signal 353 indicating whether writing is prohibited, ■ Access prohibition signal 354 indicating whether access is prohibited, ■ Memory replacement signal 353 Memory replacement signal 3 indicating presence/absence
There are only 55 3 bits. Of these, the write prohibition signal 353 and the access prohibition signal @354 are sent to the operation comparison circuit 3.
52. Further, the memory replacement signal 355 is applied to the data bus buffer 332 and is also applied to the replacement memory 320 via an inverter 356. If the address currently being accessed is replacement gIM, the replacement signal 355 becomes 'O', this replacement signal 355 passes through the inverter 356, activates the replacement memory 320, and the replacement memory 320 is accessed. .If it is not a replacement area, the replacement signal 355 is “1n
, the data bus buffer 332 is activated,
Memory 220 is accessed. In this way, memory switching is performed as set.

On the other hand, when an access command is output from the emulation CPU 310 via the control bus C, the operation detection circuit 351 transfers the access detection signal 357 to the operation comparison circuit 3.
Give to 52. Further, if this access command is a write command, the operation detection circuit 351 provides a write detection signal 358 to the operation comparison circuit 352. Operation comparison circuit 3
52 is an access prohibition signal 354 and an access detection signal 3
57 at the same time, that is, when the address currently being accessed is prohibited from access, an access error signal 359 is generated. The operator can detect the access error signal 359 and know that an access error has occurred.

Further, when the operation comparison circuit 352 receives the write prohibition signal 353 and the write detection signal 358 at the same time, that is, when the address to which writing is currently being performed is write prohibited, the operation comparison circuit 352 generates a fit error signal 360. . The operator can detect the write error signal 360 and recognize that a write error has occurred. Further, this write error signal 360 is also applied to the control bus buffer 333 to prevent execution of the write command. Therefore, erroneous rewriting of the memory can be prevented.

As described above, it will be understood that the debugging device 300 according to the present invention has the same functions as the conventional debugging device 100. However, its circuit configuration is extremely simple. That is, all of the various usage classification information is collectively stored in the usage classification information storage circuit 340 made up of RAM, and this information is read by accessing this RAM, so that address verification is not required as in conventional devices. There is no need for a comparator to do this. Although a comparator is used in the operation comparison circuit 352, the comparison of addresses is not performed here, but only a few bits of data are compared, and this can be realized with a very simple logic circuit.

〔Effect of the invention〕

As described above, according to the present invention, in the debugging device,
The usage classification information regarding the memory space of the program to be debugged is stored in a memory circuit all at once, and this storage circuit is accessed to read the usage classification information, which simplifies the circuit configuration and facilitates operation. can be converted into

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a debugging device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional debugging device. 100... Conventional debugging device, 110... Emulation CPU, 120... Replacement memory, 131
...Address bus buffer F, 132...Data bus buffer, 133...Control bus buffer, 1
41... Write detection circuit, 142... Write error signal generation circuit, 143... Write prohibited area setting circuit,
144...Write detection signal, 145...Write error signal, 151...Access detection circuit, 152...
Access error signal generation circuit, 153... Access prohibited area setting circuit, 154... Access detection signal, 15
5... Access error signal, 161... Memory selection detection circuit, 162... Replacement signal generation circuit, 163...
・Replacement fr4 area setting circuit, 164...Inverter, 1
65... Memory selection detection signal, 166... Replacement signal, 200... Device to be debugged, 210...
・CPU, 220...Memory, 300...Debug device according to the present invention, 310...J, simulation C
P.U. 320... Replacement memory, 331... Address bus buffer, 332... Data bus buffer, 333...
. . . Control bus buffer, 340 . . . Use classification information storage circuit, 341 . . . Address setting circuit, 342
. . . address switching circuit, 343 . . . data setting circuit, 344 . . .-address switching signal, 351 . . . operation detection circuit, 352 .・Access prohibition signal, 355・
...Memory replacement signal, 356...Inverter, 357
...Access detection signal, 358...Write detection signal, 359...Access error signal, 360...Write error signal, A, a...Address bus, C1C...
・Control bus, D, d...Data bus.

Claims (1)

[Claims] 1. An emulation CPU for debugging a program, a usage classification information storage circuit that stores information indicating usage classification of memory space used by the program, and access to the usage classification information storage circuit. an address setting circuit that generates an address for the purpose of the above, and selecting one of the addresses generated by the emulation CPU or the address generated by the address setting circuit and supplying the selected address to the usage classification information storage circuit for access. an address switching circuit, a data setting circuit that generates data to be written to the accessed address when the usage classification information storage circuit is accessed by the address generated by the address setting circuit, and the usage classification information storage circuit. A debugging device comprising: a processing circuit that performs processing necessary for debugging based on data read from the accessed address when accessed by the address generated by the emulation CPU. 2. The debugging device according to claim 1, wherein the information indicating the usage classification of the memory spaces includes information indicating whether or not writing is prohibited for each memory space. 3. When the processing circuit reads information indicating write inhibition from the usage classification information storage circuit, it generates an error signal to indicate a write error and also performs an operation to prevent the emulation CPU from writing. A debugging device according to claim 2. 4. The debugging device according to claim 1, wherein the information indicating the usage classification of memory spaces includes information indicating whether access to each memory space is prohibited. 5. Claim 4, characterized in that the processing circuit performs an operation of generating an error signal for displaying an access error when the processing circuit reads information indicating access prohibition from the usage classification information storage circuit. Debug equipment as described. 6. The debugging device according to claim 1, further comprising a replacement memory for debugging. 7. For each memory space, whether the information indicating the usage classification of the memory space is the memory space allocated to the replacement memory or the memory space allocated to the memory within the device to be debugged; The debugging device according to claim 6, characterized in that the debugging device includes memory selection information indicating. 8. The processing circuit performs an operation of switching the memory to be accessed by the emulation CPU to a replacement memory or a memory in the device to be debugged, based on the memory selection information read from the usage classification information storage circuit. A debugging device according to claim 7.