JPS6345917U - - Google Patents
Info
- Publication number
- JPS6345917U JPS6345917U JP11283087U JP11283087U JPS6345917U JP S6345917 U JPS6345917 U JP S6345917U JP 11283087 U JP11283087 U JP 11283087U JP 11283087 U JP11283087 U JP 11283087U JP S6345917 U JPS6345917 U JP S6345917U
- Authority
- JP
- Japan
- Prior art keywords
- high dielectric
- solder
- laminated
- dielectric chips
- built
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000006071 cream Substances 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 239000011247 coating layer Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Insulated Conductors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
第1図は本考案の一実施例に従つたコンデンサ
内蔵型積層母線の概念的な一部切欠拡大平面図、
第2図は第1図のX―X線拡大断面図である。
1,2:帯状導体、3:セラミツク板、4:絶
縁性スペーサ、5:半田または半田クリーム、8
:絶縁性コーテイング層。
FIG. 1 is a conceptual partially cutaway enlarged plan view of a laminated bus bar with a built-in capacitor according to an embodiment of the present invention;
FIG. 2 is an enlarged sectional view taken along the line X--X of FIG. 1. 1, 2: Band-shaped conductor, 3: Ceramic plate, 4: Insulating spacer, 5: Solder or solder cream, 8
: Insulating coating layer.
Claims (1)
互間を絶縁して積層し、この積層体の外周を上記
端子を除いて絶縁被覆成形するようにした回路基
板用積層母線において、上記帯状導体相互間の絶
縁材としてセラミツク板からなる高誘電体チツプ
を多数個直接的に介装し、これら各高誘電体チツ
プと上記帯状導体相互間を半田又は半田クリーム
からなる導電部材で接合するように構成したこと
を特徴とするコンデンサ内蔵型積層母線。 In a laminated busbar for a circuit board, in which a plurality of band-shaped conductors each having a protruding terminal are insulated and laminated, and the outer periphery of the laminate is coated with insulation except for the terminals, A large number of high dielectric chips made of ceramic plates are directly interposed as an insulating material, and each of these high dielectric chips and the strip-shaped conductor are connected with a conductive member made of solder or solder cream. A multilayer bus bar with a built-in capacitor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11283087U JPS6345917U (en) | 1987-07-23 | 1987-07-23 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11283087U JPS6345917U (en) | 1987-07-23 | 1987-07-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6345917U true JPS6345917U (en) | 1988-03-28 |
Family
ID=30994073
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11283087U Pending JPS6345917U (en) | 1987-07-23 | 1987-07-23 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6345917U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007096272A (en) * | 2005-09-02 | 2007-04-12 | Sanyo Electric Co Ltd | Electric device and electric circuit |
US8027146B2 (en) | 2005-12-26 | 2011-09-27 | Sanyo Electric Co., Ltd. | Electric circuit device enabling impedance reduction |
-
1987
- 1987-07-23 JP JP11283087U patent/JPS6345917U/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007096272A (en) * | 2005-09-02 | 2007-04-12 | Sanyo Electric Co Ltd | Electric device and electric circuit |
US8027146B2 (en) | 2005-12-26 | 2011-09-27 | Sanyo Electric Co., Ltd. | Electric circuit device enabling impedance reduction |
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