JPS6345818A - Alignment method in semiconductor manufacturing system - Google Patents

Abstract

PURPOSE:To reduce the occupied area of an alignment mark by correctly detecting the alignment mark by changing the interval of the two marks formed in two positions for each layer which requires alignment. CONSTITUTION:Alignment marks A {(11a, 11b), (12a, 12b), ...(15a, 15b)} for automatically aligning each layer with an aligner by using reflected light or diffracted light are formed in two definite positions on a semiconductor substrate 3. The position is detected by using the each position and the distance of the mark A, the center of the segment connecting between the centers of the mark A, etc. In this case, the interval r11, r12... r15 of each mark A is changed for each layer which requires alignment. This enables the correct detection of the mark A and reduces the occupied area of the mark A.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to positioning of semiconductor manufacturing equipment that manufactures semiconductor integrated circuits using an exposure apparatus that automatically aligns each layer using reflected or diffracted light. Regarding the alignment method.

[Conventional technology]

Conventionally, as alignment marks on a semiconductor substrate, one or more alignment marks are used which are formed from different layers depending on the layer to be aligned. Even in different alignment processes, the shape, number, and spacing of the alignment marks used are all the same.

[Problem that the invention seeks to solve]

When alignment is performed using the above-mentioned conventional alignment marks on a semiconductor substrate, the marks used in each alignment process are similar in shape, number, spacing, etc. However, there is a drawback that alignment marks used in other processes may be mistakenly detected.

Additionally, as the number of alignment marks increases as the number of alignment steps increases, the area occupied by the alignment marks increases.
This was a constraint when designing chips and circuit layout.

The purpose of the present invention is to make it possible to detect correct alignment marks, reduce the area occupied by the alignment marks by devising the arrangement of the alignment marks, reduce the size of the chip, and limit the constraints when designing the circuit layout. An object of the present invention is to provide a method for aligning semiconductor manufacturing equipment that can reduce the amount of time required.

[Means for solving problems]

The semiconductor device alignment method of the present invention uses reflected light or diffracted light to form alignment marks at two predetermined locations on a semiconductor substrate for automatically aligning each layer using an exposure device. In an alignment method for semiconductor manufacturing equipment in which position detection is performed using the position and distance of each of the two alignment marks, the center of a line segment connecting the centers of the marks, etc., the two alignment marks is a method for aligning a semiconductor manufacturing apparatus, which is characterized in that marks are formed at different intervals depending on the layers to be aligned.

[Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 3 shows, by way of example, two rectangular alignment marks la, lb arranged a certain distance tfii r t apart. Figure 4 shows alignment marks 1a, 1
This is an alignment waveform detected when positioning is performed using b. Peak 2a is detected from mark la, and peak 2b is detected from mark 1b. And two peaks 2a, 2b
The distance M r 2 is the distance r1 between the two marks la and lb.
It becomes longer or shorter in proportion to. By the way, marks used for alignment between layers are usually formed in different layers depending on the purpose. Here, it is assumed that the marks used for alignment in the gate polycrystalline silicon process are the marks shown in FIG. 3 formed in the LOCOS process. Also, the mark used in the contact process is the third mark formed in the gate polycrystalline silicon process.
Let us use the marks shown in the figure. When actually aligning the contact process, assuming that the distance between the two marks formed in the LOCOS process is the same as the distance between the two marks formed in the gate polycrystalline silicon process, the light irradiation If there is a mark formed by the Locos process in the area where the mark is being searched, it will be detected incorrectly.
Therefore, in the present invention, by changing the distance between the two marks formed in each step, the distance between the two peaks of the alignment waveforms detected respectively can be changed, and the marks can be detected correctly. FIGS. 1 and 2 are plan views showing alignment marks used in five different steps formed on a wafer as an embodiment of the present invention. 1st
The figure is a plan view of the structure formed at an arbitrary location within the chip, and FIG. 2 is a plan view of the structure formed on the scribe line, which is a linear margin for cutting the chip. When arranged as shown in FIG. 2, the chips can be made smaller and restrictions on circuit design can be reduced because there are no alignment marks in the chip. Furthermore, the proportion occupied on the scribe line can be reduced, and the alignment marks can be placed effectively.

Note that the shape of the alignment mark used in the present invention may be any shape such as a circle, square, triangle, star, etc., as long as it does not interfere with alignment. The same applies to the location on the wafer.

〔Effect of the invention〕

As explained above, in the present invention, the alignment marks are formed at two locations, and the spacing between each mark is changed depending on the layers to be aligned. One of the features is that alignment marks can be detected. The second effect is that by devising the placement of alignment marks, it is possible to reduce the area occupied by the alignment marks and reduce constraints when designing chip miniaturization and circuit layout. can give.

[Brief Description of the Drawings] Fig. 1 is a plan view showing the arrangement of alignment marks used in one embodiment of the present invention, and Fig. 2 is a plan view showing the arrangement of alignment marks used in another embodiment of the invention. Plan view shown, 3rd
4 are plan views of unit alignment marks and diagrams showing alignment waveforms detected when alignment is performed, for explaining the principle of the alignment method. la, lb, lla, llb, 12a, 12b. 13a, 13b, 14a, 14b, 15a. 15 b ... Alignment mark, rl, 'll
+ r 12 + r13 + ' 14. '15... Distance of alignment mark, 2a, 2b... Peak of alignment waveform, r2... Distance of peak of alignment waveform, 3... Chip, 4... Scribe line. 1st Tefu・Iwa 2 Ro exchange 3 Concave 4 Fig.

Claims (1)

[Claims] Alignment marks are formed at two predetermined locations on a semiconductor substrate for automatically aligning each layer using an exposure device using reflected light or diffracted light, and each of the two alignment marks is In an alignment method for semiconductor manufacturing equipment that performs position detection using position and distance, or the center of a line segment connecting the centers of marks, the two alignment marks are arranged according to the distance between each layer to be aligned. , a method for aligning semiconductor manufacturing equipment, characterized in that each mark is formed at different intervals.