JPS634342A - Testing instrument for integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an integrated circuit testing device, and in particular, to an input terminal of a composite integrated circuit in which a memory section and a logic section coexist, an algorithmic interface for testing a memory section is installed. The present invention relates to an integrated circuit testing device that selectively or simultaneously supplies serial patterns for pattern trosic portion testing.

[Conventional technology]

The conventional test device includes a plurality of pattern generators 62A, as shown in FIG.

A plurality of controllers 6L4, 61B, 6+(' are provided to independently control the pattern generation of the pattern generators 62E, and the patterns output from each pattern generator 62A, 62B are selected by the generator selector 65, and then tested via the formatter 65. By applying the signal to a predetermined input terminal of the integrated circuit under test in the station 64, patterns can be generated without increasing the frequency of the entire test apparatus.

However, with regard to synchronization between patterns, the above conventional technology only takes into account the least common multiple of the pattern generation frequencies of multiple pins, but does not take into account the generation of synchronous or asynchronous patterns at arbitrary frequencies.

[Problem that the invention seeks to solve]

In the above conventional technology, when multiple pattern frequencies are used on multiple pins, for example, when a high-speed pattern is required on a specific pin such as a clock pin, or when a high-speed serial pattern is required, these and low-speed patterns can be used. There was a problem in that it was difficult to synchronize between the two, and only the least common multiple of frequencies could be synchronized.

An object of the present invention is to provide an integrated circuit testing device that can easily control synchronization between patterns for patterns of any frequency on any pin, and can generate synchronous or asynchronous patterns in any test cycle. Our goal is to provide the following.

[Means for solving problems]

The above purpose is to provide a lock generator that can output multiple clock frequency signals in a programmable manner, and to arbitrarily send those output signals to an algorithmic pattern generation section and a serial pattern generation section provided corresponding to each pin. A clock selector selectively supplies the clock signal, and a clock signal supplied from this clock selector to the serial pattern generator is synchronized with the output pattern data of the algorithmic pattern generator during the period when the synchronization request signal is output. This is achieved by providing a pattern synchronization circuit that supplies the clock signal supplied from the clock selector as it is to the serial pattern generation section during the period when no synchronization request signal is output.

[Effect]

The clock generator outputs clock signals of several types of frequencies to be used in advance to the clock selector according to instructions from the test pattern controller. The clock selector selects and allocates the clock signal used by the serial pattern generator corresponding to each pin and the clock signal used by the algorithmic pattern generator according to instructions from the test pattern controller. A pattern synchronization circuit is provided between the clock selector and the serial pattern generator, and this pattern synchronization circuit determines whether or not to synchronize the output patterns of both pattern generators depending on the presence or absence of a synchronization request.
During the period when the synchronization request signal is output, the input clock signal from the clock selector is changed to a clock signal synchronized with the output pattern data of the algorithmic pattern generator, and when the synchronization request signal is not output, , the input clock signal from the clock selector is input as is to the serial pattern generator and the pattern selector.

The output turn signal of the serial pattern generator and the output pattern data of the algorithmic pattern generator are also input to the pattern selector, and these input signals are selectively or simultaneously selected according to instructions from the test pattern controller. It is output and supplied to the input terminal of the device under test of the test station via the formatter.

Therefore, in some test cycles, patterns can be generated at independent frequencies, and in some test cycles, the algorithmic pattern and the serial pattern can be synchronized, and different patterns can be generated while working cooperatively with each other.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 5. Fig. 1 is a block diagram showing the configuration of the embodiment device;
The figure is a detailed block diagram of the pattern synchronization circuit in Figure 1, Figure 3 is a timing diagram of each part signal in Figure 2, Figure 4 is a diagram explaining a test example of a composite device, and Figure 5 is a diagram of the pattern synchronization circuit in Figure 4. It is a figure which shows the pattern generation example with respect to the test example of a figure.

As shown in FIG. 1, the device of this embodiment includes a clock generator 1, a clock selector 2, an algorithmic pattern generator 3, a pin block 12 installed corresponding to each pin, and a tester. It is composed of a stage stage 10 and a test pattern controller 11. bottle block 1
2 consists of a pattern synchronization circuit 4, a serial pattern memory section 5 including a serial pattern generator, a pattern selector 6, a formatter 7, and a synchronization timing setting section 9, and has the number of blocks equal to the number of pins. . The output of the algorithmic pattern generator 3 is selected and input as a necessary pit pattern by a pattern selector 6 in a common pin block 12. Test pattern controller 11c, designation of generation frequency for clock generator 1, output of clock selector 2? It performs assignments to the algorithmic pattern generator 3 and pin blocks 1 to 9, specifies synchronization timing to the synchronization timing setting section 9, and instructs pattern switching to the formatters 7 to 9. The pattern synchronization circuit 4 in the pin block 12 receives the clock signal f1 input from the clock selector 2 and the synchronization request output from the algorithmic pattern generator 3, as detailed in FIG. According to the state of the control signal CTL, the synchronized clock signal CLK-5 is output to the serial pattern memory section 5. As a control signal for synchronization, in addition to the control signal CTL output from the above-mentioned algorithmic pattern generator, it is also possible to receive a different type of clock signal f2 from the clock selector 2 via the multiplexer 8 and use it. be. Normally, when testing complex devices, the algorithmic pattern for testing the memory section is slower than the serial pattern for testing the logic section consisting of shift registers, so synchronization between the low-speed pattern and the high-speed pattern is required. In this case, the output control signal CT of the algorithmic pattern generator 5
When synchronizing high-speed patterns using L, a clock signal f is used as a control signal for synchronization.

This control function makes it possible to determine whether or not synchronization is required for each test cycle and to perform synchronization at any frequency.

The synchronization timing setting section 9 performs time settings that serve as synchronization conditions necessary for synchronization. The serial pattern memory unit 5 receives the synchronization clock signal C from the pattern synchronization circuit 4.
Receives LK -S as input, creates a memory address,
It functions as a serial pattern generator that generates serial patterns stored in memory in advance. The pattern selector 6 selects a serial pattern and a synchronous clock signal CLK.
-5, Receive six algorithmic patterns as input,
Select one of them and output to format tough.

The formatter 7 detects the rising edge of the waveform of the signal received at the input.
The falling edge is adjusted, and if necessary, the pulse width of the waveform within one cycle is controlled. Test station 10
Then, input each selected test pattern from each bin block 12? and supplies it to the device under test. At the same time, the output results of the device under test are captured.

The pattern synchronization circuit 4, as shown in FIG.
1, 41', a delay circuit 42, and a switch 45.

The latch 41 receives a high-speed clock signal f supplied from the clock selector 2, and the launch 41' receives a synchronization control signal CT output from the algorithmic pattern generator 3.
This is a circuit that temporarily holds or passes L as necessary. The delay circuit 42 receives the clock signal C1l' from the latch 41 and outputs it as a clock signal CLK-D delayed by the time specified by the synchronization timing setting section 9, as shown in FIG. The switch 43 is
The clock signal CLK-D from the delay circuit 42 and the clock signal C1l from the latte 41 are switched according to the state of the synchronization control signal CTL from the launch 41' to generate a serial pattern as the synchronized clock ffi signal CLK-S. It is output to the memory section 5. The pattern data DAT and synchronization control signal CTL output from the algorithmic pattern generator 3 are 1/f as shown in FIG.

If the synchronization clock signal CLK-5 is required 45 hours after the rising edge of the pattern data DAT as a synchronization condition, the switching of the pattern data DAT ( In this case, the synchronous clock signal CLK
By setting the delay time tD in the synchronization timing setting section 9 so that the time at the rising edge of -5 becomes t5,
The desired synchronized clock signal CLK-5 is obtained.

Therefore, the synchronization period or the asynchronous period can be controlled by the switching level of the synchronization control signal CTL from the algorithmic pattern generator 5, and the synchronization control signal C
By programming in such a way that TL switches in the falling direction, it becomes possible to synchronize at any time t5 in any cycle using this synchronization control signal CTL.

In FIG. 2, the control signal CTL dependent on the frequency 13 is used as the synchronization control signal, but as shown in FIG.
By using the signals, it is possible to obtain synchronous and asynchronous signals for each cycle.

FIG. 4 shows an example of a test in a synchronous test or an asynchronous parallel test of a composite device, and FIG. 5 shows an example of test pattern generation in that case. Reference numeral 40 denotes a device under test, which is composed of a RAM section which is a memo section and a SAM section which performs serial access to a logic section. Each part can operate independently or continuously, and the SAM part generally operates at a higher speed. The test is first performed at the individual test frequencies by parallel reading of the RAM and SAM sections, then the
Transfer the data written to the M section to the SAM section trap data, and
Read from part M and perform a continuous operation test. At this time, the control data in the RAM section is transferred to L-4B (D in Figure 6).
AT pattern). Furthermore, read data cannot be guaranteed unless the read clock from the SAM section is synchronized for a time t5 from the timing after data transfer.

In this embodiment, since the serial pattern generation frequency f1 and the generation frequency 13 of the algorithmic pattern generator can be easily assigned to each pin by the clock selector 2, as shown in FIG. While generating addresses and data for the RAM section, the serial pattern clock signal and data are simultaneously generated by SAM.
can occur independently into parts. Furthermore, in the synchronous transfer test, the pattern synchronization circuit 4 can synchronize the algorithmic pattern and the serial pattern data within an arbitrary cycle using the control signal CTL from the algorithmic pattern generator.

Although the synchronization of low-speed signals and high-speed clocks has been described above, it is possible to similarly synchronize high-speed clocks and high-speed signals by switching the synchronization control signals.

〔Effect of the invention〕

As explained above, according to the present invention, algorithmic patterns and serial patterns can be generated. Since each pin can be tested at a different frequency, it can be used for independent and simultaneous testing of the memory and logic parts of composite devices, as well as parallel and simultaneous testing of different types of devices. can be performed in a short time, and synchronization of the algorithmic pattern and serial pattern can be achieved in any cycle in real-time data transfer tests between the memory section and the logic section.
Advanced testing of composite devices can be performed, and testing costs can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of an embodiment of the present invention, FIG. 2 is a detailed block diagram of the pattern synchronization circuit in FIG. 1, FIG. 3 is a timing chart of various signals in FIG. 2, and FIG. 4 5 is a diagram illustrating a test example of a composite device, FIG. 5 is a diagram showing an example of pattern generation for the test example of FIG. 4, and FIG. 6 is a block diagram of a conventional example. １・・・・・・・・・・・・・・・Clock generator 2・
・・・・・・・・・・・・・・・Clock selector 5・・−
・・・・・・・・・・・・Algorithmic pattern generator 4・・・・・・・・・・・・・・・Pattern synchronization circuit 5
・・・－・・・・・・・・・ Serial pattern memory section. 6・・・・・・・・・・・・・・・Pattern selector. 7・・・・・・・・・・・・Formatsuta. 8......Multiplexer. 9......Synchronization timing setting section. 10 ・・・・・・・・・・・・Test station. 11 ・・・・・・・・・Test Hattern Controller. 12 ・・・・・・・・・Pin block. 40 ・・・・・・－・・・Device under test 74
1.41'... Lanotino 42 ...... Delay circuit. 43 ・・・・・・・・・・・・Switcher, °, ゝ, °1 ゛, 2nd agent Patent attorney Masaru Ogawa

Claims (1)

[Claims] 1. An integrated circuit in which an algorithmic pattern for testing a memory part and a serial pattern for testing a logic part are input selectively or simultaneously to a composite integrated circuit in which a memory part and a logic part coexist. In circuit testing equipment, there is a clock generator that programmably outputs clock signals of multiple frequencies, an algorithmic pattern generator that arbitrarily selects those output clock signals, and a serial pattern generator that is provided corresponding to each pin. and a clock selector that supplies the clock signal to the serial pattern generator from the clock selector to the serial pattern generator, and synchronizes the clock signal supplied from the clock selector to the serial pattern generator with the output pattern data of the algorithmic pattern generator during the period when the synchronization request signal is output. An integrated circuit testing apparatus characterized in that a pattern synchronization means is provided for performing synchronization control between the pattern outputs of both of the pattern generation sections as the clock signal. 2. The integrated circuit testing apparatus according to claim 1, characterized in that the synchronization request signal is a synchronization control signal generated in synchronization with the output pattern data of the algorithmic pattern generation section. Integrated circuit testing equipment. 3. In the integrated circuit testing apparatus according to claim 1, a clock output from the clock selector and supplied to the serial pattern generation section and the algorithmic pattern generation section as the synchronization request signal. An integrated circuit testing device characterized by using a clock signal having a frequency different from that of the signal.