JPS6342471B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an encoding circuit that compresses and encodes an image signal such as a facsimile signal at high speed.

Conventional configuration and its problems In order to shorten the transmission time of image signals and to reduce the capacity of memory for storing image information, encoding methods are used that suppress the redundancy of image signals. For example, in a facsimile group device, a modified Huffman (MH) encoding method is employed as a one-dimensional encoding method, and a modified read (MR) encoding method is employed as a two-dimensional encoding method.

The MH encoding method calculates the number of consecutive run lengths of white runs or black runs in the image signal, and calculates the number of consecutive run lengths of white runs or black runs, and divides this into 1728 pixels for every 64 pixels for each white run and black run.
"Make-up code" that encodes every pixel
This is a method of encoding and compressing an arbitrary number of run lengths by combining this and a "terminating code" which is coded by dividing each pixel from 0 to 63.

The MR encoding method calculates the positional information of the changed pixel on the coding line by referring to the positional information of the changed pixel that has already been encoded on the coding line and the positional information of the changed pixel of the previous line that has already been encoded. Types of modes (pass mode, vertical mode, horizontal mode)
In this method, the encoded lines are sequentially encoded.

In addition, a line synchronization signal (EOL signal) is added after each line of encoded data and before the first data of one page, and after the last line of one page, an EOL signal is continuously added as a page end signal.
Add times.

When performing this type of encoding at high speed, instead of converting the code length into serial codes at once each time the code is determined, an intermediate method is used between the block that determines the code and the block that converts it to serial code. There is an encoding method in which a first-in, first-out memory (FIFO) memory, which is a buffer memory, is provided, an instruction code instructing to generate a determined code is written in the FIFO memory, and this instruction code is read out and converted into a serial code. .

In the encoding method using intermediate buffer memory as described above, a code generation instruction code is created up to the last line of one page, and an EOL signal generation instruction code is created to generate an EOL signal six times in a row as the end signal of a page. Even after all code generation instruction codes and EOL signal generation instruction codes have been written to the FIFO, encoding is not completed and the code generation instruction code remains in the FIFO memory, and this amount is variable. It is quantity. Therefore, in order to read out the instruction codes remaining in the FIFO memory, convert them into serial codes, and completely complete the encoding, it is necessary to memorize the number of instruction codes remaining in the FIFO memory. Attempting to grasp this amount using an external circuit has the drawback of increasing the circuit scale and complicating control.

OBJECTS OF THE INVENTION An object of the present invention is to provide an encoding circuit that can easily detect the completion of encoding in an encoding system using an intermediate buffer memory.

Structure of the Invention In order to achieve the above object, the present invention creates an instruction code indicating the end of a page, stores this in an intermediate buffer memory (FIFO), and reads this instruction code from the intermediate buffer memory (FIFO). The configuration is configured to detect the completion of encoding.

DESCRIPTION OF THE EMBODIMENTS FIG. 1 shows an embodiment of the encoding circuit of the present invention. FIG. 2 is a diagram showing the relationship between a page signal, a synchronization signal, and an image signal. In Fig. 2, a is a page signal, b is a synchronization signal indicating synchronization of each line, and c is an image signal.One page's worth of data is sent during the "H" level section of page signal a, and " One line of image data is sent during the H'' level section. Therefore, the image data is sent during the "H" level section of the page signal a and the "H" level section of the synchronization signal b.

In Figure 1, 1 is a change point detection circuit, 2 is a counter, 3 is a control circuit, 4 is a selector, and 5 is a
In the FIFO memory, a change point detection circuit 1 detects a change from a white signal to a black signal or a change from a black signal to a white signal in a binary image signal input in synchronization with a clock. A counter 2 counts the number of continuous bits of the white signal or black signal. When a change in the signal is detected by the change point detection circuit 1, the control circuit 3 selects the value of the counter 2 with the selector 4, and stores information on the number of run lengths of the white signal or the number of run lengths of the black signal in the FIFO memory 5. Write the value of counter 2 and then clear counter 2. When the control circuit 3 detects the end of the line, that is, the "L" level of the synchronizing signal b, it first writes information on whether the run length of the white signal or the number of run lengths of the black signal and the value of the counter 2 to the FIFO memory 5. , then clears the counter 2, also clears the change point detection circuit 1, and prepares for encoding the next line. Thereafter, the selector 4 selects an instruction code that instructs to create an EOL signal, and writes that instruction code into the FIFO memory 5. By repeating this series of operations, the FIFO
The memory 5 sequentially stores the white signal of each line, the run length number of the black signal, and an instruction code for instructing to create an EOL signal. Furthermore, the control circuit 3
When the end of the page, that is, the "L" level of the page signal a is detected, first, information on the number of run lengths of the white signal or the number of run lengths of the black signal and the value of the counter 2 are written to the FIFO memory 5, and then the selector 4 Select an instruction code that instructs to create an EOL signal, write that instruction code to the FIFO memory 5 six times in succession, then selector 4 selects an instruction code that indicates the end of the page, and write the instruction code to the FIFO memory 5.
Write the instruction code to. With the above operation,
The FIFO memory 5 sequentially stores the number of run lengths of the white signal, the number of run lengths of the black signal, the EOL signal generation command code, and the page end command code for each line.

6 is a ROM, 7 is a P/S shift register, 8 is a register, 9 is a clock generation circuit, 10 is a memory, 11 is a page end detection circuit, and ROM 6 is used for the number of run lengths of the white signal and the number of run lengths of the black signal. The corresponding code and its code length, and the code corresponding to the EOL signal generation instruction code (“000000000001” for the MH code) and its code length (code length 12 for the MH code) are stored. The code read from the ROM 6 is temporarily stored in the P/S shift register 7, and the code length read from the ROM 6 is temporarily stored in the register 8. The clock generation circuit 9 generates a clock for the code length stored in the register 8, and
The parallel code stored in the shift register 7 is converted into a serial code and input to the memory 10. Assuming that the FIFO memory 5 stores the number of white signal run lengths, the number of black signal run lengths, the EOL signal generation command code, or the page end command code, the oldest data is read out and stored in the ROM 6. The code is converted into a corresponding code and code length, the code is input to the P/S shift register 7, the code length is input to the register 8, the clock generation circuit 9 generates a clock corresponding to the code length, and the clock is input to the memory 10. After this operation, the FIFO memory 5 is checked, and if data is stored, the oldest data is read out and the same operation is performed. Through the above operations, the code and synchronization (EOL) signal corresponding to the image signal of each line are stored in the memory 10. When the page end detection circuit 11 detects the page end command code, it is known that encoding for one page has already been completed, so the encoding operation can be ended.

Although the above embodiment describes the case of a one-dimensional encoding method, the case of a two-dimensional encoding method, such as MR
It can also be easily applied to the case of encoding methods.

Effects of the Invention The present invention provides the following effects.

Enter the page end command code at the end of one page.
It is only necessary to write to the FIFO memory, and it is easy to detect the completion of encoding.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an encoding circuit according to an embodiment of the present invention, and FIG. 2 is a timing diagram showing the relationship between a page signal, a synchronization signal, and an image signal. 1... Change point detection circuit, 2... Counter, 3...
...Control circuit, 4...Selector, 5...FIFO memory, 6...ROM, 7...P/S shift register, 8...Register, 9...Clock generation circuit,
10...Memory, 11...Page end detection circuit.

Claims (1)

[Claims] 1 Count the run length number of the read image signal, generate an instruction code to create a code corresponding to the counted number, store the instruction codes in the first-in/first-out memory in the order of generation, and An instruction code indicating the end of a page is generated in an encoding circuit such as a modified Huffman (MH) code that sequentially extracts instruction codes from first-in/first-out memory and creates a code corresponding to the instruction code for encoding. First-in the means and its instruction code.
An encoding circuit comprising means for storing in a first-out memory and means for detecting an instruction code indicating the end of the page, so that completion of encoding can be easily detected.