JPS6341025B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a conversion device that extracts a change in capacitance value as a change in the number of pulses.

Generally, the rate of change in capacitance in variable capacitance elements used as sensors for temperature and pressure detection is a few percent.
However, if the change in the capacitance value of the variable capacitance element is directly converted and extracted in correspondence with the number of pulses, the amount of change in the number of output pulses will be small, making it difficult to accurately interpret the change information. It was unsuitable for handling.

An object of the present invention is to provide a capacitance-to-pulse (digital quantity) number conversion device that is highly accurate and capable of high-speed processing.

A conversion device according to the present invention includes: a capacitive element having one end connected to a signal terminal; a means connected to the other end of the capacitive element for charging the capacitive element to a first potential;
a first capacitor having a capacitance value smaller than the capacitor; a second capacitor having a capacitor smaller than the first capacitor;
means for transferring the charge of the capacitive element to the second capacitive means;
means for discharging the charge of the capacitance means, means for discharging the charge of the second capacitance means, and a means for discharging the charge of the second capacitance means; and detecting means, and transfers the electric charge charged in the capacitive element to the first capacitive means an arbitrary number of times, and after discharging, transfers the remaining electric charge of the capacitive element to the second capacitive means. death,
It is characterized in that it discharges and outputs a number of pulses corresponding to the number of times each capacitor means operates.

Further, if the capacitive element is a capacitive element with an unknown value or a variable value, and the first capacitive means and the second capacitive means are of known values, the capacitance value of the capacitive element can be easily measured. .

Further, according to the present invention, the capacitance value of the variable capacitance element,
By converting the difference between predetermined capacitance values into the number of pulses, a conversion device can be obtained that can extract a small change in capacitance as a change in the number of pulses.

Further, according to the present invention, a capacitive element Cx having an unknown capacitance value and a capacitive element Cs having a known capacitance value,
It has a capacitive means having a smaller capacitance value than the two capacitive elements described above, and means for transferring charge from one capacitive element to the other capacitive element, and the amount of charge accumulated in the aforementioned capacitive elements Cx and Cs or A conversion device is obtained in which the sum or difference between the charges accumulated in the two capacitive elements is transferred to the capacitive means, discharged, and extracted as a number of pulses proportional to the charges.

Hereinafter, the present invention will be described in detail using reference examples with reference to the drawings. For convenience of explanation, all transistors shown in each figure are P-channel enhancement type insulated gate field effect transistors (hereinafter referred to as P channel enhancement type insulated gate field effect transistors).
IGFET) As a reference example for explaining the present invention, _FIG. 1 shows the amount of charge accumulated in capacitive elements _C A conversion device is shown that transfers and discharges to _CM and extracts the number of pulses proportional to the amount of charge mentioned above.

In this reference example _, the unknown variable capacitance _element C _X , the known capacitance element C _S , _the capacitance elements _C A level detection capacitive element C _B is used to detect the level.

In addition, charging IGFETQ ₁ is used to charge the capacitances C _X and C _S mentioned above, and
IGFETQ ₂ , IGFETQ ₃ for charging the level detection capacitor C _B , IGFETQ ₄ and capacitor C _M for transferring constant charge from the capacitor C _X and C _S to the counting capacitor C _M
IGFETQ ₅ is provided to discharge a more constant charge.

Of these, IGFETQ ₁ has its gate connected to terminal 1, which is supplied with the control signal φ _S , and its drain connected to a constant voltage.
They are respectively connected to terminals 6 to which V _D is supplied, and their sources are connected to node 2 . IGFETQ ₂ has its source connected to node 2, its gate connected to terminal 9 of clock signal φ ₁ , and its drain connected to output terminal 3 of the conversion circuit. Next, IGFETQ ₃ connects the drain to terminal 6
The gate is connected to the terminal 10 of the clock signal φ ₂ and the source is connected to the output terminal 3. Further, the drain of IGFETQ ₄ is connected to node 2, the gate is connected to terminal 9 of clock signal φ ₁ , and the source is connected to node 4. IGFETQ ₅ has its drain connected to node 4, its gate connected to terminal 10 of clock signal φ ₂ , and its source connected to terminal 5. In this reference example, terminal 5 is grounded.

Further, one terminal of the capacitive element C _X is connected to the node 2, and the other terminal is connected to the terminal 7 to which the control signal φ _A is supplied. Further, one terminal of the capacitive element C _S is connected to the node 2, and the other terminal is connected to the terminal 8 to which the control signal φ _B is supplied. capacitive element
One terminal of C _B is connected to terminal 9 and the other terminal to output terminal 3. Further, one terminal of the capacitive element _CM is connected to the node 4, and the other terminal is grounded. Here, the signals φ _S , φ ₁ , φ ₂ take the ground potential and the level of the power supply voltage V _D , and the signals φ _A , φ _B
takes a potential whose absolute value is greater than or equal to the ground potential (V _D −V _P ). (V _P is the pinch-off voltage of the IGFET) Next, the operation of this reference example will be explained. Initially, terminal 6 has a potential of V _D , and terminals 1, 3, 7, 8,
It is assumed that nodes 9 and 10 and nodes 2 and 4 are at ground potential. From this state, when the control signal φ _S becomes a low level potential -V _D , IGFETQ ₁ becomes conductive and node 2
The capacitive elements C _X and C _S connected to the potential −(V _D −
V _P ) is charged. Subsequently, when the signal φ _S becomes high level (ground level), IGFETQ ₁ becomes non-conductive. Next, signals φ _A and φ _B are at low level −(V _D −
V _P ), the potential at node 2 is -2 (V _D −V _P )
to move to. In this state, when the clock signals φ ₁ and φ ₂ alternately become low level (−V _D ), the capacitive element _CM connected to node 4 is charged and discharged between −(V _D −V _P ) and the ground potential. As the process is repeated, the potential at node 2 becomes higher. When the potential at node 2 becomes higher than -(V _D - V _P ) and signal φ ₁ becomes low level, IGFET Q ₂ becomes conductive and the charge accumulated in capacitive element C _B is discharged.
When the signal _φ1 returns to high level, the potential of output terminal 3 changes from low level to high level, and the capacitive element
An output indicating the end of discharging the charges accumulated in C _X and C _S can be detected. _{Counting the number of discharges N _ _ _ M} + α can be expressed as (1). (α is the correction number) Next, the initial state of the circuit shown in the reference example in Figure 1 is the same as the previous case, except that terminal 8 is not connected anywhere or is connected to an arbitrary constant voltage source. , the same circuit operation as in the above example is performed except for the terminal 8, and the number of discharges _NX is counted, it can be expressed as _NX = _CX / _CM +α (2). Furthermore, if the same operation is performed by replacing terminals 7 and 8, the number of discharges can be expressed as N _S =C _S /C _M +α (3). Furthermore, as an initial state, terminal 6 is at potential -V _D , and terminals 1, 3, 7, 9
and 10 and nodes 2 and 4 are at ground potential,
It is assumed that the terminal 8 is at a potential of -(V _D -V _P ). In this state, the control signal φ _S is at a low level potential −V _D
Then, IGFETQ ₁ becomes conductive and the capacitive elements C _X and C _S
The node 2 to which is connected becomes -(V _D -V _P ).
Subsequently, when the signal φ _S becomes high level, IGFETQ ₁ becomes non-conductive. Next, the signal φ _A is set to the potential −(V _D −V _P ), and the signal φ _B is set to the ground potential. In this state, when the clocks φ ₁ and φ ₂ alternately become low level, the capacitive element _CM connected to node 4 repeats charging and discharging between −(V _D −V _P ) and the ground potential, and the potential of node 2 decreases. becomes higher. The number of discharges N until the potential of node 2 becomes higher than -(V _D -V _P ) and a discharge end signal is output to output terminal 3 is N = (C _X - C _S )/C _M + α ...... It is expressed as (4). Based on the circuit operation described above, the capacitance value of an unknown capacitive element can be measured by comparing it with the capacitance value of a known capacitive element. Furthermore, by counting the _difference between _C Furthermore, it is smaller than the known capacity C _S and has a counting capacity.
By connecting circuits containing a known _capacitive element C _{K larger} than C _M in _parallel , calculate N _K = ₍ C Even if _X has a large capacity, it can be easily obtained. In this way, equation (1) or
Using formula (5) arbitrarily, the number of pulses corresponding to the capacitance value of _{the capacitor C} . In addition, even if the capacity C _S is not present, the capacity
It is also understandable to find C _X based on C _M. However, since such a conversion device has only one capacitive element that discharges charge from _the capacitive elements _C has reached its limit.

Next, a first embodiment of the present invention will be described with reference to FIG. IGFETQ ₁₁ has its gate connected to terminal 11 to which control signal φ _S is supplied, and its drain connected to constant voltage V _D
A source is connected to the node 12 at a terminal 16 to which the voltage is supplied. The IGFETQ ₁₂ has its source connected to the node 12, its gate connected to the terminal 18 of the clock signal _φ1 , and its drain connected to the output terminal 13 of the conversion circuit. next
The IGFETQ ₁₃ has its drain connected to the constant voltage V _D terminal 19, its gate connected to the clock signal φ ₂ terminal 20, and its source connected to the output terminal 13. Also
The drain of IGFETQ ₁₄ is connected to node 12, the gate is connected to the terminal 18 mentioned above, and the source is connected to node 14.
The IGFETQ ₁₅ has its drain connected to the node 14, its gate connected to the aforementioned terminal 20, and its source grounded.
Further, the IGFETQ ₁₆ has its drain connected to the node 12, its gate connected to the control signal φ _t terminal 21, and its source connected to the node 15. The IGFETQ ₁₇ has its drain connected to the node 15, its gate connected to the control signal φ _u terminal 22, and its source grounded. Further, one terminal of the capacitive element C _X is connected to the node 12, and the other terminal is connected to the terminal 17 to which the control signal φ _A is supplied. capacitive element
One terminal of C _B is connected to the terminal 18, and the other terminal is connected to the output terminal 13. Further, one terminal of the capacitive element _CM is connected to the node 14, and the other terminal is grounded. Further, one terminal of a capacitive element C _N having a larger capacitance value than the capacitive element C _M is connected to the node 15,
The other terminal is grounded. The level of the power supply voltage control signal is the same as the reference example shown in FIG. 1, and the control signals φ _t and φ _u are the same as φ ₁ and φ ₂ , respectively.
Initially, the potential of terminals 16 and 19 is -V _D , and terminals 11, 13, 17, 18, 20, 21 and 2
2 and nodes 12, 14 and 15 are assumed to be at ground potential.

When the control signal φ _S becomes low level from this state,
IGFETQ ₁₁ becomes _{conductive and the capacitive} element _C

Next, when the potential of signal φ _A becomes −(V _D −V _P ),
The potential at node 12 shifts to -2 (-V _D -V _P ).
After that, the signals φ _t and φ _u alternately go to low level _n times, and after discharging the charge accumulated in _{the capacitive} element _C
φ _u goes to high level, then signals φ ₁ and φ ₂ alternately go to low level m times, and when capacitor C _M discharges the charge accumulated in capacitor C _X , the potential at node 12 becomes -
(V _D −V _P ) and a signal indicating the end of discharge is output to the output terminal 13, then the value of the capacitance C _X is C _X = mC _M + nC _N + β (6). (β is a correction constant) Here, the detection accuracy can be improved by making the value of C _N different from C _M.
Therefore, the known capacitive elements C _M , C _N and the number of discharges m,
The conversion speed can be shortened by appropriately setting n.

Next, a second embodiment of the present invention will be shown with reference to FIG. This is similar to the embodiment shown in Figure 2.
IGFETQ ₁₆ , Q ₁₇ and capacitive element C _N to IGFETQ ₁₈
The drain of IGFETQ ₁₈ is connected to node 14, the gate is connected to terminal 21 where signal φ _t is input, and one terminal of capacitive element _CN is connected to the source of IGFETQ _{18 .} and ground the other terminal. If the potential of the control signal φ _t is -V _D and the IGFETQ ₁₈ is in a conductive state, the amount of charge discharged when the signals φ ₁ and φ ₂ alternately become low level is (C _M +C _N ) (V _D −
V _P ) and if IGFETQ ₁₈ is non-conducting, then C _M (V _D −V _P )
It is. Therefore, assuming that φ _t is low level n times and φ ₁ and φ ₂ are alternately low level m times, the value of C _X can be expressed by equation (5). In this way the first
Similar to the embodiment, the conversion time can be shortened.

The above is P channel enhancement type MOS
-FET has been described, but the present invention is not limited to this, and can be applied not only to enhancement type IGFETs but also to depletion type IGFETs by appropriately selecting the substrate bias voltage. Furthermore, the first and second embodiments can be used individually as well as in combination with the reference example described above.

Furthermore, the present invention is not limited to a conversion device that converts a capacitance value into a pulse number, but is, for example, presented in Paper No. 451 of the 1971 National Conference of the Institute of Electronics and Communication Engineers, "AD conversion circuit as an analog memory input/output circuit". The conversion speed of an AD converter can be increased by applying the proposed circuit to a conversion circuit that converts an analog quantity and a digital quantity by transferring charge between at least two capacitive elements.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a reference example for explaining the present invention, Fig. 2 is a circuit diagram showing a first embodiment of the invention, and Fig. 3 is a circuit diagram showing a second embodiment of the invention. It is a diagram. Explanation of symbols, Q ₁ to Q ₁₈ ... P channel enhancement type IGFET, C _X , C _S , C _B , C _M , C _N ...
Capacitive element, φ ₁ , φ ₂ , φ _S , φ _A , φ _B , φ _t ... Control signal terminal, V _D ... Constant voltage source, 1 to 22 ... Nodes and terminals of the conversion circuit.

Claims (1)

[Claims] 1. A capacitive element having one end connected to a signal terminal, a means connected to the other end of the capacitive element for charging the capacitive element to a first potential, and a capacitance value smaller than that of the capacitive element. a first capacitive means having a capacitance value smaller than that of the first capacitive means; a means for transferring the electric charge of the capacitive element to the first capacitive means; means for transferring electric charge to the second capacitive means; means for discharging the electric charge of the first capacitive means; means for discharging the electric charge of the second capacitive means; means for detecting a change to a second potential having an absolute value smaller than the first potential, and after transferring the electric charge charged in the capacitive element to the first capacitive means an arbitrary number of times and discharging it. . A conversion circuit characterized in that the remaining charge of the capacitive element is transferred to the second capacitive means, discharged, and outputs a number of pulses corresponding to the number of times each capacitive means operates. 2. The conversion device according to claim 1, wherein the capacitive element has an unknown capacitance value, and the first and second capacitive means have known capacitance values.