JPS6340954A - Memory device - Google Patents

Abstract

PURPOSE:To improve the use rate of a memory bank and a data bus by constituting the titled device so that write and read-out operations can be executed to the respective memory banks of two memory units by request of once from a processor. CONSTITUTION:When the request of read-out to an R0 address is received in a double access by an interface part 1 in a timing 1, a read-out processing of (R0+1) address=R1 address is executed continuously after the R0 address. The request is sent out a memory unit 2. Subsequently, in a timing 2, the value of an address register 10 is set to an address register 25, and the read-out of the R0 address is started to a bank 24-0. Also, in the timing 2, a value 1 is set to a double access mode register 30, as well, of a memory unit 3, and in the next timing 3, the read-out of the R1 address is executed to a bank 34-0. That is to say, since the R0 address and the R1 address being the next address are read out continuously in the timing 1, the use rate of a memory bank and a data bus can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION 1. Summary of the Invention The present invention relates to a storage device, and more particularly to a storage device in an information processing system.

BACKGROUND ART Conventionally, a storage device in an information processing system has independent read data lines and write data lines as an interface, but operation instructions and request address information for this storage device are shared between reading and writing. Generally, reading and writing are not performed at the same time, and only the reading or writing operation is instructed.

In addition, in order to shorten the apparent cycle time in conventional storage devices, the memory is divided into several units (usually called banks) that can operate independently, and banks are assigned to addresses, and the memory is contiguous. Many of the addresses used here can be accessed every machine cycle using interleaving techniques. In this case, several times this access width ~
In order to access a block several tens of times larger, it is common to access this storage device while updating the address information every machine cycle.

In such conventional storage device access, the interface for operation instructions and address information is occupied by a series of operations, so the write data bus is not used during a read operation, and conversely, the write data bus is not used during a write operation. Since the read data bus is not used, the data bus is used inefficiently, and therefore the throughput of this storage device is poor.

OBJECTS OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the conventional devices, and an object of the present invention is to provide a storage device that can improve the usage efficiency of memory banks and data buses, and improve throughput.

Structure of the Invention A storage device according to the present invention is provided with a device comprising an interface section for a processing device and a plurality of memory units, and a plurality of memory units having addresses assigned according to the order of the memory units. A memory bank and a selection means for selecting and outputting one of the address information and control information of the preceding memory unit and the address information and control information from the interface section are provided in each of the memory units, and the interface section write and read operations with respect to the memory bank of one of the memory units and the memory bank of the other memory unit in response to input of address information and control information from and input of a double access control signal; It is characterized in that it performs the following.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, one embodiment of the present invention is comprised of an interface section 1 with a processing device (not shown) and memory units 2-5.

In the interface section 1, the address register 10 sets the address sent from the signal line 111,
It is sent out from signal lines 100 and 101. The request register 11 sets a request signal from a signal line 112, and the double access mode register 12 sets a write request signal from a signal line 114 (a write operation is performed when this bit has a value of "1").

The write data register 14 sets the corrupt data sent from the signal line 115 and sends it from the signal line 105 to each memory module. The read data register 15 has signal lines 215, 315, 415,
The data read from each memory module sent from 515 is set and sent from signal line 116 to the processing device.

The decoder 16 generates a request signal for each memory unit 2 to 5 using the lower two bits of the address from the signal line 111 and the request signal from the signal line 102, and sends a signal w.
The signals are sent from A106 to A109 to memory units 2 to 5, respectively.

On the other hand, in the memory unit 2, the write data register 22 sets the contents of the register 14 sent from the signal line 105. Double access mode register 20 sets the contents of register 12 sent from signal line 103, and the output of register 20 is sent to AND circuit 29-0 via signal line 200. The AND circuit 29-0 combines the output of the request register 57-1 of the memory unit 5 sent from the signal line 510 (the request signal of the memory unit 5 is set in the register 57-1) and the value of the register 20. The logical product is calculated and sent from the signal line 203 as a double access request signal.

The selector 23-0 receives the contents of the address register 10 except for the lower two bits via the signal line 100, and the signal line 50
7 inputs the contents of the address register 55 of the memory unit 5, and the value from the signal line 203 is "0".
When the value from the signal @203 is "1", the signal line 507 is selected, and the signal line 2 is selected.
04 to the address register 25. The address register 25 sets the output of the selector 23-0 from the signal line 204, the lower two bits of this output are sent to the bank control circuit 26 via the signal line 208, and the output from the selector 23-0 is sent via the signal line 207. Bank 24-
0 to 24-3 and to memory unit 3.

The contents of the write request register 13 are input to the selector 23-1 through a signal line 104, and the contents of the write request register 51 of the memory unit 5 are input through a signal line 505. The selector 23-1 selects the signal line 104 when the value from the signal line 203 is "0" and selects the signal line 505 when the value is "1", and sends the signal to the write request register 21 via the signal line 201. Write request register 2
1 sets the output of the selector 23-1, and the signal line 205
A write request signal is sent to the bank control circuit 26 and the selector 33-1 of the memory unit 3.

The double access request register 27-0 is a register that indicates that the request to the memory unit 2 is a double access request, and the output of the AND circuit 29-0 is input through the signal line 203, and the output of the AND circuit 29-0 is input to the OR circuit 29-1. It is output via the signal line 216. Request register 2
7-1 is a register indicating a request from the decoder 16 to the memory unit 2, which is input from the decoder 16 through the signal line 106, and is input through the signal line 210 to the OR circuit 29-1 and the AND circuit 39 of the memory unit 3.
Output for -0.

OR circuit 29-1 is double access request register 2
7-O and the request register 27-1 are logically summed and outputted to the bank control circuit 26 via the signal line 206. In the bank control circuit 26, the signal line 208
Banks 24-0 to 24- are determined based on the lower two bits of the address register 25 (indicating the bank address) sent from the address register 25, the write request signal sent from the signal 1i 1205, and the request signal sent from the signal line 206. 3
and generates control signals for the respective banks 24-0 to 24-2.
4-3 from signal lines 209-0 to 209-3.

The banks 24-θ to 24-3 are memory banks that can each operate independently, and common write data is supplied from the write data register 22 through a signal line 202. Further, a common intra-bank address is supplied from the address register 25 via a signal line 207 .

In the bank control circuit 26, for example, register 2
When the value of the lower two bits of 5 is "00", the value of the request register 27-1 is "1", and the write request register 21
If the value of is rOJ, signal line 209-0 connects bank 2.
A read request is sent to 4-0.

When the value of the lower two bits of the address register 25 is "10J", the value of the request register 27-1 is "1", and the value of the write request register 21 is "1", the signal line 209
-2, a write request signal is sent to bank 24-2. Similarly, request signals are sent to other banks 24-1 and 24-3 through signal lines 209-1 and 209-3.

The read data from the banks 24-0 to 24-3 are outputted to the OR circuit 28 through signal lines 211 to 214, respectively, and logically summed. Sent on 17th.

FIG. 2 is a block diagram showing the interior of #O bank 24-0 in FIG. 1 in detail. FIG. 3 is a timing chart showing the operation. The operation of the bank will be explained using FIGS. 1 to 3. In one embodiment of the invention, the bank access time and cycle time are three machine cycles.

When a request is sent to the memory unit 2 and the bank control circuit 26 determines which bank 24-0 should be activated, an activation signal is sent through the signal line 209-0.

At timing O (T=O), a read start signal is sent to bank 24-0. This activation signal is set in activation register 250 and sent to timing circuit 253 via signal line 260. The timing circuit 253 generates a hold signal for holding the data in the write data register 252 and the bank address in the bank address register 251 during a cycle period, and sends it out from the signal line 261.

Read operation (T=1.2.3>, timing 3 (T
=3), the read data at the address specified by the signal line 262 is read from the memory 254 and sent out from the signal line 266. At this time, a set signal for the bank read data register 255 is sent from the timing circuit 253 via the signal line 265.

The bank read data register 255 reads this bank 24-
Timing 4 when O is activated and valid data is read
The value is cleared to "O" except when valid data is sent from the signal line 214 (T=4).

In the write operation (T=4.5.6), instead of setting read data in the bank read data register 255, a write pulse is sent from the timing circuit 253 to the memory 254 via the signal line 264, and the write pulse specified by the bank address register 251 is sent from the timing circuit 253 to the memory 254. The contents of the bank write data register 252 are written to the address through the signal line 263.

Other banks 24-1 to 24-3°34- in FIG.
θ~34-3.44-0~44-3.54-0~54-
Bank 24-0 also has a similar configuration and can operate in the same way as bank 24-0.

The above content is the configuration of memory unit 2, and the internal configurations of other memory units 3 to 5 are also the same as the configuration of memory unit 2 (in FIG. 1, memory units 4 and 5 are
(The internal structure of is omitted.)

The output signals of the memory unit 2 are transmitted through signal lines 205 and 207.
, 210 to the memory unit 3, and the output signals of the memory unit 3 are signal lines 305, 307.

310 (The output signal of the write request register 31 is sent out through the signal line 305, and the output signal of the address register 35 is sent out through the signal line 307.
(by which the output signal of the request register 37-1 is sent) is sent to the memory unit 4. Also, the output signal of the memory unit 4 is the signal [1405, 407, 4
10 to the memory unit 5, and the output signals of the memory unit 5 are sent to the memory unit 2 via signal lines 505, 507, and 510. That is, the memory units 2 to 5 are connected in an annular manner in the order of 2-3-4-5-2.

The output of read data from each memory unit 2 to 5 is sent to the OR circuit 17 via signal lines 215 , 315 , 415 , and 515 , and to the read data register 15 via signal line 110 . Since each bank outputs the value "0" as read data at times other than the read timing, necessary read data can be obtained by calculating the logical sum of each read data. Each memory unit 2~
Addresses for banks in memory units 2 to 5 are memory units 2 to 5.
It is numbered in the direction of 5, and banks 24 to 0.34
-0.44-0゜54-0.24-1.34-1.・・・
The addresses increase by one in the order of...

4 and 5 are timing charts of one embodiment of the present invention. Using FIGS. 1 to 5, we will explain the specific operation of an embodiment of the present invention in the case where there is a read request and a write request at the same time at consecutive addresses, which is a characteristic point of the present invention. I do.

FIG. 4 shows consecutive read accesses R to R7 and consecutive malicious accesses W to consecutive addresses on the storage device.
-W7 is a timing chart when processing one single read access or single-I include access in each machine cycle. In this case, the double access mode register 12 that specifies double access has the value "0", and the selectors 23-0 .
Since the selection signal of 23-1゜33-0.33-1 has the value rOJ, the address register 25゜35 and write request register 21.31 in each memory unit 2 to 5 have the address of the interface section 1, respectively. The contents of register 10 and write request register 13 are input.

The read start address R8 is an address in bank #0 24-0, and as mentioned above, in one embodiment of the present invention, addresses are assigned in order of bank number, so the next address R1
is within #1 puncture 34-θ. Timing 1 (T-1
Since the lower two bits of the address register 10 have the value "00", the read access to the R6 address accepted by the interface section 1 at
and read data register 1 at timing 7.
Set to 5.

Continuing, at timing 2 it was originally W. The R. should handle write access to the address. Since the #0 bank 24-0 is in use for three machine cycles when accessing the address, the processing device waits until timing 4, and a read access to the R1 address is sent instead. R
At address 1, the lower two bits of address register 10 have the value “01”.
” Therefore, the value from the signal @107 becomes rlJ, and the #1 bank 34-0 of the memory unit 3 is accessed.

W at timing 4. Since a write access to the address is accepted and the lower two bits of the address register 10 are "00", the write operation is performed using three machine cycles from timing 6 to timing 8 when #O bank 24-0 is not used. will be held. After that, read access and write access are accepted alternately, but the address input line 111 and the command input line 112, 1
Since there is only one 14, read access and write access can each be processed only once every two machine cycles.
It can be seen that the usage efficiency is poor.

Next, FIG. 5 is a timing chart when the same access as in FIG. 4 is processed using double access. Double access means that when a certain request is accepted once in double access mode, the same process as this request is performed for the next address following the process for this request.

That is, two processes (two reads or two writes) are performed with one request.

First, at timing 1, when a read request for address R0 is received by the interface unit 1 with double access, the read process for address Ro+1 (referred to as address R1) is performed subsequent to address R0. Since the lower two bits of the address R0 have the value "OO", the value from the signal line 106 becomes "1", and the request is sent to the memory unit 2.

Also, at timing 1, the double access mode register 20
is assumed to be the value rOJ. At this time, selector 23-0
The selection signal input to the selector 23-1 via the signal line 203 has a value of "0". Therefore, at timing 2, the value of the address register 10 is set in the address register 25, and the value of the write request register 13 is set to "0" in the write request register 21 (since it is a read request, the value of the register 13 is "0" at timing 1). ) is set. Furthermore, the value "1" from the decoder 16 is set in the request register 27-1. This output is sent to the bank control circuit 26 through the OR circuit 29-1. The bank control circuit 26 is connected to the signal line 20
From the output of #8 and signal line 205, we know that #0 bank 24-0 is to be read, and from the signal line 209-0 we read bank 2.
4-O starts reading address R8.

At timing 2, the value "1" is also set in the double access mode register 30 of the memory unit 3.

At timing 3, the interface section 1 accepts reading of address R2. At timing 2, the value of the request register 27-1 and the value of the double access mode register 30 are "1J", so the value from the signal line 303 becomes "1", and the value of the address register 25 of the memory unit 2 is stored in the address register 35. The content (R,') of is set. The write request register 31 has memory unit 2.
The contents of the write request register 21 (value rOJ: H output) are set. Also, the value "1" is set in the request register 37-0, but the request register 37
It is not set to -1.

As mentioned above, addresses are assigned in the direction of memory units 2 to 5, so the memory units 2 to 5 as a whole are the same as when reading from address R1, which is the next address after address R8, is accepted at timing 2. An action is taken. That is, since the double access from the R0 address is received at timing 1, the R address and the next address, the R1 address, are successively read.

In this way, from then on, by performing double access reading to the addresses on the even bank side (memory unit 2, 4) at timings 3, 5, 7, . . . Read data at consecutive addresses starting from address R8 is set every machine cycle.

Writing is made to wait in the processing unit until timing 4 as in normal times, and after timing 4, one write is made every two machine cycles.
A write request in double access mode is sent to the interface unit 1 one after another.

However, the write data is at consecutive addresses W after timing 4. , Wl, W2. Write data corresponding to... is sent out every machine cycle. The operation is basically the same as reading in double access mode, and writing is performed every machine cycle from timing 6 onwards.

As is clear from a comparison between FIG. 4 and FIG. 5, by introducing the double access function, each bank is used without waste, and the signal line 115 of the write data bus and the signal line 116 of the read data bus is used every machine cycle, increasing the efficiency of data bus usage.

In one embodiment of the present invention, the case where the memory unit 3 is accessed from the memory unit 2 during double access has been described, but the same operation can be performed when accessing the subsequent memory unit 5 from another memory unit 4. This becomes clear when considering that the memory units 2 to 5 are connected to each other in an annular manner and that data and control signals are commonly distributed to each of the memory units 2 to 5.

In this way, by dividing the storage device into a plurality of memory units 2 to 5, addressing the banks of memory units 2 to 5 in the order of memory units 2 to 5, and providing a double access function, it is possible to access consecutive addresses. Read access and write access can be performed in parallel, increasing the efficiency of using banks and data buses and improving throughput.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, as described above, a write operation and a read operation with respect to a memory bank provided in each of a plurality of memory units can be performed by a single request from a processing device. By doing so, it is possible to improve the usage efficiency of memory banks and data buses, and to improve throughput.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a detailed block diagram of the memory bank shown in FIG. 1, FIG. 3 is a timing chart of FIG. 2, and FIGS. is a timing chart of one embodiment of the present invention. Explanation of symbols of main parts 1...Interface sections 2 to 5...Memory unit 10.25.35.55...Address register 11, 27-0.27-1゜37-0.37-1...Request register 12.20.30...Double access mode register 13.21, 31.51...Write request register 23-0 .23-1.33-0.33-1...
Selector 1'4, 22.32...Write data register 15...Read data register 16...Decoder 24-0~24-3.34-0~34- 3゜44-0～
44-3.43-0~54-3...Bank 26
．． 36...Bank control circuit

Claims (1)

[Claims] A storage device comprising an interface section for a processing device and a plurality of memory units, the plurality of memory banks being supplied with common write data and having addresses assigned according to the order of the memory units. and a selection means for selecting and outputting one of the address information and control information of the preceding memory unit and the address information and control information from the interface section, and selecting means for selecting and outputting one of the address information and control information of the preceding memory unit and the address information and control information from the interface section. Write and read operations are performed on the memory bank of one of the memory units and the memory bank of the other memory unit in response to input of address information and control information and input of a double access control signal. A storage device characterized by: