JPS6340364A - Random access memory - Google Patents

Abstract

PURPOSE:To make larger the distance between the adjacent bit lines of a random access memory and to reduce the capacity between the adjacent bit lines by a method wherein the adjacent bit lines are each formed in a manufacturing process different from each other. CONSTITUTION:A first bit line 1 is constituted of a first layer poly Si layer and a second bit line 6 is constituted of a second layer poly Si layer which is formed in a manufacturing process different from that of the first bit line 1. Cell plates 2 are formed between a field oxide film and the second bit line 6. As the first bit line 1 and the second bit line 6, which adjoins the first bit line 1 and is formed in a manufacturing process different from that of the first bit line,are each formed on different insulating films, the distance between the adjacent bit lines is augmented. as more as the amount of the film thickness of an interlayer insulating film to be formed between them and the capacity between the adjacent bit lines is reduced. Thereby, the change amount of signal potential to appear on the bit lines can be augmented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a method of configuring bit lines in a dynamic random access memory, particularly a random access memory constructed using MOS transistors.

[Prior art] Figure 3 shows a dynamic MO with a conventional folded bit line configuration.
FIG. 2 is a diagram showing a planar arrangement of a memory section of an SRAM (random access memory). In FIG. 3, the random φ access memory consists of an active region 4 for storing and transferring information charges, and a first layer aluminum wiring layer electrically connected to the active region 4 via a contact region 5. a cell plate 2 serving as one electrode of a memory cell capacitor that stores information charges, and a word line 3'' for controlling read/write operations of information charges in the memory cell. A field oxide film is provided between the active regions so that they are electrically insulated from each other. That is, a field oxide film is formed around the active region 4. The cell plate 2 is surrounded by a chain line in the figure. In this region where the cell plate 2 is not formed, a MOS transistor is formed with the word line 3 as a gate electrode, and the MOS transistor is formed outside the field oxide film when reading/writing signal charges. In the folded bit line configuration shown in the figure, memory cells are connected to every other bit line 1 for one word line 3.

That is, one bit line pair is formed by two bit lines. Next, the operation will be explained using an information read operation as an example.

First, when one word line is selected, information held in memory cells connected to the word line 3 is read onto the bit line 1. In a normal folded bit line configuration, in a bit line pair, a bit line to which a selected memory cell is connected and a bit line to which an unselected memory cell is connected (
The configuration is such that information is read by detecting a potential difference between the bit lines (hereinafter referred to as complementary bit lines). In other words, a reference potential appears on the complementary bit line, a potential corresponding to the information held by the memory cell appears on the selected bit line, and the potential difference between the potential on this bit line and the reference potential on the complementary bit line is expanded to transmit information. It is configured to read.

[Problems to be Solved by the Invention] Normally, when reading information onto the bit line 1, if the bit line capacitance is C[1 and the memory cell capacitance is C8, the amount of change in potential appearing on the bit line is Cs/Ca. This is a very small value given by . Therefore, it was necessary to detect this amount of potential change using a highly sensitive sense amplifier. However, as memories become more highly integrated, the distance between adjacent bit lines becomes smaller, and the capacitance between adjacent bit lines increases.
As a result, the bit line capacitance Ca increases, and the amount of change in potential appearing on the bit line becomes extremely small, making it difficult to read information accurately. Here, it is assumed that the bit line capacitance 14Ca includes the wiring capacitance of the bit line itself and the stray capacitance parasitic thereto.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a random access memory having a bit line configuration that eliminates the above-mentioned problems and does not increase the capacitance between adjacent bit lines even when the degree of integration increases.

[Means for Solving the Problems] In the random access memory according to the present invention, adjacent bit lines are formed in different manufacturing processes.

[Operation] In the random access memory according to the present invention, since adjacent bit lines are formed in different manufacturing processes,
Since the distance between adjacent bit lines is greater than the distance between adjacent bit lines when formed in the same conventional manufacturing process, the capacitance between adjacent bit lines is reduced.

(Embodiment of the Invention) Fig. 1 is a diagram showing a planar arrangement of a memory cell portion of a random access memory which is an embodiment of the present invention. The difference from the cell configuration is that the bit line 1 and the focus line 6 are formed in different manufacturing processes.The other configurations are the same as the conventional one and are given the same reference numerals.

FIG. 2 is a diagram showing a cross-sectional structure taken along line A-B in FIG. 1. As shown in FIG. 2, the first bit line 1 is
The second bit line 6 is made of a first polysilicon layer.
is composed of a second layer polysilicon layer formed in a manufacturing process different from that of the first bit line 1. A cell plate 2 is formed between the field oxide film and the second bit line 6.

As is clear from the configuration of FIG. 2, the first bit line 1 and the second bit line 6, which is adjacent to the first bit line 1 and formed in a different manufacturing process, are formed on different insulating films. Therefore, the distance between adjacent bit lines increases by the thickness of the interlayer insulating film formed therebetween, and the capacitance between adjacent bit lines is reduced. Thereby, the amount of change in signal potential appearing on the bit line can be increased.

In the above embodiment, the bit line is formed using polysilicon, but the same effect as in the above embodiment can be obtained even if it is formed using other materials such as polycide, silicide, or aluminum.

Furthermore, in the above embodiment, a random access memory with a folded bit line configuration was described;
Similar effects can be obtained by applying the present invention to random access memories with other configurations.

[Effects of the Invention] As described above, according to the present invention, since adjacent bit lines are formed in different manufacturing processes, the thickness of the interlayer insulating film formed between them is greater than that of the conventional method. To realize a dynamic random access memory that can reduce the capacitance between adjacent bit lines accordingly, increase the amount of change in signal potential appearing on the bit line, and read information accurately. be able to.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a planar arrangement of a memory cell portion of a random φ access φ memory according to an embodiment of the present invention. FIG. 2 is a diagram showing a cross-sectional structure taken along line A-B in FIG. 1. FIG. 3 is a diagram showing a planar arrangement of a conventional random access memory. In the figure, 1 is a first bit line, 6 is a second bit line adjacent to the first bit line and formed in a different manufacturing process from the first bit line, 2 is a cell plate, and 3 is a word line. , 4 is an active region, and 5 is a contact region. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A memory cell array consisting of a plurality of memory cells arranged in a matrix of rows and columns, each of which stores information, and memory cells arranged in the same row in the memory cell array are connected. A random access memory comprising at least a word line and a bit line to which memory cells arranged in the same column in the memory cell array are connected, characterized in that adjacent bit lines are manufactured using different manufacturing processes. Access memory.