JPS6337997B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fixed pattern noise removal circuit in a video camera using a solid-state image sensor.

2. Description of the Related Art Solid-state imaging devices configured with semiconductor ICs have been developed as imaging devices such as television cameras in place of conventional image pickup tubes. FIG. 1 schematically shows such a solid-state imaging device. 1st
In the figure, 1 is a horizontal scanning circuit, 2 is a vertical scanning circuit, and 3, 3 _o , 3 _{o +1} , 3' _o , 3' _{o +1} are light beams that become multiple 1 light receiving elements arranged in a plane. The diodes, 4, 4 _o , 4 _o+1 , 4' _o , 4' _o+1 , etc. are MOS transistors for vertical switches arranged in the same way.
5 _, 5 o, 5 _o+1 are horizontal switch MOS transistors, 6, 6, 6' are vertical scanning lines, 7, 7 _o , 7 _o+
1 is a horizontal scanning line, 8, _8o , 8o ₊₁ is a vertical signal line,
9 is a horizontal signal line. Note that here the subscripts n,
(n+1) etc. means the nth or (n+1)th.

First, an overview of the signal reading method of such a solid-state imaging device will be explained.

Photodiodes 3 arranged in a planar manner receive light and store photoelectrons in their respective junction capacitors according to the amount of light received. When the vertical scanning circuit 2 generates a positive scanning pulse on the vertical scanning line 6, the vertical switch MOS transistors 4 _o , 4 _o+1 , . . . connected to the vertical scanning line 6 are turned on. Subsequently, the horizontal scanning circuit 1 scans the horizontal scanning lines 7 _o ,
7 When positive scanning pulses are sequentially generated at _o+1 ,...,
Correspondingly, the horizontal switch MOS transistors 5 _o , 5 _o+1 , . . . are sequentially turned on, and the photoelectrons stored in the photodiodes 3 _o , 3 _o+1 , . It is extracted and becomes an image signal.
When the reading of the photodiodes _3o , 3o ₊₁ , .
The photoelectrons of the photodiodes 3' _o , 3' _o+1 , . . . are read out. By sequentially repeating the vertical scanning and horizontal scanning as described above, the photoelectrons of all the photodiodes are read and an image signal is obtained.

FIG. 2A shows a horizontal scanning pulse waveform _15o applied to the gate of the n-th horizontal switch MOS transistor, and similarly, FIG. 2b shows the (n+1)th horizontal scanning pulse waveform 15o ₊₁ . FIG. 2C shows the signal waveform obtained at the output terminal 14 (FIG. 1).
Spiked voltage fluctuations 17 _o , 17 _o+1 and 18
_o , 18o ₊₁ is called spike noise, and is generated between the gates of MOS transistors _5o , 5o ₊₁ shown in FIG. 1 or between horizontal scanning lines _7o , _7o+1 and horizontal signal line 9. This occurs at the rising and falling portions of the horizontal scanning pulse due to existing parasitic capacitances such as 10 _o and 10 _o+1 . Broken lines 19 _o and 19 _o+1 indicate the case where there are signal charges.

If the above spike noise always has a constant shape at every scanning point, the frequency components of this waveform are only the repetition frequency and frequency components that are integral multiples of the repetition frequency, and compared to the frequency components of the original signal. Since it has a high frequency, it can be easily removed with a low-pass filter, and there is little harm to the image signal. However, in reality, the shape and size of this waveform are the changes in the horizontal scanning pulse waveforms 15 _o and 15 _o+1 , and the parasitic capacitance 1
It changes greatly due to changes of 0 _o and 10 _o+1 , and for example, as shown in FIG. 3, the waveform becomes exactly similar to an amplitude modulated wave. However, unlike in the case of ordinary amplitude modulated waves, the carrier frequency (corresponding to the repetition frequency of spikes) and the modulation frequency (the frequency at which the spike waveform changes) are close to each other, so as shown in Figure 3, A time lag is observed between the envelope 20 of the positive polarity spike and the envelope 21 of the negative polarity spike, and therefore, as a whole, frequency components lower than the repetition frequency of the spike are included as shown by the broken line 22. Become. This component has the same frequency band as the original signal and can no longer be removed by a low-pass filter, becoming a pseudo signal that interferes with the image signal. In particular, this pseudo signal is
This occurs when the signals of the vertically arranged photodiodes (3 _o , 3' _o , ..., etc.) that share the vertical signal lines 8 _o , 8 _o+1 are commonly overlapped, so the vertical stripes are fixed on the playback screen. It appears as pattern noise, is very noticeable, and greatly impairs image quality.

As a conventional technique for removing such fixed pattern noise, there is a signal processing circuit system as shown in FIG. Utility Model Application No. 53-52105 (Utility Model Application No. 54-155426) In this figure, 23 is the sensor section of the solid-state imaging device as previously explained in FIG. 1, 24 is the amplifier, 27 is the integrating capacitor, and 28 is the integrating reset. for switch
MOS transistor, 29 is a load resistor, 30 is a power supply, 31 is a reset pulse application terminal, 32 is a signal output terminal, etc. The transistor 25 and the emitter resistor 26 constitute a grounded emitter amplifier circuit. FIG. 5 is a diagram of operating voltage waveforms or current waveforms of essential parts of the circuit of FIG. 4, and the operation of the circuit will be explained using this diagram. A signal having the waveform shown in FIG. 5A is applied to the base of the transistor 25. To be more precise, this spike noise consists of a positive polarity spike followed by a negative polarity spike, each pair having a different size and shape, but we will avoid complexity here. Therefore, it is drawn as a uniform waveform. Further, an appropriate DC bias voltage is superimposed on the waveform A so that the transistor 25 operates with good linearity. FIG. 5B shows the reset pulse waveform, and when the pulse is at a high level, the integral reset switch MOS transistor 28 is turned on, and when it is at a low level, it is turned off.

Now, assuming that the switch is on before time t _o , the integrating capacitor 27 is approximately the voltage V _A of the power supply A 30, ignoring the voltage drop due to the load resistor 29.
is charged up to. When the switch is turned off at time t _o , the charge stored in the integrating capacitor 27 is discharged through the transistor 25, and the voltage of the integrating capacitor (although the discharge current at this time is a current controlled by the waveform shown in FIG. 5A) The collector voltage of transistor 25) drops according to the waveform shown in FIG. 5C. The amount of voltage drop is proportional to the value obtained by integrating the collector current of the transistor 25 from time t _o to time t' _o , that is, the total sum of discharged charges during that period, and inversely proportional to the capacitance value of the integrating capacitor 27.
If the beginning t _o and the end t' _o of the integration period are set so as to completely include both the positive spike noise 17 _o and the negative spike noise 18 _o , the adjacent spikes of both positive and negative polarities will be at the same level through integration. Therefore, these cancel each other out, and the integral value, that is, the total sum of discharged charges, is not affected by the spike at all.

The integral value is the sum of the value due to the DC bias current of the transistor 25 and the value due to the original signal current 19 _° .

Next, when the integral reset switch is turned on at time _t'o , the integral capacitor 27 is charged again to the voltage V _A of the power supply 30 through the load resistor 29, but the amount of charge at this time _is
Since it is almost equal to the charge discharged during the period up to t′ _o ,
(To be exact, the charge flowing through the transistor 25 from t' _o to t _o+1 is also added.) This charging current waveform (FIG. 5 D) is output from the signal output terminal 32 as a voltage drop across the load resistor 29. By extracting the signal, it is possible to obtain a signal from which the spike noise has been removed. Actually, the low-frequency portion (average value of the broken line 37) obtained by passing the waveform shown in FIG. 5D through a low-pass filter becomes the image signal.

The above is an explanation of the operating principle of this signal processing circuit, but there are some points to keep in mind when actually using it. The first point is that in order to improve the effect of canceling spike noise, it is necessary to
The second point is to delay t′ _o as much as possible.
By delaying t′ _o , the period until the next integration start point (t _o+1 ) is shortened, but because of this, the integration reset (charging of the integrating capacitor) is not performed sufficiently. It is necessary to avoid deterioration of resolution due to mixing of signals from neighboring photodiodes. To achieve this, the load resistance must be selected to a suitably low value, and the integral reset switch must be
The on-resistance of the MOS transistor must also be sufficiently low. Furthermore, the switching time must also be sufficiently short.

By the way, if such a conventional signal processing circuit is
There are several obstacles to making it into an IC, but the biggest one is that the integral reset switch requires a MOS transistor. Bipolar ICs are generally better suited in many ways than MOS ICs for linear ICs that process video signals, so the need for MOS transistors in such ICs is problematic. In recent years, bipolar IC
Technology that uses MOS transistors in combination has also been developed, but the performance is still insufficient in terms of important characteristic parameters such as on-resistance and switching time.

For these reasons, the conventional signal processing circuits explained above are not suitable for IC implementation, and bipolar
There is a demand for new signal processing circuits suitable for IC implementation.

The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art, eliminate the need for MOS transistors, and use bipolar
An object of the present invention is to provide a fixed pattern noise removal circuit system suitable for ICs.

The key point of the present invention is to apply the rectifying characteristics of a diode or transistor to perform the function of an integral reset switch, and to apply a reset pulse to one end of an integral capacitor, which acts as if the reset pulse were superimposed on the integrated voltage of the capacitor. This superimposed pulse then makes the diode or transistor conductive or non-conductive to perform integration and integral reset. More specifically, the present invention connects a transistor that converts an input voltage to a current, an integrating capacitor and a cathode of a diode to the collector of the transistor, and connects the anode of the diode to a power supply via a load resistor. By applying a negative integral reset pulse to the other end,
When the reset pulse is at a high level, the diode is cut off and the capacitor performs an integration operation, and when the reset pulse is at a low level, the diode is turned on and at the same time as the integration is reset, the integrated value of the input signal stored in the capacitor is read and taken out to the load resistor.

Hereinafter, the present invention will be explained with reference to Examples.

FIG. 6 shows a first embodiment of the invention. In FIG. 6, 38 is a diode for an integral reset switch, and other symbols that are the same as those in FIG. 4 are the same as those explained in FIG. 4 or have the same functions. FIG. 7 is a waveform diagram for explaining the operation of the embodiment shown in FIG. A is the base voltage waveform of the transistor 25, B is the reset pulse application terminal 3
1, C is the collector voltage waveform of the transistor 25, and D is the load resistor 29.
This is the waveform of the current flowing through. The waveform diagrams A to D also show mutual time relationships. The signal waveform applied to the base of the transistor 25 in FIG.
It has a spike shape as shown in Figure A. To be precise, each spike noise has a different size and shape as explained in Figure 3, but to avoid complication, it is shown in Figure 5. Similarly, it is drawn with a uniform waveform. Further, an appropriate DC bias voltage is superimposed on the waveform of FIG. 7A so that the transistor 25 operates with good linearity. The reset pulse applied to the reset pulse application terminal 31 is a negative polarity pulse as shown in FIG. 7B.

Now, assume that the reset pulse is at a low level just before _time to, charging of the integrating capacitor 27 has already been completed, and therefore the collector potential of the transistor 25 has reached the voltage V _A of the power supply 30.
(To be precise, the voltage drop due to the collector current of the transistor 25 flowing through the load resistor 29 and the voltage drop due to the diode must be subtracted from V _A , but since this drop is small, it will be ignored in the explanation.) (The diode is described as an ideal diode with no offset voltage.) Then the time t _o
When the reset pulse changes from low level to high level by the voltage V _P , the voltage across the integrating capacitor cannot change suddenly, so the collector potential of the transistor 25 changes to the reset pulse voltage as shown in Figure 7C. It rises by the amount of V _P , and (V _A
+V _P ) is reached. In this state, the integral reset switch diode 38 is reverse biased and cut off. And from time t _o to t′ _o
Until then, all of the collector current of the transistor 25, including the DC component, flows through the integrating capacitor 27, and as a result, the electric charge stored in the capacitor 27 decreases as time passes, and the voltage across it decreases. , the collector voltage waveform of the transistor 25 decreases as shown in FIG. 7C. The amount of voltage drop Vc from t _o to t′ _o is equal to the integral value of the collector current during this period, that is, the value obtained by dividing the discharged charge by the capacitance value of the capacitor, so it satisfies the condition of V _C ≦V _P By determining the relationship among the capacitor capacitance value, collector current, reset pulse amplitude, pulse width, etc., the cut-off state of the diode 38 can be maintained between t _o and t' _o .

Next, at time _t'o , when the reset pulse changes from high level to low level by voltage V _P ,
The collector potential is (V _A −V _C ) as shown in Figure 7 C.
(Actually, due to the pulse fall time, the waveform tip of C does not drop to the rounded edge (V _A - V _C ), but this is done here to explain the principle.) When the diode 38 is in a forward bias state Then it turns on. At the same time, the capacitor 27 by the power supply 30
charging starts. It is obvious that the charging time constant T is given by the product of the capacitance value of the integrating capacitor and the resistance value of the load resistor 29, but by setting this to be sufficiently smaller than the pulse width τp of the reset pulse, , it is possible to rapidly charge the capacitor 27, and therefore the waveform of the collector potential rapidly rises from (V _A −V _C ) toward V _A as shown in FIG. By the end of the pulse period (t _o+1 ) _, charging is almost completed and the state returns to the same state as at the first time to. The charging current waveform during this period is as shown in FIG. 7D. Note that returning the state of the integrating capacitor to the state before integration is called integration reset, and the pulse and diode that play this role are called reset pulse and reset switch diode. From _to like this
The operation during the period up to t _o+1 is regarded as one cycle, and this operation is repeated one after another.

Incidentally, the amount of charge charged in the period from _t'o to t0 ₊₁ matches the amount of charge discharged as _the collector current of the transistor during the period from t0 to _t'o . And since this is proportional to the integral value of the collector current from t _o to t' _o as mentioned above,
If the charge during the period from t′ _o to t _o+1 is taken out as a signal, only the original signal with the spike noise of both positive and negative polarities canceled can be obtained, as in the explanation of the prior art. On the other hand, since the charging charge during the period from t′ _o to t _o+1 is equal to the integral value of the charging current during this period, the voltage waveform generated at both ends of the load resistor 29 when the charging current flows through the load resistor 29 is By passing it through a filter, the above signal can be obtained. To be precise, in addition to the charging current, the collector current of the transistor 25 is also added to the current flowing through the load resistor 29 during the pulse period (t' _o to t _o+1 ), but since the ratio is small, the current flowing through the load resistor 29 is This does not impede understanding, and if you take this into consideration carefully, you will understand that spike noise in both the positive and negative directions will be canceled out more precisely.

In this first embodiment, the points to keep in mind are:
The purpose is to set the charging time constant determined by the integrating capacitor and the load resistance to be smaller than the pulse width τp. The design example is for a solid-state imaging device that horizontally scans a photodiode at a period of 140 nSec, with a pulse width τp of 50 nSec, an integral capacitance of 40 pF,
Load resistance: 150Ω, charging time constant 6nSec. If the capacitor capacitance value is too small, the V _C shown in Figure 7 (c) will increase, and the pulse amplitude will need to be correspondingly increased.Also, if the load resistance is too small, the signal voltage that can be extracted across it will become small. Even if the time constant is the same, care must be taken when selecting the capacitor and load resistance values.

Next, a second embodiment will be described with reference to FIG. 8, in which the above-mentioned restrictions regarding load resistance selection are eliminated and, therefore, a sufficient signal voltage can be extracted.

In FIG. 8, 41 is an integral reset switch transistor, 42 is a power supply of voltage V _A , and 30 is a transistor for an integral reset switch.
It is a power supply with a voltage V _B higher than V _A , and the others are the first
It is the same as or performs the same function as that of the embodiment.

In explaining this embodiment, the waveform diagram of FIG. 7 will be used again. Now, just before time t _o , the reset pulse is at low level and the integrating capacitor 2
Assume that charging of the transistor 7 has already been completed and the collector potential of the transistor 25 has reached the voltage V _A of the power supply 42. (To simplify the explanation, it is assumed that there is no base-emitter offset voltage Vbe of the transistor.) Next, when the reset pulse changes from low level to high level at time _to , the collector potential of transistor 25 is as shown in FIG. The reset pulse voltage increases by the amount of the reset pulse voltage V _P , and (V _A +V _P )
reach. In this state, the base and emitter of the transistor 41 is in a reverse bias state and is cut off. The operation from time t _o to t′ _o is exactly the same as in the first embodiment,
The collector voltage waveform of the transistor 25 decreases in proportion to the integral value of the collector current, as shown in FIG. 7C. Of course, between t _o and t′ _o, transistor 4
1 maintains the cut-off state.

Next, at time _t'o , when the reset pulse changes from high level to low level by V _P ,
As _{shown in} FIG.
In reality, (V _A −
V _C ). ) The base-emitter of the transistor 41 becomes forward biased and enters the active state. At the same time, from the power supply 30 to the load resistor 2
9, the capacitor 27 via the transistor 41
charging starts. The charging time constant T at this time is the emitter resistance of the transistor 41 and the capacitor 2.
It is given by the product of the capacitance values of 7 and does not depend on the resistance value of the load resistor 29. This point is different from the first embodiment described above, and there is an advantage that a sufficient signal voltage can be extracted because the resistance value can be designed to an appropriately large value. The emitter resistance value of the transistor 41 depends on the emitter current value, but a value of 50Ω or less can be easily obtained, and the charging time constant T can be designed to be sufficiently smaller than the pulse width τp. By the end of the pulse period (t _o+1 ) _, charging is almost completely completed and the state returns to the same state as at the first time to. The operation of this circuit by this repetition is the same as in the first embodiment, and the point that spike noise is thereby removed is also the same.

To summarize the features of the second embodiment, the transistor 41 operates as an integral reset switch by utilizing the rectifying characteristics of its base-emitter junction.
At the same time, it operates as a common base amplifier. This allows the load resistance value to be selected regardless of the charging time constant, making it possible to obtain a large signal voltage.

Next, a third embodiment is shown in FIG. In this embodiment, a resistor 43 is inserted in series with the emitter of a transistor 41. This resistor 43 allows the charging time constant to be adjusted as necessary.
Also, since the peak value of the charging current is approximately equal to the value obtained by dividing the amplitude of the reset pulse by the charging resistance (the sum of the emitter resistance of the transistor 41 and the resistance value of the resistor 43), the load resistance can be changed by adjusting the value of the resistor 43. By adjusting the peak value of the current flowing through the transistor 29, an appropriate design can be made to prevent the transistor 41 from becoming saturated.

Next, a fourth embodiment is shown in FIG. In this embodiment, a resistor 44 is inserted in series with the integrating capacitor 27. This resistor 44 allows the third
It is clear that the charging time constant and the peak value of the charging current can be appropriately designed as in the case of the embodiment. Another advantage of this embodiment is that the spike-like drop in the collector voltage of the transistor 25 (see FIG. 7C) that occurs during the charging period can be reduced, and the degree of freedom in setting the voltage of the power source 42 is increased accordingly. .

Note that the following may be considered as a modification of the above embodiment. In the first to fourth embodiments, it is also possible to change each transistor from an NPN type to a PNP type. With this change, it is natural to reverse the polarity of the power supply and the direction of the diode in the first embodiment. Note that the diode 38 is a base, which is often seen in IC circuits.
It may be a diode-connected transistor whose collector is conductively connected.

As explained above, according to the present invention, a signal processing circuit that can remove spike noise peculiar to solid-state imaging devices and fixed pattern noise generated on the screen due to the spike noise, which is required in the conventional technology, can be used.
It can be realized without using transistors, and the circuit
IC becomes extremely easy.

Still another effect of the present invention is that the gain of the signal processing circuit can be set large because the load resistance can be set independently of the charging time constant.

Although the present invention has been explained based on the assumption that the spike noise to be removed is unique to solid-state imaging devices, similar noise occurs in other devices or signal processing circuits, and it is necessary to remove this noise. However, the present invention is effective even in such cases.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of the solid-state imaging device, Figure 2 is a waveform diagram of the horizontal scanning pulse and output signal as above, Figure 3 is a spike noise waveform diagram, Figure 4 is a noise removal circuit according to the prior art, Figure 5 is an explanation of the operation of the same as above. FIG. 6: First embodiment of the present invention; FIG. 7: Explanatory diagram of the same operation as above; FIG. 8: Second embodiment of the present invention; FIG. 9: Third embodiment of the present invention; FIG. 10 Fourth embodiment of the present invention. Explanation of symbols, 23...Sensor section of solid-state imaging device, 24...Amplifier, 25...Transistor, 2
7... Integrating capacitor, 29... Load resistance, 31
...Reset pulse application terminal, 32...Signal output terminal.

Claims (1)

[Claims] 1. Noise components contained in a video signal output from a solid-state image sensor that sequentially reads optical information accumulated in a plurality of photoelectric conversion elements provided on a surface region of a semiconductor substrate using discontinuous scanning pulses. A noise removal circuit that integrates and resets the integral for each pixel and eliminates the noise includes a first transistor that converts the input voltage into a current, and a capacitor connected at one end to the collector of the transistor and to which a reset pulse is applied to the other end. and a unidirectional semiconductor element having one end connected to the collector of the transistor and the other end connected to a first power source via a load. 2. The noise removal circuit according to claim 1, wherein the unidirectional semiconductor element is a diode or a diode-connected transistor. 3. Claims characterized in that the unidirectional semiconductor element is a second transistor having an emitter connected to the collector of the first transistor, a collector connected to the load, and a base connected to a second power source. The noise removal circuit according to item 1.