JPS6334641A - Information processor - Google Patents

Abstract

PURPOSE:To obtain an information processor making unnecessary the reproduction of an IC, even when a fault is generated, by providing a means which executes the function of an instruction word for the instruction word, when the instruction code of the instruction word, and a bit of address modifying control information coincide with a condition set at a RAM in a decoder. CONSTITUTION:When an instruction having the fault exists in the instruction register 1, the RAM 20 in the decoder 4 is set to detect the instruction, and also, the combination of the instructions to execute the another combination of the basic instructions for the instruction, is set at a prescribed position on a main memory. At the time of detecting the instruction having the fault by the decoder 4, the content of an instruction register 9, after being corrected to designate the next instruction, is saved, and a new value is set in stead of the above, and a combined instruction on the previously stated main memory is executed. After completing execution, a saved value is returned to the instruction counter 9, and a mode is returned to an ordinary mode.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to avoiding design failures in LSI-based information processing devices.

(Prior Art) What is the problem when a design failure occurs in an LSI-based information processing device? There is a high probability that the LSI will need to be remanufactured to resolve the issue. On the other hand, even with a single gate array that has a relatively short turnaround time,
Does LSI remanufacturing take a longer time than SSI technology? In short, the impact on the development and evaluation period of the device is extremely large.

(Problems to be solved by the invention) The conventional LSI information processing device mentioned above has a long turnaround time, and in order to smoothly proceed with evaluation, it is necessary to design LSI hardware that requires remanufacturing. The drawback is that means are needed to avoid the above obstacles.

The purpose of the present invention is to detect all specific conditions from the command code and address modification control information of the command word, and then detect this? Is it set in a variable state, and when a specific condition is detected, an instruction is sent to a predetermined main memory area? Execute according to the above variable state and specific conditions? Can the above disadvantages be overcome by delegating the function of the detected instruction? It is an object of the present invention to provide a friend information processing system a configured to eliminate the problems and shorten the turnaround time.

(Means for solving all problems) The information processing apparatus according to the present invention is configured to include all of a condition detection means, a RAM means, and an execution means.

The condition detection means is for detecting a specific condition from the instruction code of the instruction word and the address modification control information.

The LLAM means is for setting in a variable state under specific conditions.

The execution means is for, when a specific condition is detected by the condition detection means, executing an instruction in a predetermined king memory area in accordance with the variable state, and acting on behalf of the instruction for which all the specific conditions are detected. be.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an instruction control section χ of an embodiment of an information processing apparatus according to the present invention. In FIG. 1, 1 is an instruction register, 2 is an index register, 3 is a segment register, 4 is a decoder, 5 is an address adder, 6 is a virtual address register, 7 is a TLB, 8 is a control circuit, 9 is an instruction counter, 10 is a counter, and 11 and 12 are switching circuits, respectively.

In FIG. 1, instruction register l is cache memory (
This is an instruction register for setting read data from (not shown), and the index register 2 is used for address modification during operand address calculation according to the designation of the instruction word set in the instruction register 1. The segment register 3 stores a segment descriptor 9, which is used to calculate a virtual operand address according to the designation of the instruction word set in the instruction register 1. Address adder 5 is instruction register 11 index register 2
, and the contents of the segment register 3, and calculate the virtual address. The calculated virtual address is set in the virtual address register 6, converted to a real address by the TLB 7, and sent to the cache memory. The decoder 4 decodes the instruction code set in the instruction register 1 and all address calculation designation fields, and detects all trap conditions.

Instructions are taken out according to the instructions of the instruction counter 9,
Each time an instruction fetch request is sent, the contents of the instruction counter 9 are incremented by l via the counter l07. When a branch instruction is executed or initialized, the instruction counter 9 is initialized by an arithmetic processing section (not shown).

When a trap condition is detected by the decoder 4 due to the instruction set in the instruction register 1, it is corrected to specify all the next instructions, and then all the contents of the instruction counter 9 are saved in a predetermined memory area and the error is confirmed. A new value is taken out from the specified area and set in the instruction counter 9.

In this state, the information processing device enters the trap mode, and the trap segment descriptor of the segment register 3 is used as an instruction segment. This discriminator is not used except in trap mode. Is there a combination of commands that are substituted for the trap segment by a combination of basic commands for each trap function at the time of initial setting? Set it. This causes the a+ branch to the above segment to generate a trap and process the t instruction function.

On the other hand, when executing an instruction in a trap segment, it may be necessary to access the instruction segment of the trapped instruction as an operand. For this reason, a load instruction is added to extract an operand from the instruction segment. This instruction generates a trap and uses the instruction segment descriptor as an operand segment descriptor. The operand segment descriptor can be accessed arbitrarily even in trap mode.

At the end of the trap segment instruction group, there is provided an instruction for fetching and setting the contents of the instruction counter 9 from the save area and for dividing by 4 in the trap mode.

FIG. 2 is a block diagram showing the decoder 4 of FIG. 1 in detail. @2 In Figure 2, 20 is a random access memory (hereinafter referred to as RAM), 21 is a decoder, and 22 is a condition detection circuit.

The decoder 4 includes a RAM 20 that is accessed by the instruction code set in the instruction register 1, and a field that specifies the address modification set in the instruction register 1. A t-th decoding circuit 21 for decoding, and a condition detection circuit 2 for inputting the output of the decoding circuit 21 and detecting all trap conditions.
It is composed of 2. The RAM 20 has multiple bit entries corresponding to the instruction food, and the decoding circuit 21
By setting appropriate bits in the RAM 20 in combination with the output of , all conditions can be calculated by combining any address modification designation and instruction code.

FIG. 3 is a block diagram showing details of the condition detection circuit 22 &- in FIG. 2. In FIG. 3, 23 is a flip-frog, 24 to 27 are NAND gates, and 28 is an O
This is the R gate. Signal lines 60 to 64 are each RAM
20 output signal lines, and signal lines 71 to 73 are outputs of the decoding circuit 21. NAND gates 25-27 detect trap condition sounds based on output borrowing codes corresponding to specific commands sent via signal lines 62-64 and address modification conditions sent via signal lines 71-73. .

The clip-flop 23 is reset by the output of the RAM 20 corresponding to the most recently executed instruction, and the NAND gate 24 detects the combination condition of a specific instruction. N
AND gates 25-27 have a similar configuration. The logical sum of each of these detected conditions is sent to the OR gate 28.
is determined and reported to the processor on signal line 74'.

) The contents of LAM 20 are set as part of initialization when the device is powered on or reset, depending on the trap conditions.

In this embodiment, the instruction code, address modification field,
Although all trap conditions are detected by combinations of and instructions, it is clear that conditions such as master mode/slave mode can be used.

(Effects of the Invention) As explained above, the present invention traps all instructions under specific conditions and executes them on a group of instructions in a specific area.
This has the effect that design obstacles can be avoided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a seventh embodiment of an information processing apparatus according to the present invention. Figures 2 and 3 are detailed block diagrams of the decoder shown in Figure 1. 1...Instruction register 2...Index register 3...Segment register 4...Decoder 5...
...Address adder 6...Virtual address register 7...TLB8...
...Control circuit 9...Instruction counter 10...Counter 11.12...Switching circuit 20...RAM21
...Decoding time, abbreviation 22...Condition detection circuit 23
...Flip frogs 24-27...NAND gate 28...OR gate

Claims (1)

[Claims] a condition detection means for detecting a specific condition from an instruction code of an instruction word and address modification control information; a RAM means for setting the specific condition in a variable state; and the specific condition is detected by the condition detection means. and an execution means for executing an instruction in a predetermined main memory area according to the variable state and acting on behalf of the function of the instruction that detected the specific condition. Processing equipment.