JPS6333408Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a video signal output circuit suitable for use in magnetic recording and reproducing devices (VTR). That is,
In the case of a VTR, when an unrecorded tape is played back, noise appears on the image receiving surface of the monitor, so normally the muting circuit is operated when the control (CTL) signal recorded on the tape is not played back. The video output is muted to prevent noise from appearing on the image receiving surface. Furthermore, even after the power of the VTR is turned on, the above-mentioned muting operation is performed for a certain period of time until the equipment starts operating stably.

On the other hand, in addition to normal playback, VTRs allow various modes such as search mode, slow motion mode, and still mode, but in modes other than these normal playback modes, guard bands are applied to the playback video signal. Noise may be mixed in, and the vertical synchronization signal may be disturbed by this noise, or the vertical synchronization signal itself may not be detected, and the screen may not be vertically synchronized. To prevent this, it is necessary to insert a pseudo synchronization signal, particularly a pseudo vertical synchronization signal, into the video signal reproduced in a mode other than the normal reproduction mode.

In order to achieve each of the above-mentioned objectives, in the past, separate circuits have been provided for each, which has the disadvantage of complicating the circuit and increasing the number of parts.

In view of these points, this invention proposes a common circuit that can achieve both of the above objectives.

An example of a circuit according to this invention will be explained below with reference to FIG. 1 of the drawings. 1 is an input terminal for the video signal reproduced from the VTR, and input transistor 2
It is connected to the Emitsuta. This emitter is grounded through a resistor 3, the collector is connected to a DC power supply terminal 5 (for example, with a DC voltage of +10.5V) through a resistor 4, and the base is connected to the connection point between resistors 6 and 7. It is connected and grounded through a capacitor 8. Note that resistors 6 and 7 are connected in series between power supply terminal 5 and ground.

The collector of this transistor 2 is further connected to the base of an output transistor 9, and the collector of this transistor 9 is connected to a DC power supply terminal 5.
The emitter is grounded through a resistor 10 and connected to an output terminal 12 through a resistor 11. Reference numeral 13 denotes an input terminal for a muting signal, and in a reproduction state, that is, in a CTL signal reproduction state (including various modes), a signal 1 is supplied to the input terminal 13, and a signal 0 is supplied in a state in which a CTL signal is not reproduced. shall be. Reference numeral 14 denotes an input control terminal for a pseudo vertical synchronizing signal, to which control signal 1 is supplied in a normal reproduction state, and control signal 0 is supplied in other reproduction modes. Reference numeral 15 denotes a vertical blanking pulse input terminal, to which vertical blanking pulses obtained from a synchronizing signal oscillation circuit, a rotating servo system of a rotating head (drum), etc. are always supplied.

And vertical blanking pulse input terminal 15
is grounded through a time constant circuit 18 consisting of a capacitor 16 and a resistor 17, and the connection point between the capacitor 16 and resistor 17 is connected to one input end of a NAND circuit 20 through a resistor 19, and an input control terminal. 14 is connected to the other input terminal of the above-mentioned NAND circuit 20 through an inverter 21, and the output terminal of this NAND circuit 20 and the input terminal 13 of the muting signal are connected to each input terminal of an OR circuit 22 which takes a logical sum. , whose output terminal is connected to the muting transistor 2 through the resistor 23.
Connected to the base of 4.

Furthermore, an output level clipping diode 25 and a capacitor 26 are connected between the emitter of the output transistor 9 and the ground to determine the muting level and the sync chip level of the pseudo vertical synchronizing signal.
A series circuit, ie, a clip circuit 28, is connected to the
The connection point between the diode 25 and the capacitor 26 is connected to the emitter of the transistor 24 mentioned above, and the output end of the inverter 21 is also connected to this emitter through a resistor 27. Further, the collector of the transistor 24 is connected to the video signal transmission line, that is, the base of the output transistor 9 in this case.

In this case, the inverter 21, NAND circuit 20, and OR circuit 22 may each be formed of C-MOS.

Next, the operation of the above-described configuration will be explained. It is assumed that a vertical blanking pulse Pa as shown in FIG. 2A is constantly supplied to the vertical blanking pulse input terminal 15. By supplying this pulse Pa to the time constant circuit 18, the capacitor 1
The signal shown in FIG. 2B is connected to the connection point between 6 and resistor 17.
Pb is obtained. The dashed line shown in FIG. 2B is the threshold level of the C-MOS forming the NAND circuit 20 and the like.

In such a configuration, the control signal to the input control terminal 14 is 1 in the normal playback state of the VTR.
Therefore, the output of the inverter 21 becomes 0,
Therefore, the connection point between diode 25 and capacitor 26 is grounded. Also, since the output of the inverter 21 is 0, the output of the NAND circuit 20 is 1,
The input of the OR circuit 22 becomes 0.

On the other hand, the mutating signal 1 is applied to the input terminal 13 of the muting signal (for example, CTL
Since the signal is being regenerated), the OR circuit 22
The input becomes 0, so the output of the OR circuit 22 also becomes 0, and the muting transistor 24 is turned off, so that the output is supplied to the input terminal 1.
The video signal from the VTR is obtained at the output terminal 12 without being muted.

Next, when the muting signal 0 is supplied to the input terminal 13 (for example, if the CTL signal is not regenerated), one input of the OR circuit 22 becomes 1, its output becomes 1, and the muting transistor 24 is turned on. , so that the video signal passing through the signal transmission line is passed through this transistor 24, so that almost all the signal applied to the input terminal 1 is no longer available at the output terminal 12 and is muted.

Furthermore, during playback other than normal playback, for example in a search mode, the control signal to the input control terminal 14 becomes 0, thereby causing the output of the inverter 21 to become 1. The output voltage of the inverter 21 at this time is selected to be about +10V. When the output of the inverter 21 becomes 1, the signal shown in FIG.
Only when Pb is higher than the threshold level, the output of the NAND circuit 20 becomes 0, therefore the input side of the OR circuit 22 becomes 1, and its output side becomes 1 as shown in FIG. 2C. The time width τ of the pulse Pc shown in FIG. 2C can be changed by selecting the capacitance of the capacitor 16 and the resistance value of the resistor 17.

Therefore, in this state, the vertical blanking pulse Pa from the synchronizing signal oscillator supplied to the input terminal 15 or the vertical blanking pulse Pa obtained from the pulse generator (so-called PG) based on the rotation of the rotating head (rotating drum) (Figure 2A)
Within the period τ, the transistor 24 is turned on for a period of τ, and therefore a vertical synchronization signal (actually a pseudo vertical synchronization signal), that is, a timing pulse Pc, is inserted from the outside into the video signal transmitted through the signal transmission line. becomes.

Thereby, even video signals reproduced in modes other than normal reproduction can be monitored without vertical synchronization being disturbed.

In this way, the invention allows a single circuit to perform both the muting operation and the insertion of the pseudo vertical synchronization signal, thereby reducing the number of components and simplifying the overall circuit configuration. It has great features that can be used.

Furthermore, as described above, by configuring the inverter 21, NAND circuit 20, OR circuit 22, etc. with C-MOS, the DC level of the output can be adjusted to, for example, 0 to 10V.
Since it is possible to obtain a wide range of signals, it is possible to directly control the transistor 24, and since no amplifying element is particularly required, the number of components can be further reduced.

[Brief explanation of drawings]

FIG. 1 is a connection diagram showing an example of an output circuit according to this invention, and FIG. 2 is a waveform diagram of its operation. 25 and 26 are diodes and capacitors for output level clipping, 24 is a transistor, and 22 is an OR circuit.

Claims (1)

[Scope of utility model registration request] It has a transistor whose emitter is connected to the series connection point of the video signal output level clip diode and the capacitor, and whose collector is connected to the signal transmission line, and the base of the transistor is connected to the timing signal for the muting signal and the pseudo synchronization signal. 1. An output circuit for a video signal, characterized in that an output end of an OR circuit that calculates a logical sum with a pulse is connected.