JPS63316236A - Interruption control circuit - Google Patents

Abstract

PURPOSE:To attain the execution of a multiple interruption at an edge trigger mode by providing a sequential circuit to convert plural interruption factors into an independent interruption pulse and output them when the plural interrup tion factors are multiply generated. CONSTITUTION:When an interruption factor RXR is generated, an interruption signal INT, since the output of AND gates 11 and 21 is logics '1' and '0', synchronizes to CLK, the output of JK-FF1 and an interruption signal INT go to the logic '1', all the outputs of AND gates 21-23 go to the logic '0' by NOT gates 31-33, and the interruption signal INT is kept, as it is, at the logic '1' so long as the interruption factor RXR exists. Presently when respective factors RXR, TXR, and TXE are generated, sequence is determining by the actions of respective AND gates 11-13, 21-23 are respective NOT gates 31-33, 41 and the interruption signal INT is independently generated to respective interruption factors.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an interrupt control circuit in a microprocessor circuit, and particularly to a rising edge trigger type interrupt control circuit that controls multiple interrupts using a single interrupt line. This invention relates to an interrupt control circuit for

[Conventional technology]

Interrupts interrupt the program being executed by the microprocessor and are sent to the requestor via the interrupt signal line.
This is done to provide emergency services. Generally, interrupts are activated by the interrupt signal line, but there are two types of triggers: one is triggered by the edge (change point) of the interrupt signal line, and the other is triggered by the level of the interrupt signal (logic "1'" level). There are different types. Generally, edge triggers are often used.

The timing of a conventional interrupt control circuit using this edge trigger is generally as shown in FIG.

In Figure 3, TXR and RXR are interrupt factors, and I N
T=TXR+RXR (INT4.logical sum of tTXR and RXR), and when activating an interrupt at the rising edge,
An interrupt is activated at point A, but is not activated at point B because there are no rising edges or edges due to the logical sum with the TXR signal of the interrupt factor. Therefore, the interrupt caused by the interrupt factor TXR is serviced, but the interrupt caused by RXR is masked by the interrupt factors TX, R and cannot be serviced.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional interrupt control circuit using the edge trigger shown in the timing diagram of FIG. 3, when multiple interrupt factors are assigned to one interrupt signal line, each interrupt factor is normally are combined into one interrupt signal by the logical sum of An object of the present invention is to provide a removable interrupt control circuit.

[Means for Solving the Problems] ``The configuration of the interrupt control circuit of the present invention is such that the interrupt control circuit detects interrupts by edge interrupts using a single interrupt signal line for a plurality of interrupt factors. Multiple interrupts in edge trigger mode are possible by providing a sequential circuit that converts and outputs independent interrupt pulses when multiple interrupt factors occur multiple times. It is characterized by

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an interrupt control circuit according to an embodiment of the present invention, and FIG. 2 is a time chart of FIG. 1.

In FIG. 1, 1 to 3 are interrupt factors RXR and TXR.

JK~Flip-flop that holds TXE interrupt request (
(hereinafter referred to as JK-FF), 11-13 and 21-23
is an AND gate, 31 to 33 and 42 are NOT gates, and 41 is an OR gate.

The operation shown in FIG. 1 will be explained below using the timing chart shown in FIG.

When interrupt factor RXR occurs, INT (interrupt signal) becomes A.
Since the outputs of AND gates 11 and 21 are logic "1" and "0" at the point, the output of JK-FFI becomes logic "1" in synchronization with CLK, and the interrupt signal INT becomes logic "1".
becomes.

At this time, the outputs of AND gates 21 to 23 are all logic "o" due to NOT gates 31 to 33, so even if other interrupt factors TXR and TXE occur, the interrupt factor that occurred first will be ignored. Interrupt signal IN until RXR runs out
T remains at logic "1".

Now, as shown in Figure 2, each interrupt factor RXR, TXR and T
If XE occurs, each AND gate 11, 12 .
13 and 21, 22, 23, each NOT gate 31, 3
2. The order of interrupt factors is determined by the operations 33 and 41, and the sequence is A in FIG.

At each point B and C, an interrupt signal INT is generated as a pulse synchronized with an independent clock CLK for each interrupt factor.

In the interrupt controller of a general personal computer,
It is necessary to make effective use of limited interrupt resources. Although this example describes line interrupts, line control LSIs generally handle transmission service requests.

It has three interrupt factors: communication service request and transmission buffer empty request. It is wasteful to make these all correspond to each interrupt signal line as independent interrupt signals, and on the other hand, if they are combined into one signal line using OR, edge detection using edge triggers will not be possible as described above. Cases arise (such as full-duplex communication).

Therefore, the circuit becomes particularly effective in such cases.

〔Effect of the invention〕

As explained above, the present invention provides an edge-triggered interrupt detection circuit with a sequential circuit, so that interrupt signals can be sent to the -tree interrupt generation signal line independently for a plurality of interrupt causes. The effect is that it can be generated.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an interrupt control circuit according to an embodiment of the present invention, FIG. 2 is a time chart of FIG. 1, and FIG. 3 is a time chart of a conventional interrupt control circuit. 1~3...JK-FF, 11~13.21~23...
-AND gate, 31-33.42...NOT gate, 41...OR gate. 1
゜、4-Representative patent attorney Susumu Uchihara.

Claims (1)

[Claims] In an interrupt control circuit that detects interrupts by edge interrupts using a single interrupt signal line, if each of the multiple interrupt factors occurs multiple times, they can be detected as independent interrupts. 1. An interrupt control circuit characterized in that the interrupt control circuit is equipped with a sequential circuit that converts the signal into an input pulse and outputs the signal, thereby making it possible to perform multiple interrupts in an edge trigger mode.