JPS63311882A - Digital electronic still camera - Google Patents

Abstract

PURPOSE:To decrease the memory capacity by dividing a video signal into two field signals, obtaining a difference signal between the 2nd field signal and the 1st field signal, converting the difference signal into a signal with fewer bit number and storing the signal into a memory. CONSTITUTION:A signal selection means 18 dividing a frame video signal outputted from an AD conversion means 14 converting a video signal 104 into a corresponding digital signal 106 into the 1st field signal and the 2nd field signal, and signal conversion means 20, 22 converting the signal into a signal with a few data by comparing the 2nd field signal selected by the signal selection means 18 with the 1st field signal, are provided. Then the 1st field signal selected by the signal selection means 18 and the 2nd field signal converted by the signal conversion means 20, 22 are stored in a semiconductor storage module via a connection means. Thus, in storing the frame video signal, the capacity of the memory attached/detached is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic still camera, and more particularly to a digital electronic still camera in which a video signal representing a still image is stored in a storage device in the form of digital data for each frame.

Background Art For example, in an electronic still camera, a memory is removably connected to a camera body having an imaging optical system and a solid-state imaging device, and a video signal representing a still image captured by the imaging device is stored in this memory in the form of a digital signal. What is done is known. The memory where this video signal is stored is
The video signal is removed from the electronic still camera and loaded into a playback device, and the video signal read from the memory by the playback device is played back as a visible image on the screen of a video monitor.

In such an electronic still camera with a removable memory, when the video signal is a frame signal, each field signal making up the frame signal is stored in the memory.

Generally, the memory capacity required to store one frame of a high-quality digital image signal is on the order of several megabits, and the memory of a digital electronic still camera that stores multiple frames of such image information requires an enormous amount of memory. Therefore, it has the disadvantage of being large and expensive.

the purpose The present invention overcomes these drawbacks of the prior art.

An object of the present invention is to provide a digital electronic still camera that can reduce the capacity of a removable memory when storing frame video signals.

DISCLOSURE OF THE INVENTION According to the present invention, a digital electronic still camera to which a semiconductor memory module to which a video signal representing a still image is stored in the form of digital data of a frame signal is connected is provided with a connection that connects the semiconductor memory module in a circuit. and a solid-state imaging device.

An imaging means for capturing an image of a subject with a solid-state imaging device and outputting a video signal representing the subject, an AD converting means for converting the video signal output from the imaging means into a corresponding digital signal, and an AD converting means. Signal selection means for dividing the video signal of the output frame signal into a first field signal and a second field signal, and comparing the second field signal selected by the signal selection means with the first field signal. The first field signal selected by the signal selection means and the second field signal converted by the signal conversion means are transmitted to the semiconductor memory via the connection means. It is stored in the module.

Embodiments of the digital electronic still camera according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an embodiment of a digital electronic still camera according to the present invention.

The camera of this embodiment includes a camera 10 having an image sensor 12, and a memory 30 connected to the camera 10 via a connector 32. In the same figure, the elements on the left side from the connector 32 are mounted in a single housing as a digital electronic still camera.

The memory 30 is, for example, a "module" such as an SRAM semiconductor memory integrated circuit (IC) card or cartridge.
It is a rewritable digital storage device installed in the form of a data input line 118 for odd-numbered fields, an input line 120 for data to even-numbered fields, an output line 122 for data from odd-numbered fields, and address, read/write. Control lines 142 including enable, chip select, strobe, clock, etc. are connected to camera 10 via connector 32. Note that the connector 32 may include a power supply line for the memory 30.

As the image sensor 12, a solid-state imaging device such as a CCN or a MOS is advantageously applied. The image sensor 12 is controlled from the control circuit 28! A control signal sent through the Ji 12B reads out a video signal to its output 102 in synchronization with a clock supplied from a synchronization circuit (not shown). An even field and an odd field of one field of video signal for each frame are alternately read out to the output 102. Output 102 of image sensor 12 is input to signal processing circuit 14 .

The signal processing circuit 14 color-separates the video signal of the input 102,
For example, necessary adjustments such as white balance adjustment and gradation correction.
This is a video signal processing circuit that performs 5L image signal processing on this and outputs it to its output 104. Output 104 is input to AD converter 16. Note that this signal processing circuit 14 is omitted and the output 102 of the image sensor 12 is directly used as A.
It may also be input to the D converter 18. In the case where the signal processing circuit 14 is omitted, the signal processing circuit may be provided, for example, in the reproduction installation described later.

The AD converter 16 is a signal conversion circuit that converts an analog video signal at its input 104 into 8-bit digital data in this embodiment and outputs it to its output 10B. The output 106 is connected to the signal line 1 via the switch circuit 18.
It is selectively output to either 0B or 110. The switch circuit 18 has a function of selectively connecting the output 106 from the AD converter 16 to either the signal line 108 or 110 in response to a control signal 136 from the control circuit 28, as conceptually shown by a dotted line. With this, A.D.
Output 10B from converter 18 is applied to signal line 110 for even fields and to signal line 108 for odd fields.

A signal line 110 to which an even field video signal is supplied is connected to one input of the subtracter 20. The other input of the subtracter 20 is an odd field 3 of a memory 30, which will be described later.
From 0a to signal line 122, connector 32 and signal line 12
The odd field signals read through 4 are input. The subtracter 20 outputs, as an output 112, the difference between the even field and odd field video signals input from the signal lines 110 and 124. Output 112 is input to nonlinear circuit 22 .

The nonlinear circuit 22 is an encoding circuit that nonlinearly converts the 8-bit digital signal as the input 112 from the subtracter 20 and encodes it into a 4- to 5-bit digital signal.

Since the video signals of the odd and even fields forming one frame of the video signal have a very strong correlation and are similar, the difference between the video signals of the even and odd fields determined by the subtracter 20 is as shown in FIG. As shown in the figure, the distribution is mostly at a level close to O. Therefore, in the nonlinear circuit 22, in view of the fact that the input 112 from the subtracter 20 representing the difference between the video signals of the even field and the odd field is mostly distributed in small values close to the O level, as shown in FIG. When the absolute value of the input level is small, the output level is finely changed in response to small changes in the input level, and when the absolute value of the input level is large, the output level is not changed due to small changes in the input level. The output level is changed when the input level changes considerably.

The nonlinear circuit 22 sets the output level in this way, and
Displayed as a 5-bit digital signal. As mentioned above, the input 112 from the subtracter 20 is distributed over small values close to the O level compared to the 8-bit signal of the output 108 from the AD converter IB, so 4 to 5 bits is sufficient. can be displayed.

Output 11B from nonlinear circuit 22 is stored in even field storage section 30b of memory 30 via connector 32.

On the other hand, signal line 1 to which odd field video signals are supplied
08 is connected to the signal line 114 via the switch circuit 26. The output 132 from the code generation circuit 24 is input to the other input terminal of the switch circuit 26 . The switch circuit 28 outputs the output 1 from the code generator circuit 24 in response to a control signal 138 from the control circuit 28, as conceptually shown by a dotted line.
32 or the output 108 from the switch circuit 18 is selectively output to the signal line 114.

The code generation circuit 24 receives the control signal 13 from the control circuit 28.
0, a recording code indicating the standard for conversion from an 8-bit signal to a 4- to 5-bit signal performed in the nonlinear circuit 22 is generated and output as an output 132. In this embodiment, the recording code generated by the code generation circuit 24 is recorded in a vacant portion of the odd field storage section 30a of the memory 30.

Code generation circuit 24 selected by switch circuit 26
Odd field video signals from the recording court or the AD converter 16 are recorded in the odd field storage section 30a of the memory 30 via the signal line 114, the connector 32, and the signal line 1113. As described above, the odd field video signals stored in the odd field storage section 30a of the memory 30 are connected to the signal line 122, the connector 32, and the signal line 12.
4 to the subtracter 20.

The control circuit 28 is a control function section that controls the operation of the entire device in response to the instruction signal 144 from the operation display section 38, and the control signal is sent to the image sensor 12 via the control line 12B and the control line 128. to the signal processing circuit 14 via
The control line 1 is connected to the code generation circuit 24 via the control line 130.
34 to the AD converter 1B, a control line 138 to the switch circuit 18, and a control line 138 to the switch circuit 26, respectively. The control circuit 28 also monitors the status of each part of the device using these control lines.

The control circuit 28 also writes to the odd field storage section 30a and the even field storage section 30b of the memory 30,
It also has a function of controlling reading from the odd field storage section 30a, and a control line 140 including write and read address, enable, chip select, clock, etc. is connected to the connector 32.

The control circuit 28 is advantageously implemented in a processing system, to which is connected, for example, a memory (not shown) for storing various data and programs.

The operation display section on the 3rd shows the shirt release button and automatic/
This device has various manual operation buttons such as manual settings, exposure settings, and self-balance adjustment, and has the function of inputting operator instructions to the device and providing these to the control circuit 28 via the signal line 144. It has a display function that receives a signal indicating the status of the device from the signal line 144 and displays it to the operator.

Explain the operation.

The memory 30 is attached to the camera 10 via the connector 32, and the operation display section 38 is operated to perform photographing operations of the subject.

One frame of video signal 102 consisting of an odd field and an even field is output from the image sensor 12 to the signal processing circuit 14. Signal processing such as color separation is performed in the signal processing circuit 14, and its output 104 is input to the AD converter 18. Input 1 in AD converter 16
04 is converted into a digital signal, and its output 10 days consisting of odd and even fields is output to the switch circuit 18.

When an odd field video signal is output from the An converter 16 to the switch circuit 18, the control circuit 2B puts the switch circuit 18 into the illustrated connection state via the control line 136. Therefore, the odd field video signal is transmitted through the switch circuit 18 and the control line 108.

The signal is sent to the switch circuit 26. At this time, the switch circuit 26 is connected to the control line 138 from the control circuit 28 in a state opposite to that shown in FIG. Therefore, AD converter 16
The odd field video signal output from the switch circuit 26 and the signal line 114 . Connector 32. The data is stored in the odd field storage section 30a of the memory 30 via the signal line 118. When an even field video signal is output from the An converter 16 to the switch circuit 18, the control circuit 28 connects the switch circuit 18 to the opposite connection state as shown in the figure via the control line 13B. Therefore, the even field video signal is sent to the subtracter 20 via the signal line 110 during the switch circuit. At this time, from the control circuit 28 to the control line 140. Connector 32. Odd field storage section 3 of memory 3o is controlled by a control signal sent to memory 30 through control line 142.
The odd field video signals stored immediately before 0a are sent to the signal line 122, connector 32 . It is read out via the signal line 124 and input to the other input of the subtracter 20.

The subtracter 20 subtracts the odd field video signal read from the memory 30 from the even field video signal sent from the AD converter 18, and outputs the difference signal to the nonlinear circuit 22. The nonlinear circuit 22 converts this differential 8-bit digital signal into a 4- to 5-bit digital signal as described above, and connects the signal line 11Ei, connector 32,
The data is stored in the even field storage section 30b of the memory 30 via the signal line 120. Therefore, the even field storage section 30b stores even field signals based only on the difference from the odd field signals.

The control circuit 2 sends a control signal to the code generation circuit 24 via the control line 130 at a time other than storing the above-mentioned odd field and even field video signals, for example, before storing the video signal, and outputs a control signal to the nonlinear circuit 22. 4~ held in
A recording code indicating the standard for conversion to a 5-bit digital signal is generated. At this time, the control circuit 28 connects the control line 138
A control signal is sent to the switch circuit 26 via the switch circuit 26 to bring the switch circuit 26 into the illustrated connection state. Therefore, the recording code output from the code generation circuit 24 is transmitted to the odd field storage section 30a of the memory 30 via the switch circuit 2.
is memorized. The recording code stored in the memory 30 is read out during reproduction and used to restore the even field differential signal stored in the even field to the original 8-bit signal.

The video signal stored in the memory 30 in the apparatus of this embodiment is reproduced by a reproduction apparatus such as that shown in FIG. 2, for example. The playback device 200 has a connector 40 to which the memory 30 is detachably connected, so that its read data line 150 is connected to the input 152 of the representative value setting circuit 44, and its read data line 15B is connected to the input 158 of the switch circuit 48. be done. Further, the control line 182 is connected to the control circuit 58 via the connector 40.

In the representative value setting circuit 44, the switch circuit 4 is connected to the control circuit 5.
8, the odd field storage section 30 of the memory 30 is connected to the opposite connection state as shown.
A recording code 30c is input from a. The representative value setting circuit 44 converts the 4- to 5-bit even field differential video signal read from the even field storage section 30b of the memory 30 into an 8-bit differential signal using the recording code, and outputs the signal to the adder 46. do.

Next, the switch circuit 48 receives the control signal 1 from the control circuit 58.
The 8-bit odd field video signal read from the odd field storage section 30a of the memory 30 is input to the adder 46.

The adder 4B adds the even field difference signal from the representative value setting circuit 44 and the odd field signal read out from the memory 30, creates an even field video signal, and adds the even field signal to the even field in the monitor memory 50. Storage section 50
Store it in b.

On the other hand, the odd field video signal read from the odd field storage section 30a of the memory 30 is stored in the odd field storage section 50a of the monitor memory 50.

Output 16B of even field storage section 50b and output 16 of odd field storage section 50a of monitor memory 50
8 are connected to the switch circuit 52, respectively. The switch circuit 52 selects either of these two outputs 168 and 1Ei8 according to the control signal 17B from the control circuit 58 and inputs it to the input 170 of the DA converter 54. Therefore, by switching the switch circuit 52, the even field and odd field video signals are input from the even field storage section 50b and the odd field storage section 50a of the monitor memory 50 to the DA converter 54, respectively.

[) The A converter 54 receives the control signal 178 from the control circuit 5.
converts the even field and odd field video signals input to the input 170 into analog signals, and outputs the output 172 to the video monitor 56.

In this way, the playback device 200 reads out the even field difference signal and the odd field signal from the memory, creates an even field signal from the even field difference signal and the odd field signal, and displays the video together with the odd field signal. Output to monitor 56.

According to the digital electronic still camera of this embodiment, as described above, the odd field signals are stored as they are in the memory 30, but the even field signals are obtained by calculating the difference signal from the odd field signals, and this difference signal is used as the original. Considering that the value is smaller than that of the signal, the signal is converted into a signal with a smaller number of bits and stored in the memory 30. Therefore, the capacity of the memory for storing even field signals can be reduced.

During playback, odd field signals are stored in the memory 30.
The signal read from the memory 30 is used for display as is, and the even field signal is converted back to an 8-bit signal using the recording code read from the memory 30, and then added to the odd field signal to form the original. An even field video signal is created.

In the above embodiment, when storing an even field video signal in the memory 30, the difference between the even field video signal and the odd field signal is calculated, and the signal is converted into a signal with fewer beeps and then stored. The field signals and the odd field signals may be reversed. That is, the even field video signal may be stored as is in the memory 30, and the odd field signal may be stored after calculating the difference from the even field signal and converting it into a signal with a smaller number of bits.

Further, in the above embodiment, the recording code is stored in the odd field storage section 30a of the memory 30, but it is stored in an empty portion of either the odd field storage section 30a or the even field storage section 30b. All you have to do is make it so.

Effects According to the present invention, the first field signal is stored in the memory as it is, but the second field signal is calculated as a difference signal from the first field signal, and this difference signal is converted into a signal with a small number of bits. It converts it into a signal and stores it in memory. Therefore, the capacity of the memory for storing the second field signal can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing an embodiment of a digital electronic still camera according to the present invention, and FIG. 2 shows an example of the configuration of a playback device that plays back a video signal stored in a memory by the device shown in FIG. 3 is a graph showing the relationship between the input and output of the nonlinear circuit in FIG. 1, and FIG. 4 is a graph showing the relationship between the output level of the subtracter in FIG. 1 and its probability density. It is a graph. Explanation of symbols of main parts 12, Image sensor 1B, AD converter 18.2B, Switch circuit 20, Subtractor 22, Nonlinear circuit 24, Code generation circuit 28, Control circuit 30, Memory 30a, Odd field storage 30b, Even field storage 44, Representative value setting circuit 4B, Adder 50, Monitor memory 54, DA converter patent applicant Fuji Photo Film Co., Ltd. Managing Director Number: Takao Mitsushige Takao

Claims (1)

[Scope of Claims] 1. A digital electronic still camera to which a semiconductor storage module is connected, in which a video signal representing a still image is stored in the form of digital data of a frame signal, the camera comprising: a connection means connected to the camera; an imaging means having a solid-state imaging device, imaging a field with the solid-state imaging device and outputting a video signal representing the field; and a video signal output from the imaging means. AD conversion means for converting a frame signal into a corresponding digital signal; signal selection means for dividing a video signal of a frame signal outputted from the AD conversion means into a first field signal and a second field signal; and by the signal selection means. signal conversion means for converting the selected second field signal into a signal consisting of less data by comparing the selected second field signal with the first field signal, the first field signal selected by the signal selection means; A digital electronic still camera characterized in that the signal and the second field signal converted by the signal converting means are stored in the semiconductor storage module via the connecting means. 2. The camera according to claim 1, wherein the signal converting means converts the second field signal and the first field signal into
1. A digital electronic still camera, comprising: subtraction means for determining the difference between a field signal and a field signal; and signal compression means for compressing the output from the subtraction means into a signal with a small number of bits. 3. In the camera according to claim 2, the signal compression means is configured to compress the second signal outputted from the subtraction means.
A digital electronic still camera, characterized in that the digital electronic still camera is a nonlinear circuit that nonlinearly converts a signal representing the difference between the field signal and the first field signal into a signal with a small number of bits. 4. The camera according to claim 2, further comprising code generating means for generating a code used when compressing the signal from the subtracting means in the signal compressing means, A digital electronic still camera characterized in that a code generated from a generating means is stored in the semiconductor storage module via the connecting means.