JPS63311460A - Bus control system - Google Patents

Abstract

PURPOSE:To set an arbitrary error state without inserting an artificial fault by a person's help, by transmitting the contents of a status register instead of original status information, when a mode register is in a test mode. CONSTITUTION:When a mode register 94 is in a test mode, the generation of an arbitrary abnormal state can be simulated by setting a suitable value to a status register 95. An operation mode of the mode register 94 and a report opportunity and status information of the status register 95 and set before executing each test, by a test mode setting command instructed to a bus control part 9 of an input/output controller 5 from a bus control part 9 of a central processing unit 2 being an executing processor of a test program. In such a way, an arbitrary error state can be set.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus control method for a bus control unit included in a processing device connected to a common bus, and particularly relates to a method for generating a pseudo failure in the bus control unit and the processing device. .

[Conventional technology]

Conventionally, as a method for generating a pseudo fault in a processing device connected to this type of common bus, a method of manually inserting a fault has been a common method.

[Problem that the invention seeks to solve]

The conventional system test using the above-described manual method of manually inserting pseudo faults has the disadvantage of being inaccurate because it increases the test time and is prone to human errors.

[Means for solving problems] The bus control method according to the present invention is as follows.

In an information processing system comprising a plurality of processing devices connected by a common bus and having a bus control unit that controls the common bus.

The bus control section has an operation mode register that stores a test operation mode, and a status register that stores a response status during the test operation.

In the response cycle when receiving information to the own bus control unit, if the operation mode register is in normal mode, the original status information set by the functional firmware of the own processing device is transmitted, and if the operation mode register is in test mode. is characterized in that the content of the status register is transmitted instead of the original status information.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a system block diagram showing a bus control method according to an embodiment of the present invention. In Figure 1, the common bus l
A central processing unit 2, a main storage device 3, and an input/output control device 5 are connected to the system.

Each device has the same bus control section 9.

FIG. 2 is a block diagram of the bus control section 9 shown in FIG. 1. In FIG. 2, the bus control section 9 includes a common bus control section 91 that sends and receives information to and from a common bus l, and an internal bus of each device (in FIG. 2, the bus control section 9 is a component).
Since the input/output control device 5 has been explained, an internal bus control section 93 that sends and receives information to and from the internal bus 51) is connected to the common bus control section 91 and the internal bus control section 93, and is connected to the bus control section 9. Consisting of a control section 92 that performs overall control, a mode register 94 that stores the operating mode of the bus control section 9, and a status register 95 that stores response status information when the mode register 94 is in the diagnostic mode. has been done.

The basic operation of communication on the common bus 1 is a request cycle in which a request source transmits requested operation information to a request destination.

It consists of a response cycle in which the request destination reports the result to the request source, and each cycle consists of a request phase and a reply phase.

The operation of the bus control unit 9 when the central processing unit (hereinafter referred to as EPU) 2 shown in FIG. 1 executes an IO command to the input/output control unit (hereinafter referred to as IOC) 5 will be described in detail.

On the common bus l, EPU 2, in the request cycle,
When the information shown in FIG. 3(1) is sent out, the common bus control section 91 of the bus control section 9 of the l0C5 receives it and transmits it to the control section 92. The control unit 92 checks the request source information among the information shown in FIG. 3(1), and if it recognizes that the request is for its own device, it checks whether the request can be accepted. During the information reception operation, if there is a parity error and the information cannot be received, the control unit 92 does not perform the information storage operation and sets the error status in an internal register (not shown). The error status is notified to the EPU 2 via the common bus control unit 91. When the information can be accepted and the control unit 92 sets the information to the internal register, the request phase is completed and the bus control unit 9 returns to the common bus l as a rewrite phase.
and complete the request cycle.

After the request cycle is completed, the functional firmware (not shown) of the IOC 5 instructs the bus control unit 9 to read the received information, and the control unit 92 transmits the information to the internal bus 51 through the internal bus control unit 93.Function Firmware will be updated after receiving the information.

Determine whether the instructed to request can be executed.

After preparing a normal code as a result status if possible, and preparing an error code as a result status if it is not possible, a message is sent to the control unit 92 via the internal bus 51 and internal bus control unit 93 as shown in FIG. ) to instruct the activation of a response cycle. The control unit 92 transmits the information to the common bus 1 via the common bus control unit 91.
Send to U 2 and start the request phase.

When the EPU 2 completes the reception operation normally, it transmits the address information shown in FIG. end.

As is clear from the above description, the occurrence of an abnormality in the IOC 5 is reported as an error status in the request phase of the request cycle, or as a result status in the request phase of the response cycle.

The above operation is similar to the common bus control in the prior art, and in the system of this embodiment, the mode register 94 in FIG. 2 controls the bus control section 9 in the normal mode.

Next, the bus control operation when the mode register 94 of the IOC 5 is in the test mode will be explained.

When the 10C5 receives the information shown in FIG. 3(1) in the request cycle, the control unit 92 recognizes that the request is for its own device, and checks the contents of the status register 95 shown in FIG. If the reporting trigger is a request cycle, the status information in the status register 95 is set as an error status in an internal register without checking whether the request can be accepted, and the error status is notified to the EPU 2. If the reporting trigger is a response cycle, the above processing is performed in the same manner as in 1 normal mode.

The control unit 92 completes the request cycle, and the functional firmware of the l0C5 performs the same operation as in the normal mode, transmitting the information shown in FIG. The unit 92 stores the status information in the status register 95 at the start of the response cycle as shown in FIG.
3) Overwrite the result status and perform the subsequent processing.

Therefore, mode register 94 is in test mode.

By setting an appropriate value in the status register 95, the occurrence of any abnormal state can be simulated.

The operating mode of the mode register 94 and the reporting trigger and status information shown in FIG. It is set before each test is executed by a test mode setting command instructed to section 9.

〔Effect of the invention〕

As explained above, the present invention includes a mode register that stores an operating mode in a bus control section provided in each of a plurality of processing devices connected by a common bus.

A status register is provided to store the response status of the common bus, and when the mode register i:E is in the test mode, the content of the status register is sent instead of the original status information, thereby preventing one person from simulating a failure. This has the effect of allowing you to set any error status without inserting it.

[Brief explanation of drawings]

FIG. 1 is a system block diagram showing a bus control method according to an embodiment of the present invention, FIG. 2 is a block diagram of the bus control unit in FIG. 1, and FIG. 3 is information communicating on the common bus in FIG. 2. FIG. 4 is a diagram showing the contents of the status register in FIG. 2. l...Common bus, 2...Central processing unit (EPU)
, 3... Main storage device, 5... Input/output control device (
IOC), 9...Bus control unit, 91...Common bus control unit, 92...Control unit-93...Internal bus control unit, 94...Mode register, 95...Status register t51 ...Internal bus of input/output control device. tN1 diagram Figure 2

Claims (1)

[Claims] 1. An information processing system comprising a plurality of processing devices connected by a common bus and having a bus control unit that controls the common bus, wherein the bus control unit stores a test operation mode. It has an operation mode register that stores the response status during test operation, and a status register that stores the response status during test operation.If the operation mode register is in the normal mode in the response cycle when receiving information for the own bus control unit, the self-processing device A bus control method characterized in that original status information set by functional firmware is transmitted, and when the operation mode register is in a test mode, the contents of the status register are transmitted instead of the original status information.