JPS6331024B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an automatic transmission control device for an automobile, and more particularly, the present invention is equipped with an abnormality detection means for detecting an abnormality in a signal pick-up line, a processing circuit, etc. used for determining a speed change. The present invention relates to an automatic transmission control device that performs set abnormality protection. A normal automatic gear shift control system has a control circuit that receives a vehicle speed response signal and a signal corresponding to engine output torque or a throttle opening response signal as input signals, compares and calculates these two signals, and outputs a transmission gear shift operation control signal. . This vehicle speed response signal is supplied, for example, by a known reed switch type vehicle speed sensor that detects the rotation speed of the drive shaft. This reed switch type vehicle speed sensor uses a magnet MG that rotates according to the rotation of the drive shaft.
It operates ON-OFF, and a constant voltage is applied between both terminals, emitting constant voltage pulses at a frequency that corresponds to the drive shaft rotation speed. This vehicle speed sensor is placed near the drive shaft or inside the speedometer, and the output signal line leading to the control circuit may be disconnected. In this case, the same output signal as when the vehicle is stopped is usually generated. For example, in the case of a reed switch with one end connected to the body ground and the other end connected to a constant voltage circuit, a constant voltage non-pulse continuous signal is generated, which is the same signal as when the vehicle is stopped. In such a case, the control circuit of the automatic transmission control system will determine that the vehicle has stopped.
A transmission control signal is issued to shift to a gear shift position (for example, 1st gear) at low speeds, but if the vehicle is traveling at high speed and is suddenly shifted to a higher speed, a sudden sudden engine brake will be activated. death,
The shock is large and dangerous, and there is a risk of transmission or engine failure. This problem can be solved by a system that is equipped with an abnormality detection means that detects an abnormality in the signal loop from the judgment reference index detection means to the control circuit that makes the gear change judgment, and sets and locks the automatic transmission to a safe speed gear in the event of an abnormality. This can be improved by changing the configuration. However, depending on the driving situation of the vehicle, a signal similar to that in an abnormal state may appear even if the signal loop is normal. For example, if the wheels stop due to sudden braking while driving at high speed, the vehicle speed signal will be at a low level similar to when the signal loop is broken or the vehicle is shortened.
In such a case, it is preferable to smoothly release the abnormality setting (lock) of the abnormality detection means and control circuit. SUMMARY OF THE INVENTION An object of the present invention is to lock an automatic transmission to a safe speed gear in response to an abnormality in a vehicle speed pulse signal system, and to automatically release the lock in response to the signal system returning to normal. In order to achieve the above object, the automatic transmission control device of the present invention includes: a vehicle speed detection means that generates a pulse signal corresponding to the vehicle speed; a vehicle speed processing means that generates vehicle speed information based on the pulse signal; and a differential value of the vehicle speed information. Abnormality detection means that calculates and enters an abnormality detection state when the differential value indicates a decrease in vehicle speed of a predetermined speed or more; an engine power indicator signal such as an engine output torque corresponding signal, a throttle opening signal, the vehicle speed information, and the abnormality detection state. a speed change control means for determining a speed gear of the automatic transmission in response to the abnormality detection state; a comparison means for comparing the vehicle speed condition with predetermined vehicle speed information to determine whether the former is greater than or equal to the latter; and the comparison means and a reset means for canceling the abnormality detection state of the abnormality detection means when it is determined that the vehicle speed information is equal to or higher than the predetermined vehicle speed information. As a result, when the vehicle speed information signal line is abnormal, the automatic transmission is forcibly locked into a safe speed gear, and after the signal becomes normal, the gear gear is set in accordance with the driving condition. Even if the automatic transmission is forcibly locked to a safe speed gear in a special driving situation such as sudden braking, the lock will be automatically released when normal driving resumes. In the present invention, a comparison means compares the vehicle speed information with predetermined vehicle speed information in an abnormality detection state and determines whether the former is greater than or equal to the latter; and when the comparison means determines that the vehicle speed information is greater than or equal to the predetermined vehicle speed information, Since the vehicle is equipped with a reset means for canceling the abnormality detection state of the abnormality detection means, when the vehicle recovers from the abnormal state, the abnormal state is automatically reset when the vehicle speed information indicates a predetermined vehicle speed or higher. As a result, the time from abnormality recovery to reset corresponds to the vehicle speed. Therefore, when the vehicle speed is low (the period of the pulse signal is long: it is difficult to determine normality/abnormality), automatic reset is not performed, making it difficult for the automatic reset function to malfunction. On the other hand, when the vehicle speed is relatively high (the period of the pulse signal is short: it is easy to judge normality), an automatic reset is activated in a short time and the speed range is lower than the set safe speed gear in response to the abnormality.
The speed gear can be switched to the required speed corresponding to the current vehicle speed at an early stage, improving driving performance. In this way, a rational automatic reset operation is performed in accordance with the vehicle speed. Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In this case, a vehicle speed sensor 31 is a vehicle speed response signal generating means, an FV (frequency-voltage) converter 32 is a vehicle speed signal processing device, a throttle opening detection circuit 33,
The abnormality detection circuit 40, the reset circuit 41, and the shift control device 42 constitute the automatic shift control device of the present invention, which controls the gear position of the automatic transmission 45. Each part shown in FIG. 1 will be explained in detail below. Reed switch of reed switch type vehicle speed sensor 31
The + side of the LSW is connected to the input terminal of the FV conversion circuit 32, and one terminal is grounded to the vehicle body.
The magnet MG rotates according to the rotation of the drive shaft, and the reed switch LSW turns ON and OFF at a frequency that responds to the vehicle speed.
A constant wave high pulse signal appears at the terminal L of the FV conversion circuit 32 due to the circuit configuration in which the lead switch LSW is connected in parallel to the FV conversion circuit 32. The FV conversion circuit 32 is well known and a detailed explanation will be omitted, but it includes transistors T _r 1 to _{T r} 3, diodes D1 to D4,
It consists of resistors R1 to R10 and capacitors C1 to C4, and has shaping, differentiation, integration, and buffer circuits sequentially from the signal input terminal side, and its output terminal is connected to the + side V _s2 terminal, which is common to the control circuit, through resistor R10. It consists of the emitter terminal A of a pnp transistor T _r 3 (for buffer, collector grounded) connected to the terminal. Note that one terminal of the FV conversion circuit 32 is grounded to the body. The + terminal (output terminal) of the reed switch of the vehicle speed sensor 31 is connected to the FV conversion circuit 32
The diode D1 terminal inside is connected as an input terminal. The output terminal A of the FV conversion circuit 32 is connected to the − input terminal of the comparator IC1 of the comparison circuit 43. The throttle opening detection circuit 33 has signal pressures V _B , V _C , V _D corresponding to three stages of throttle opening, respectively.
It has OR circuits D7 to D9 on its output end side for selectively supplying signal voltages V _B , V _C , and V to the comparator IC1 of the comparison circuit 43 via diodes D9, D8, and D7, respectively. _D is the second stage constant voltage V _s2
and the ground terminal with two resistors R25 and R2, respectively.
6. The pressure is divided by R21 and R22, R14 and R15. However, each voltage dividing terminal is connected to a comparator via resistors R17, R24, and R28, respectively.
Connected to output terminal G of IC1 (positive feedback)
Therefore, each divided voltage terminal voltage V _B , V _C , V _D is determined by three resistors R25, R26, R28; R21, R22, R
24; Generates three different signal pressures of V _B < V _C < V _D basically defined by R14, R15, and R17. Of these three throttle opening response pressure output terminals B, C, and D, terminal B is only connected to ground via resistor R26, but terminal C (throttle opening second stage) is composed of transistor TR5. The switch circuit SW1 is grounded through the switch circuit SW1, which conducts to ground when closed, and the bias voltage input terminal C' of the switch circuit SW1 is connected to the throttle opening detection switch.
Grounded via VSW (e.g. vacuum switch for negative pressure detection in engine intake system), and constant voltage circuit (hereinafter referred to as + side) via resistor R18.
Connected to V _s2 . Terminal D, like terminal C, is connected to ground via switch circuit SW2.
Switch circuit SW consisting of 4 transistors T _r
The bias voltage input terminal D' of No. 2 is connected to ground via another throttle opening detection switch ASW (for example, an accelerator position detection switch or a switch with a different operating point of the same type as VSW), and is connected to the + side via the other resistor R11. Connected to V _s2 . A Zener diode DZ (reverse direction) is connected to the ground in parallel with the capacitor C5 to the + side _Vs2 of the output torque corresponding signal E〓 forming circuit 33. Switch circuit SW1 is the npn type transistor
The emitter of T _r 5 is grounded, and the collector is connected to the voltage dividing terminal C. Base is diode D6
(in the opposite direction), the capacitor C7 and the resistor R20 are connected in parallel to ground, and on the other hand, the resistor R19 is connected to the terminal C', and then the resistor R18 is connected to the +
Connected to side V _s2 . The switch circuit SW2 is
It consists of an npn type transistor T _r 4, whose collector is connected to the voltage dividing terminal D, and whose base is connected to the terminal D' via R12 and the + side V _s2 via the resistor R11, while the diode D5 and the capacitor C6
and a resistor R13 connected in parallel. The outputs of the diodes D7 to D9 constituting the OR gate are applied to the comparator 43 as the throttle opening signal E. Switch ASW, VSW is shown in Table 1 below.
This shows the relationship between the opening and closing of and the voltage level of E〓.

[Table] The - input terminal of the comparator IC1 of the comparator 43 receives the output of the FV conversion circuit 32, that is, the vehicle speed signal V _A
However, the throttle opening signal E is applied to the + input terminal. Output terminal G of comparator IC1 is + side
V _s2 via a resistor R30 (second stage + side V _s2 ), this second stage + side V _s2 is further connected in series to the first stage + side V _s1 via a resistor R31,
On the other hand, a diode D12 and a resistor R32 are connected in parallel to the series resistors R30 and R31 of the solenoid driver 44 to the + side (first stage) V _s1 . Note that the conventional + side or constant voltage circuit V _s2 is connected to the output terminal K of this resistor R31. Also, this first stage + side V _s1 is connected to + via diode D16.
Connected to constant voltage power supply. Series resistors R33 and R3 are connected to the first stage + side which is the output side of the diode D16.
The collector terminal of the npn transistor T _r 6 is connected through the terminal 4, and the emitter terminal of the transistor T r 6 is grounded.
The base terminal is connected to the resistor R through the diode D13.
32 and the terminal between diode D12. The base terminal of the transistor T _r 6 is also grounded via a resistor R35, and from its collector terminal it is connected via a resistor R34 to an npn transistor T _r
Connected to the base terminal of 7. Transistor T _r
The emitter terminal of 7 is connected to the first stage + side V _s1 ,
A diode D17 and a coil of a shift solenoid valve SSV of the automatic transmission 45 are connected in parallel to the collector terminal, and the other ends of these are grounded.
The automatic transmission 45 is a known solenoid-controlled two-speed transmission. Next, the abnormality detection circuit 40 will be explained. In the abnormality detection circuit 40, a capacitor C9 differentiates the vehicle speed analog signal V _A , and the differential signal is sent to a comparator.
Give it to the - input terminal of IC2. On the other hand, V _s2 is R36,
It is applied to the series circuit of R37 and R38, the divided voltage (constant voltage) of R38 is applied to the capacitor C10, and the voltage of the capacitor C10 is applied to the comparator IC.
It is applied to the + input terminal of 2. Comparator IC2
Since the sum of the voltage drops of resistors R37 and R38 is applied to the - input terminal of , via resistor R39, the voltage at the - input terminal of comparator IC2 is normally higher than the voltage at the + input terminal, and the output of comparator IC2 is at a negative level and the output transistor T _r8 is off. During normal acceleration/deceleration, the rate of change in vehicle speed is small, so the rate of change in vehicle speed signal V _A is small, and capacitor C9 does not substantially generate a differential signal. However, when the reed switch LSW is disconnected or shorted, or when the wheels lock due to sudden braking on a low-friction road, the driving response pulse is interrupted, so the vehicle speed signal
V _A decreases at the fastest speed determined by the time constants of resistors R8 and R9 and capacitors C3 and C4 of the FV conversion circuit 32, and at this time, the potential of the comparator IC2 side electrode of differential capacitor C9 decreases, and the output of comparator IC2 becomes positive. level, and transistor T _r8 becomes conductive. When T _r8 conducts, the resistance R40
and comparator IC2 through diode _D18
The negative input terminal of is held at a low potential, so that the output of comparator IC2 remains at a positive level,
Transistor T _r8 remains on (abnormality detection state). Since the collector of the transistor T _r8 is connected to the base of the transistor T _r6 of the solenoid driver 44 through the diode _D19 , the transistor T _r6 is locked off in the abnormality detection state. To summarize the above, the gear settings of the automatic transmission 45 are shown in Table 2 below.

[Table] Next, the reset circuit 41 will be explained. The output voltage of the comparator IC1 is applied to the base of the npn transistor _Tr9 of the reset circuit 41, and the collector of the transistor _Tr9 is connected to the negative input terminal of the comparator IC2 of the abnormality detection circuit 40 via the capacitor C11 and the diode _D19 . ing. When _{the abnormality detection circuit 40 is in a normal state, the output of the comparator IC2 is at a negative level and the transistor T r8 is} off.
Since the diode _D19 is inserted between the two, the - input of the comparator IC2 is at a positive high level (voltage higher than the voltage of C10) regardless of whether the transistor _Tr9 is on or off. Turning on and off of T _r9 due to positive and negative fluctuations in the output of IC1 does not cause a state change in the abnormality detection circuit 40. However, in the event of an abnormality, the transistor T _r8 of the circuit 40 is on as described above, and since V _A is low, the output of IC1 is positive and the transistor T _r9 is conductive. Thereafter, when the level of V _A increases and E〓<V _A , the output of the comparator ICI turns negative, which turns off the transistor T _r9 . This causes the collector potential of transistor T _r9 to rise, which is applied to the comparator of circuit 40 via capacitor C11 and diode _D19 .
It is applied to the negative input terminal of IC2, the output of the comparator IC2 turns negative, and the transistor T _r8 turns off. In other words, in the abnormality detection circuit 40, comparator IC2 - transistor T _r8 - diode
The loop of D ₁₈ - resistor R ₄₀ - comparator IC2, that is, the abnormality set loop, is reset and the abnormality detection circuit returns to the normal state, and in the device 42, the ground level lock (off-lock) caused by turning on transistors T _r6 and T _r8 is released, Comparator IC
Transistor T _r6 turns on according to the output polarity of 1,
It starts to turn off. The reset conditions for the circuit 40 described above, E〓<V _A , E〓=V _B , V _C or V _D , mean that the vehicle speed signal has returned to a predetermined level or higher, that is, the signal line has returned to normal. . In the reset circuit 41, the transistor T _r9 may be replaced with a pnp type transistor, and the vehicle speed signal V _A or its divided voltage may be applied to its base. Alternatively, the circuit 41 may be provided with a comparator so that the voltage V By comparing _A with a given reference voltage, V _A
transistor on the condition that it rises above a predetermined level
T _r9 may be turned off. In the embodiment shown in FIG. 1, the comparator is IC1.
It can be said that it is shared as As shown in Table 2, the reason why the gear stage is set to 2nd speed when an abnormality is detected is that if a wire breakage or short occurs between the terminal L and the sensor 31 during high-speed driving (2nd speed), This is because if the speed is increased, the vehicle speed changes greatly, which is dangerous for the driver, and may also cause a large impact to the clutch system, engine system, and vehicle drive system. Even if the gear shifts from the first gear to the second gear in the event of a failure or sudden braking, the engine load will increase, so the coupling ratio will be lowered in the clutch control system to prevent a large shock from occurring. FIG. 2 shows another embodiment of the invention. In this case, an electromagnetic induction type vehicle speed sensor 31 is used as a vehicle speed response signal generating means, and a pulse shaping circuit 32a, a counter/latch circuit 32b, and a timer circuit 32c are used as vehicle speed signal processing devices.
In addition, the speed change control device 42 is composed of a microprocessor (1-chip microcomputer) 46 and a solenoid driver 44, and the microprocessor 46 is commonly used as abnormality detection means and reset means. In the vehicle speed sensor 31, a magnetic core around which a sensor coil is wound is arranged opposite to a magnet MG that rotates in accordance with the rotation of the drive shaft. It consists of When the magnet MG rotates, an alternating voltage is induced in the sensor coil, which is transmitted to the pulse shaping circuit 32.
applied to a. In the circuit 32a, the first operational amplifier OP1 inverts and amplifies the input alternating voltage,
The second operational amplifier OP2 performs inverting amplification and level shift adjustment, and the first and second transistors
T _r1a and T _r2a perform binarization and inversion amplification. As a result, a vehicle speed response pulse having a frequency and a pulse width corresponding to the rotational speed of the magnet MG is applied to the mono-multivibrator MM1. The mono-multivibrator MM1 is triggered by the rising edge of the speed detection pulse and outputs a high-level "1" pulse with a constant short width. This makes the mono multivibrator
The output of MM1 has a frequency proportional to the vehicle speed.
Generates a vehicle speed detection pulse with a constant pulse width. The vehicle speed detection pulse is applied to the counter latch circuit 32b via the NAND gate NA1. The counter latch circuit 32b is a 4-bit counter CO
1, CO2, Latch LA1 and Orgate OR1
It consists of a counter for vehicle speed detection pulses.
CO1 counts, and counter CO2 counts the carry pulses of counter CO1. That is,
Counters CO1 and CO2 constitute an 8-bit counter. The count codes of counters CO1 and CO2 are updated and stored in latch LA1 at a predetermined period.
Counters CO1 and CO2 are cleared every time this memory is updated. Therefore, the memory data of latch LA indicates the number of vehicle speed detection pulses during a predetermined period, that is, the vehicle speed. The timer circuit 3 updates the memory of latch LA1 and clears counters CO1 and CO2.
2c controls. The timer circuit 32c counters the oscillation pulses of the pulse oscillator OSC.
The frequency is divided by CO4 and NAND gates NA2 and NA3 to form a latch instruction pulse and a counter clear instruction pulse, and the counter clear instruction pulse is converted into a short pulse by mono multivibrator MM2 to energize latch LA1 (memory update). Next, counters CO1 and CO2 are momentarily cleared. The pulse that clears the counters CO1 and CO2 is applied to the computer 46 as a timing pulse A, and the latch code of latch LA1 is applied to the computer 46 as a vehicle speed indication code _Vc0 . The input port of the microcomputer 46 is
Switch ASW for throttle opening detection and
VSW is connected. The ROM of the microcomputer 46 includes the throttle opening detection circuit 33, the comparator 43, and the comparator 43 of the embodiment shown in FIG.
Program data for performing operations similar to those of the abnormality detection circuit 40, reset circuit 41, etc. and constant data referred to in its execution are stored in advance. FIG. 3 shows the control operation of the microcomputer 46 based on the program data. The control operation of the microcomputer (hereinafter referred to as microcomputer) 46 will be explained with reference to _FIG . Read the data to V _c01 and compare it with the data stored in the speed register, V _c01 −
If V _c0 ≧a, that is, if the speed signal level drops abnormally during one cycle of timing pulse A, it is assumed that the signal line is malfunctioning (including wheels locking during sudden braking), and the solenoid driver 44 is Automatic transmission 45 is activated by setting low level "0" to the output port and turning off transistors T _r6 and T _r7 .
is set to second gear, the abnormality flag is set, and the vehicle speed data _Vc0 just read is updated and stored in the speed register (the above is abnormality detection and setting of the abnormality detection state). Then, the process returns to the main routine, and returns to the beginning of the flow shown in FIG. 3 at the arrival timing of pulse A to wait for the arrival of timing pulse A. When pulse A arrives, the abnormality flag has been set (abnormality flag present? = YES), so first read the opening/closing status of the throttle opening detection switches ASW and VSW, and use the reference data V _B according to the relationship shown in Table 1. , V _C or
Identify V _D and compare the vehicle speed V _CO with it.
If V _CO is higher than that, it is assumed that the motor has returned to normal and the abnormality flag is reset, and the speed register V _c0
The memory is updated and the process returns to the main routine (the above is a reset of normal return detection and abnormality detection status). In normal case, V _c0 −V _c0 ≧a? = NO, is there an abnormality flag? = NO, read the open/close states of the switches ASW and VSW for detecting the throttle opening, and generate constant data V _B , V _C , V _D corresponding to those open/close states, similar to circuit 33 in Fig. 1. of
Read from the ROM and compare it with V _C0 , and based on the magnitude relationship between the two, set the output port to the solenoid driver 44 as high level "1": 1st speed designation signal or low level "0": 2nd speed designation signal. , memorize V _c0 in the speed register and return to the main routine, and at the timing when pulse A appears, return to the beginning of the flow in Figure 3 and wait for the arrival of timing pulse A. settings of). In this embodiment, as described above, the main part of the transmission control device is the microcomputer 46, the abnormality detection means is also the microcomputer 46, and the reset means is also the microcomputer 46.
It is said to be 6. Although the above two embodiments have been illustrated and described, the present invention is not limited only to these embodiments, but may be implemented in other embodiments. For example, a potentiometer type or absolute encoder type throttle opening sensor may be used instead of ASW or VSW, and furthermore, it can be used not only for throttle opening signals but also for intake manifold negative pressure signals, fuel injection amount signals, and other signals. An engine power indicator signal such as a signal corresponding to engine output torque may also be used.
Furthermore, although the automatic transmission has two speeds, it may have three or more speeds, and furthermore, the gear position can be determined based on the ROM based on the throttle opening and vehicle speed.
It may also perform other logic, such as accessing and reading gear instruction data. As described above, the automatic transmission control device of the present invention includes a comparing means that compares the vehicle speed information with predetermined vehicle speed information when an abnormality is detected and determines whether the former is greater than or equal to the latter; Since the reset means is provided for canceling the abnormality detection state of the abnormality detection means when it is determined that the vehicle speed information is equal to or higher than the predetermined speed information, when the vehicle speed information based on the pulse signal becomes the one indicating the predetermined speed or higher when the abnormality state is recovered, The abnormal condition is automatically reset. As a result, the time from abnormality recovery to reset corresponds to the vehicle speed. Therefore, when the vehicle speed is low (the period of the pulse signal is long: it is difficult to determine normality/abnormality), automatic reset is not performed, making it difficult for the automatic reset function to malfunction. On the other hand, when the vehicle speed is relatively high (the period of the pulse signal is short: it is easy to judge normality), the automatic reset works in a short time and the safe speed stage that was set in response to the abnormality is activated earlier. The vehicle is switched to the required speed gear corresponding to the vehicle speed, improving driving performance. In this way, a rational automatic reset operation is performed that corresponds to the vehicle speed.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a block diagram showing another embodiment of the present invention, and FIG. 3 is a flowchart showing the control operation of the microcomputer 46 shown in FIG. SW1, SW2: Switching circuit, ASW,
VSW: Throttle opening detection switch, IC1: Comparator (comparison means), IC2: Comparator,
31: Vehicle speed sensor (vehicle speed detection means), 32, 3
2a to 32c: (vehicle speed processing means), 40: abnormality detection circuit (abnormality detection means), 42: shift control device (shift control means), 41: reset circuit (reset means), 46: microcomputer (abnormality detection means, comparison means, reset means).

Claims (1)

[Claims] 1. Vehicle speed detection means that generates a pulse signal corresponding to the vehicle speed; Vehicle speed processing means that generates vehicle speed information based on the pulse signal; Calculates a differential value of the vehicle speed information and determines whether the differential value is equal to or higher than a predetermined speed. Abnormality detection means that enters an abnormality detection state when a vehicle speed decrease in a speed change control means for determining a speed; a comparison means for comparing the vehicle speed information with a predetermined vehicle speed information and determining whether the former is greater than or equal to the latter when in the abnormality detection state; An automatic transmission control device comprising: reset means for canceling the abnormality detection state of the abnormality detection means when the above is determined.