JPS63308482A - Vertical synchronization signal detection device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] A synchronizing signal is extracted from a video signal, a pulse with a predetermined pulse width is generated using the synchronizing signal, and the pulse and the synchronizing signal are guided to a storage means such as a shift register.

Read the other signal sequentially at one signal timing,
This vertical synchronization signal detection device detects a vertical synchronization signal by determining the contents stored in the storage means.

[Industrial application field]

The present invention relates to a vertical synchronization signal detection device that extracts a synchronization signal from a video signal such as an NTSC system and detects a vertical synchronization signal from the synchronization signal with high accuracy and stability.

In the NTSC system, one screen consists of 525 horizontal scans, and 30 screens are interlaced per second to create and transmit a video signal. The video signal is a brightness signal.

It consists of a color signal, etc., and a horizontal synchronization pulse is superimposed as a horizontal synchronization signal. The vertical synchronization signal section does not include a video brightness signal and transmits only vertical synchronization pulses. This vertical sync pulse has a different pulse width than the horizontal sync pulse. Generally, vertical synchronization signals are separated by utilizing this difference in pulse width. These horizontal and vertical synchronization signals are essential for reproducing the video signal, and it is necessary to transmit them.

In recent years, satellite communication systems have been used that transmit these video signals via repeaters mounted on artificial satellites. In such a satellite communication system, a video signal is first FM modulated and converted into a radio frequency band before being transmitted. In this FM modulation, spread modulation is performed to prevent power from concentrating in a specific frequency band and interfering with other communications 1, such as terrestrial microwave communications. As this spread modulation, a symmetrical triangular wave whose apex coincides with the vertical synchronization part of the video signal is generally used. By superimposing this symmetrical triangular wave on the video signal and applying FM modulation, the power density is made almost uniform within the occupied band. This spread signal is removed on the receiving side, but
It may not be completely removed and some residue will remain. This residual portion causes deterioration of the reproduced video signal, but if the apex of the spread signal coincides with the vertical synchronization portion, the deterioration of the reproduced video signal can be minimized. Therefore, the spread signal is generally generated in synchronization with the vertical synchronization signal. Therefore, separating and extracting the vertical synchronization signal is essential for reproducing video signals and generating spread signals. This synchronization signal is designed to be as unaffected as possible by noise on the transmission path.
It is also necessary to extract the data while maintaining accurate timing.

[Conventional technology]

FIG. 8 is a diagram showing waveforms near the vertical synchronizing pulse of an NTSC video signal for both odd and even fields. The signal near the horizontal synchronization pulse is composed of a vertical synchronization pulse P(Vl), a horizontal synchronization pulse PfhL, and an equalization pulse Ptel.

Horizontal synchronizing pulse P (hl is superimposed on the video signal.

FIG. 9 is a block diagram illustrating an example of a prior art vertical synchronization signal detector that separates a vertical synchronization signal from a signal such as that shown in FIG. In the figure, 1 is a pulse clamp circuit that stabilizes the peak value of the video synchronization pulse part, and 2 is a pulse clamp circuit that extracts only the synchronization pulse part from the video signal by comparing the output signal of the pulse clamp circuit 1 with an appropriate constant comparison standard. 1 is an integrator that integrates the same pulse extracted by the voltage comparator 2;] 1 is an integrator that extracts the vertical synchronizing pulse portion by comparing the output voltage of the integrator 10 with an appropriate comparison standard; This is a voltage comparator for detection.

The operation of this conventional vertical synchronization signal detector will be explained below with reference to FIG. FIG. 10 is a time chart of the ninth country signal, where (1) is the video synchronization signal S extracted by the voltage comparator 2 (1, 1, (2) is the integral output signal output from the integrator 10). 5(8), +3+ is the vertical synchronization signal 5(9) output from the voltage comparator 11.

Video signal transmission paths generally do not transmit DC components. Therefore, the waveform of the synchronization pulse portion varies depending on the video luminance signal. Therefore, in order to suppress this variation, the peak value of the video signal is made constant by the pulse clamp circuit 1.

Then, the voltage comparator 2 compares it with a constant comparison reference voltage and extracts only the synchronizing pulse portion 5(1) from the video signal. When this synchronization pulse 5(1) is integrated by an integrator 10, an integral output number 5(8) is obtained. In this case, the vertical synchronizing pulse Ptv+ and the horizontal synchronizing pulse P (hl) have different pulse widths, and the vertical synchronizing pulse P (V) is the horizontal synchronizing pulse.

It has a larger pulse width than P fhl. Therefore, when passing through the integrator 10, the integrated output signal 5 (8)
becomes chevron-shaped at the vertical sync pulse part. The voltage comparator 11 detects this chevron-shaped portion by comparing it with a predetermined reference voltage, and outputs a vertical synchronizing signal 5 (9).

[Problem that the invention seeks to solve]

The conventional vertical sync signal detector described above utilizes an integrator and a voltage comparator to detect the vertical sync signal. Therefore, if the comparison standard of the voltage comparator fluctuates due to temperature changes or changes over time, the detection timing of the vertical synchronization signal will change, making it impossible to obtain accurate and stable output timing, and in extreme cases, synchronization separation may occur. It will not be done correctly. Furthermore, if there is noise in the input signal, there is a high possibility that erroneous detection will occur due to the noise. Furthermore, it is difficult to adjust the detection timing.

[Means for solving problems]

FIG. 1 is a principle block diagram of a vertical synchronization signal detection device according to the present invention. In one form of the present invention, the vertical synchronization signal detection device includes a synchronization signal extraction unit 20 that extracts and outputs a synchronization signal from a video signal, and a pulse signal of a predetermined pulse width that is triggered by the synchronization signal of the synchronization signal extraction unit 20. A pulse signal generating section 21 that generates and outputs. A memory composed of a shift register or the like, in which a pulse signal from the pulse signal generation section 21 and a synchronization signal from the synchronization signal extraction section 20 are manually input, and the other signal is read as input data at a timing corresponding to one of the signals. Part 22. and,
A determination unit 23 is provided that determines the contents stored in the storage unit 22 and detects a vertical synchronization signal.

In another embodiment of the present invention, the vertical synchronization signal detection device further includes, in addition to the above-described configuration, a prohibition section 24 that prohibits the operation of the storage section 22 for a predetermined period of time in response to a detection signal from the 11 constant section 23.

[For production]

Synchronous signal extraction unit 2 from a video signal as shown in FIG.
A synchronizing pulse is extracted by 0, and the pulse signal generating section 21 is triggered from 1 to 1 by this synchronizing pulse to output a pulse signal with a predetermined pulse width. This 1 ~ How to do Riga 1
For example, it is possible to trigger on the rising edge of the synchronizing pulse signal, or to trigger on the falling edge of the synchronizing pulse signal.

The storage section 22 sequentially takes in the synchronizing pulse and the pulse signal from the pulse signal generating section 21 as input data at a timing determined by one of the signals. For example, when the pulse signal generator 21 is triggered by the rising edge of the synchronization pulse, the storage unit 22 sequentially reads the pulse signals from the pulse signal generator 21 at the falling timing of the synchronization pulse. When the 1-trigger occurs at the rising edge of the pulse, the storage section 22 sequentially captures synchronizing pulses at the falling timing of the pulse signal from the pulse signal generating section 21.

By doing this, the vertical synchronizing pulse P +v+ and the horizontal synchronizing pulse P (hl) have different pulse widths.

In the storage unit 23, for example, "0" is 4 in the horizontal synchronizing pulse part.
The signals are input continuously, and "1" is continuously input in the vertical synchronization pulse section. A vertical synchronization signal can be detected by determining this continuous input of "1" by the determining section 23. As a determination method, a method of logically multiplying the contents stored in the storage unit 23, a method of determining by majority vote, etc. can be used.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing a vertical synchronization signal detection device as an embodiment of the present invention. In the figure, a pulse clamp circuit 1 and a voltage comparator 2 are the same circuits as explained in FIG. 9, and are used to extract a synchronizing pulse 5(1) from a video signal. 3 is a monostable multi-by-break, which is triggered by the rising edge of the synchronizing pulse S (11) and generates and outputs pulse 5 (2) of pulse width τ (11). In this case, the pulse width of the horizontal synchronizing pulse P fh) is longer than 0.075 H,
An appropriate value shorter than the pulse width of 0.43H of the vertical synchronization pulse PfV) is selected. Here, H represents the period of the horizontal synchronizing pulse.

Output pulse 5 (2) from monostable multi-bi break 3
is input to the data input terminal (JK terminal) of the serial input parallel output type shift register 4. A synchronizing pulse S (11) is inverted and guided to the clock input terminal CLK of the shift register 4, and the shift register 4 sequentially receives data input at the timing of the falling edge of this synchronizing pulse S (11) and shifts it. In this example, the shift register 4 has a 3-bit configuration.

The shift register 4 outputs an inverted output signal Q (01 to 1(2)) of the 3-bit parallel output shift signal.
These inverted output signals Qto) to 100(2) are respectively guided to each input terminal of the AND circuit 5. The AND circuit 5 outputs a vertical synchronizing signal 5 (6).

The operation of the apparatus of this embodiment will be explained below with reference to FIG. FIG. 3 is a time chart of the signals of each part of the device shown in FIG.
, output pulse S'(2) of monostable multibibreak
, shift register 40 inverted output signal Q to)
~Q (2) , vertical synchronization signal 5 from AND circuit 5 (
6) is shown.

The synchronous pulse S (11) extracted by the pulse clamp circuit 1 and voltage comparator 2 is input to the monostable multivibrator 3 and shift register 4, respectively, and the monostable multivibrator 3 is triggered at the rising timing of the synchronous pulse 5 (11). and the pulse width τ(11 output pulses 5(
2) is output. On the other hand, the shift register 4 reads the output pulse 5 (2) of the monostable multi-by-break 3 at the falling timing of the synchronizing pulse S (11).
The pulse width τ(1) of pulse 5(2) is 0.075
Since the appropriate value of H<τ(11>0.43H) is selected, the horizontal synchronization pulse section and equalization pulse section are read at the clock timing of the shift register 4, that is, the timing indicated by the broken line in Fig. 3. The logic levels of the data input terminals are all 1''. Therefore, in this part, the inverted output signals of the shift register 4 100 (0) to -Q (21
are all "0", and the level of the output signal from the AND circuit 5 is O".

On the other hand, in the vertical synchronization pulse section, the logic level of the data input terminal read into the shift register 4 is O'', and this is sequentially shifted into the shift register 4. Therefore, the inverted output signal Q (0) to 100 of the shift register 4 is (2
) becomes “1”. This is judged by the AND circuit 5, the vertical sync pulse part is detected, and the AND circuit 5 outputs “
A vertical synchronizing signal 5 (6) of 1" level is output.

In this embodiment, the vertical synchronization signal is detected by the AND circuit 5 when all of the 3-bit inverted output signals 100 (0) to 100 (2) of the shift register 4 become "L". However, this is to prevent erroneous detection of the vertical synchronization signal. In other words, 1. For example, even if the pulse width shifts in the horizontal synchronization signal section due to noise in the transmission path and a pulse width similar to the vertical synchronization pulse is generated, vertical synchronization will not occur unless such a pulse width is generated three times in a row. Since it is not considered as signal detection, the probability of false detection can be significantly reduced. Also, there are 6 vertical sync pulses.

Even if some of these pulses are missing due to noise, etc., if there are 3 consecutive pulses out of 6, the vertical sync signal can be detected, which greatly reduces the probability of failure to detect the vertical sync signal due to noise, etc. Can be reduced.

Various modifications are possible in carrying out the invention. FIG. 4 is a block diagram showing another embodiment of the present invention as such a modified example, and in FIG. 9, the same components as in FIG. 2 are given the same reference numerals. The difference is that
The monostable multi-high break 6 is triggered by the falling edge of the synchronizing pulse 5(1) and outputs an output pulse 500) with a pulse width τ(2).
0) is inverted and guided to the clock input terminal CLK of the shift register 7. This pulse width τ(2) is selected to be an appropriate value that is larger than the space width of 0.07H between the vertical synchronizing pulses PfV1 and smaller than the space width of 0.468 between the equalization pulses PCe1.

The data input terminal of the shift register 7 has a synchronous pulse 5 (
1) is directly led and therefore the shift register 7 receives the output pulse 50 from the monostable multi-bi break 6.
The synchronizing pulses 5(1) are sequentially read at the falling timing of 0) and shifted internally. Further, the non-inverted parallel output signals Q (01 to Q(2)) of the shift register 7 are outputted to the AND circuit 5.

With this configuration, as shown in the signal time chart of FIG. 5, an input signal of "1" is continuously read into the shift register 7 only at the vertical synchronization pulse portion, thereby detecting the vertical synchronization signal. will be done.

FIG. 6 is a block diagram showing still another embodiment of the present invention, and in FIG. 9, the same components as in FIG. 2 are given the same reference numerals. The difference from the device shown in FIG. 2 is that the output pulse 5 (2) from the monostable multi-bi break 3 is guided to the data input terminal of the shift 1 register 4 via the OR circuit 9; The output pulse from the monostable multi-bibreak 8 is led to the other input terminal of the circuit 9. The monostable multi-bi break 8 is a circuit that is triggered by the rising edge of the output signal of the AND circuit 5 and emits an output pulse 5 (7) having a pulse width τ (3).

This OR circuit 9 and monostable multi-high break 8 are provided to further ensure the prevention of false detection.
A detection prohibition period is provided during which detection of the vertical synchronization signal by the shift register 4 is prohibited. That is, in the case of the NTSC system, the vertical synchronization signal is obtained at a period of 16.6 ms. Therefore, once the vertical synchronizing signal is detected, the vertical synchronizing signal will not be detected again for about 15 m5 after that.

If it is detected, it is an erroneous detection due to noise or the like.

Therefore, once the vertical synchronizing signal is detected, the vertical synchronizing signal 5 (6) activates the monostable multi-by-break 8 as a timer circuit and sends the output pulse 5 (7) to the OR circuit 9. The pulse width of this output pulse 5 (7) is set to the time just before the detection of the vertical synchronization signal and when the next vertical synchronization signal is expected to be detected. Due to this output pulse 5 (7), the data input to the shift register 4 is always "1" during the horizontal synchronizing signal period, and erroneous detection of the vertical synchronizing signal during this period is prevented. FIG. 7 is a time chart of the sixth country name part signal showing this situation, and (1) to (6) are the same as the signal waveforms in FIG. 3.

(7) shows the signal waveform of the output pulse 5 (7) from the monostable multi-high break 8.

As still another modification of the present invention, 1. For example, in the above-mentioned embodiment, false detection is prevented by an AND filter using shift 1 to registers and AND logic, but the present invention is not limited to this. You can also do it. That is, for example, the number of shift stages of the shift register may be five, and if three or more pins out of five bits are logic "1", it may be determined that a vertical synchronizing signal has been detected. Furthermore,
The number of stages of the shift register, the number of inputs to the AND circuit, etc. can also be changed as necessary.

〔Effect of the invention〕

According to the present invention, a vertical synchronization signal can be detected from a video synchronization signal with accurate timing.

Furthermore, this detection timing is not affected by temperature changes or changes over time. Furthermore, detection errors due to noise or the like can be reduced. Further, there is no need for fine adjustment of the comparator threshold value, etc., as in the conventional type, and it is possible to eliminate the need for adjustment of the device.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram according to the present invention, FIG. 2 is a block diagram of a vertical synchronization signal detection device as an embodiment of the present invention, and FIG. 3 is a time chart of signals of each part of the device shown in FIG.
FIG. 4 is a block diagram of another embodiment of the present invention, FIG. 5 is a time chart of signals of each part of the device shown in FIG. 4, FIG. 6 is a block diagram of still another embodiment of the present invention, and FIG. Fig. 6: Time chart of signals of each part of the device Fig. 8 is a diagram showing an NTSC video signal, Fig. 9 is a block diagram of a conventional vertical synchronization signal detection circuit, Fig. 10 is a time chart of signals of each part of the device shown in Fig. 9. This is a time chart. 1 - Pulse clamp circuit 2 - Voltage comparator 3.8 - Monostable multi-bi break 4.7 - Shift register 5 - AND circuit 9 - OR circuit

Claims (1)

[Claims] 1. A synchronization signal extractor (20) that extracts and outputs a synchronization signal from a video signal, which is triggered by the synchronization signal from the synchronization signal extraction section to generate and output a pulse signal with a predetermined pulse width. A pulse signal generator (21) receives a pulse signal from the pulse signal generator (21) and a synchronization signal from the synchronization signal extractor (20), and outputs the other signal at a timing corresponding to one of the signals. A vertical synchronizing signal detection device, comprising: a storage unit (22) that sequentially reads data as input data; and a determination unit (23) that determines the accumulated contents of the storage unit (21) to detect a vertical synchronization signal. 2. The pulse signal generator (21) is triggered by the rising edge of the synchronization signal, and the storage part (22) is triggered by the pulse signal generator (21) at the timing of the falling edge of the synchronization signal.
2. The vertical synchronization signal detection device according to claim 1, configured to read a pulse signal from ) as input data. 3. The pulse signal generator (21) is triggered at the falling edge of the synchronization signal, and the storage section (22) is triggered at the falling edge of the pulse signal from the pulse signal generator (21). The vertical synchronization signal detection device according to claim 1, configured to read the signal as input data. 4. The determination unit (23) is configured to detect the vertical synchronization signal according to the logical product condition of the contents stored in the storage unit (22). The vertical synchronization signal detection device described in . 5. The determination unit (23) is configured to detect the vertical synchronization signal by majority determination of the contents stored in the storage unit (22). The vertical synchronization signal detection device described above. 6. The vertical synchronization signal detection device according to any one of claims 1 to 5, wherein the storage section (22) is constituted by a shift register. 7. A sync signal extractor (20) that extracts and outputs a sync signal from a video signal; a pulse signal generator (21) that generates and outputs a pulse signal with a predetermined pulse width triggered by the sync signal from the sync signal extractor; ), a memory that receives the pulse signal from the pulse signal generator (21) and the synchronization signal from the synchronization signal extraction unit (20), and reads the other signal as input data at a timing corresponding to one of the signals. section (22), a determining section (23) that determines the accumulated content of the storage section (21) and detects a vertical synchronization signal, and a determining section (23) that determines the storage contents of the storage section (21) and detects a vertical synchronization signal; Prohibition part (24) that prohibits the operation of part (22)
, A vertical synchronization signal detection device comprising: