JPS63306718A - Serial access circuit - Google Patents

Abstract

PURPOSE:To facilitate high density by providing a count circuit counting a clock signal and a decode circuit generating an output signal at a bit output corresponding to its output signal so as to attain small size and low power consumption for the titled circuit. CONSTITUTION:The titled circuit consists of a counter circuit 1 receiving a clock phi as an input signal and counting the clock phi and a decode circuit 2 outputting sequentially signals S0-Sn corresponding to the count of the counter circuit 1. Through the constitution above, the counter circuit 1 outputs addresses A0-An in response to the input number of the clock phi. The addresses A0-An are decoded by a decoder 2 to generate the output signals S0-Sn. A binary code generating type or a Gray code generation type counter is employed for the counter circuit 1 and number of times of charge/discharge is decreased by employing especially the gray code generating type thereby reducing the power consumption. As the decode circuit 2, a NOR circuit or a NAND circuit can be used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a serial access circuit in which output signals are sequentially shifted in accordance with a clock, and particularly to a serial access circuit that can achieve high density.

(Prior Art) As a conventional serial access circuit, for example, there is one shown in FIG.
registers 20. .about.207 are serially connected, and registers 20. to 207 corresponding to the final bit are connected in series. The output S, , of the AND gate 21 is set as one input of the AND gate 21, and the clock φ is applied to the other input of the AND gate 21, and the output is used as the register 20. is configured to start.

In the above configuration, when one clock φ is input, the register 20. 80 is generated, and then when the clock φ is input, Sl is generated from the register 20□ using So as an input signal. Thereafter, an output signal is generated from each register each time the clock φ is input in the same way, and when S is generated from the register 20.1, it is returned to the AND gate 21, and a signal is generated repeatedly from So again.

On the other hand, as a conventional serial access circuit, there is one in which a redundancy circuit is added to a register, as shown in FIG. In the figure, FOI~FW□ is a phase for redundancy, transistors 22~22A are connected between adjacent register outputs, and transistors 23~22A are connected to the output of each register. ~23. are connected to each other.

In FIG. 6, if the output S1 is a defective bit, by cutting the phases F++- and F+z, S1 is not selected, but selection is performed with a shift of one bit.

That is, by canting the phase, the signal transmission transistor 22. and 23. Both are 0FFL, and no signal is transmitted to S1, which is a defective bit, and the signal that should originally be transmitted to S1 is shifted by 1 bit.7 so that it is transmitted to S2.

[Problem that the invention seeks to solve]

However, in the former serial access circuit, as the number of bits increases, the load of the signals returned from S, . Furthermore, the existence of a signal line returning from the last bit to 30 is an obstacle to increasing the density in C.

Furthermore, the latter serial access circuit requires a redundancy circuit for each bit, which is an obstacle to higher density.

[Means for solving problems]

The present invention has been made in view of the above, and in order to achieve high density and enable miniaturization of the circuit, a counter circuit to which a clock is applied and a decoding circuit connected to the circuit are combined. Provides a serial access circuit with

That is, the serial access circuit of the present invention includes the following means.

fll Address (e.g. A0 to Ai,
A, ~τ,), and for example, a binary code generation type or a Gray code generation type can be used.

(2) Decode circuit This circuit decodes the address signal output from the counter circuit and converts the output bit corresponding to the address signal from the "L" level to the "H" level (or vice versa).The circuit configuration is as follows: For example, a NOR circuit, a NAND circuit, etc. can be used.

[For production]

The decoder generates an output signal on the output bit corresponding to the address output from the counter, and serial access can be performed without operating sequentially as in the past (and without returning the last bit to the first stage). be exposed.

〔Example〕

Examples of the present invention will be described in detail below.

FIG. 1 is a block diagram showing an embodiment of the present invention, which includes a counter circuit 1 that uses a clock φ as an input signal and counts the clock φ, and 80 to S7 in order corresponding to the count value of the counter circuit 1. It consists of a decoding circuit 2 which outputs .

For the counter circuit 1, a binary code generation type, a Gray code generation type, etc. can be used. In particular, by using a Gray code generation type, the number of charging and discharging can be reduced.
Power consumption can be reduced. Further, the decoding circuit 2 can be of a NOR type or a NAND type.

In the above configuration, the counter circuit 1 selects addresses A0 to A depending on the number of input clocks φ.

Output. These addresses A0-A, 1 are decoded by the decoder 2 to generate output signals 80-S.

FIG. 2 shows another embodiment of the present invention, which is indicated by the same reference numerals as in FIG. 1, so redundant explanation will be omitted. A driver 4 is connected to the decoder 3 and an inverter 5 is provided between the decoder 3 and the decoder 2. The driver 4 outputs a spare bit, and the inverter 5 inverts the output of the decoder 3.

The redundancy decoder 3 generates a signal Rout for instructing the decoder 2 to select a spare bit or not, and has the configuration shown in FIG. 3, for example. As shown in FIG. 3, a transistor 61 receives each of addresses A0 to A, -person 10 to -person-1 as input signals.
~621% are connected in parallel through each of the phases F l''' F 2n to generate Rout.

In Fig. 2, suppose that 80 is defective, and S
It is assumed that o is selected when the address outputs A0 to A of the counter are "H". In Fig. 3, τ is determined by the decoder 3. It is sufficient to cant the phase of the circuit portion of ~τ7. The output Rout of the redundancy decoder 3 is “
Become Lo. In this state, the spare focus is not selected. However, in the state where the phase is cut, Rout becomes 'H' when So is selected, and the spare bit is selected.Then, the inverted signal of Rout is input to the decoder 2, and this decoder 2 becomes inactive, and 30~ All of Swa becomes unselected.

In this way, according to the configuration shown in FIG. 2, the number of phases matches the number of addresses, and can be halved compared to the conventional case where the number of addresses is twice as many, making it easy to achieve high density.

Figure 4 shows a circuit in which the counter circuit 1 is of the Gray code generation type, and is a NOR circuit that inputs binary B0 and Bl.
NOR gate 7bS inputting game a, Bl and B2
It is composed of a NOR gate 7C that inputs B, and B3,
Gray code and binary code correspond as shown in Tables 1 and 2. The output of this circuit is applied to a decoder. When a Gray code is used, there are fewer changes in bits than in a binary code, so the number of charging and discharging operations is reduced, and power consumption can be reduced.

(Gray code) (Binary code) [Effects of the invention] As explained above, according to the present invention, since a serial access circuit is configured by a combination of a counter circuit and a decoder, it is possible to miniaturize the circuit and reduce power consumption. Electrification can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the invention, FIG. 3 is a circuit diagram showing details of the redundancy circuit shown in FIG. Figure 4 is a circuit diagram of the gray code type counter circuit according to the embodiment of the present invention, Figure 5 is a circuit diagram of a conventional serial access circuit, and Figure 6 is a conventional serial access circuit with a redundancy circuit added. FIG. Explanation of symbols 1 --- Counter 2 --- Decode circuit 3 --- Redundancy circuit

Claims (3)

[Claims] (1) A serial device characterized by comprising a counter circuit that counts clock signals, and a decoding circuit that decodes the contents of the output signal of the counter circuit and generates an output signal as a bit output corresponding to the output signal. access circuit. (2) The serial access circuit according to claim 1, wherein the counter circuit is of a Gray code generation type. (3) The serial access circuit according to claim 1, wherein the counter circuit is connected to a redundancy circuit that generates a spare bit signal.