JPS63301989A - Image display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image display that performs display using a liquid crystal sandwiched between a substrate on which pixel electrodes connected to transistors are formed and a counter substrate on which column electrodes are formed. It is related to the device.

[Prior Art] In the field of high-density image display, a simple dot matrix type display device using a liquid crystal sandwiched between a substrate having a plurality of row electrodes arranged thereon and a counter substrate having a plurality of column electrodes arranged has conventionally been used. Are known.

[Problems to be solved by the invention] With this type of device, it is difficult to display a high-definition, full-color image with a wide viewing angle due to constraints on the drive duty ratio, and an active element is inserted into each pixel to drive the liquid crystal. Active matrix display devices are increasingly being applied in this field. An object of the present invention is to provide an active matrix type image display device having novel features in the structure and drive of a display body.

[Means for Solving the Problems] The present invention provides an image display device that performs display using a liquid crystal sandwiched between a substrate on which pixel electrodes connected to transistors are formed and a counter substrate on which column electrodes are formed. The gates of the pixel transistors are commonly connected to the row electrode for each row, the sources are connected to the row electrodes to which the gates of the transistors of adjacent pixels are connected, and the trains are connected to the pixel electrodes and the adjacent row electrodes are connected to each other. Following the data input to the pixel electrode of each pixel, a signal is applied to turn the transistor on and off, and periodically inverted image data is applied to the column electrode, respectively, and the liquid crystal is driven by the transistor for each pixel. This increases the duty ratio and improves display performance.

FIG. 1 is a plan view of a liquid crystal display of an image display device of the present invention, in which (1) is a substrate on which a plurality of pixel electrodes connected to transistors are formed, and (2) is a column electrode opposite to the pixel electrode in (1). The liquid crystal is (11, (2
It is sandwiched between 1.

As shown in (3), the pixel electrodes in the odd rows are column electrodes in the odd columns (5) whose lead electrodes are located on the second side of the liquid crystal display.
The gate of the transistor facing (7) and having its drain connected to the pixel electrode of (3) is connected to the row electrode (9) of the odd numbered row, and the source is connected to the row electrode (10) of the adjacent even numbered row. . The pixel electrodes in even rows are as shown in (4).
The gate of the transistor whose lead electrode faces the column electrode (61, (8)) of the even numbered columns located below the liquid crystal display and whose drain is connected to (4) is connected to the row electrode (10) of the even numbered row. The sources are respectively connected to the row electrodes (11) of adjacent odd-numbered rows.The column electrodes are connected to the columnar metal electrodes, and the portions opposite to the transparent pixel electrodes f31, (41) [
71, +8) are made up of transparent electrodes. The polarizing plate is attached to the surface of the substrate [11, +2).

FIG. 2 is a configuration diagram of a pixel of the image display device of the present invention driven by a transistor formed for each pixel,
(+, Jl to (f+1.Jul) are shown. (12) is a transistor, (13) is a pixel electrode connected to the drain of (12), and (16) is opposite to (13). Column electrode, (I4) is liquid crystal, (15) is (12)
is the connected row electrode of the gate.

Gfl), Gfl+I), Gfl+2) are in one line, (I
ll) row, (++2) row electrode signal, D (J)
, D (J+l) is the 5th column of odd-numbered pixels, (Jul
) column electrode signal of the column, D (j).

D(j+Il is the signal of the column electrode of the 5th column and (++11th column) of the pixel in the even row. The transistor (+
The gates of transistors 2) and +17) are commonly connected to the row electrode that transmits the signal G(1), and the sources of the transistors +18) and (+9) of adjacent pixels are connected to the row electrode that transmits the signal G(1+11). A signal is applied to the row electrode to turn the transistor on or off following the data input to the pixel electrode of the adjacent pixel, and image data is applied to the column electrode, and the transistor in one row is turned on by Gill. When the signal G(1+11
) displays an image using the stored data while the transistor is turned off. AC driving of the liquid crystal is performed by periodically inverting the polarity of data applied to the column electrodes and stored in the liquid crystal, based on a common potential applied to each pixel electrode for each row.

FIG. 3 is a layout diagram of color filters for each pixel of the liquid crystal display of the image display device of the present invention.

Each pixel has filters for the three primary colors of R (red), G (green), and B (blue), and is formed so that pixels of filters of different colors are adjacent to each other, and in odd-numbered rows, RoG and B are repeated in the row direction. , even-numbered rows repeat B, R, and G, and the image data applied to each column electrode shown in FIG. 1 is R, G, and 11 signals for each column.

FIG. 4 is a plan view of a pixel of a liquid crystal display of an image display device of the present invention, FIG. 5 is a cross-sectional view of the pixel, and FIGS. 6 and 7 are cross-sectional views of a substrate on which a pixel electrode is formed. , Figure 5 is the fourth
AA', FIG. 6 is a cross-sectional view taken along line +3-B', and FIG. Glass substrate (3
7) J: (22) is formed; (38) is the gate electrode of the transistor, (39) is the gate insulating film,
(24).

(40) is a semiconductor layer, (25); (411 is an insulating film, (30));

(42), (441 is a semiconductor layer, a metal stacked source electrode, (31); (43), +451 is a semiconductor layer, a metal stacked train electrode, (321;
(46) is the resistance connected to the source electrode, (33)
; (47) is a transparent pixel electrode, (48) is an insulating film, (
49) is an alignment treatment layer, and the opposing glass substrate (50
)l's (sll, fsz) is the adjacent color filter layer, (53) is the black pattern layer, (54) is the protective film, +36); (55) is (331).

Transparent column electrodes facing (47), (56) facing (55)
The column electrode (57) adjacent to is an alignment treatment layer, and the liquid crystal (58) is sandwiched between the substrates (371 and (50)).

(59) is a glass substrate corresponding to (37), (60) is a gate insulating film corresponding to (39), (291: (61)
1, (621 is a source electrode, a semiconductor layer like a train electrode, a laminated metal electrode, +321; (63)
is in contact with (29); (62) and pixel electrode (33):
(Transparent electrode that serves as a resistance in the same layer as 641, (65),
[i) is an insulating film and an alignment layer corresponding to (48) and (491), respectively.

(67) is a glass substrate corresponding to (37), (21)
(68) is next to the row electrode (20) and (22):
The row electrode is in the same layer as (38), the gate insulating film (69) corresponds to (39), and (28).

(711, (72) are connected to the source electrode of the transistor through (29) and +321, and (26
).

(70) in contact with (21); (68)
are connected to form row electrodes. (20), (27)
As shown in (21) and (28), the row electrode is a multilayer wiring including an electrode in the same layer as the gate electrode, a source electrode, and an electrode in the same layer as the train electrode.
) is sufficiently lower than the resistance (32) connected to the resistor (32).

(73) and +74) are the insulating films and alignment layers corresponding to +48) and (49), respectively. As shown in Fig. 4, one pixel having filters of the same color is divided into almost symmetrical pairs on the left and right sides, and faces a transparent electrode (36) that is in contact with a row of metal electrodes (35). There are pixel electrodes (33) and (34), respectively (22).
, (23) is connected to the drain of the transistor whose gate electrode is. The metals of the gate electrode, source electrode, train electrode, and column electrode are AI, old, Cr, Mo,
Transparent pixel electrodes and column electrodes are made of In20a such as Ta and W.
, SnO□ (ITO), gate insulating film, insulating film is Si
O□, 5iJ4. SiOxNy, Al□Os, Ta
J6 etc., semiconductor layer is Si, source semiconductor layer, drain semiconductor layer is N-type Si, color filter, black pattern layer is patterned by ink printing or photolithography of resin containing dye, protective film is polyimide or insulation. The alignment treatment layer, which is made of the same material as mentioned above, is formed by rubbing the polyimide film, and the rubbing directions are almost perpendicular between the opposing substrates. After the gate insulating film, the semiconductor layer, and the insulating film thereon are successively deposited, the insulating film and the semiconductor layer are patterned into the shapes (25) and (24), respectively, and a source electrode and a drain electrode are formed on the semiconductor layer. It is formed by laminating N-type S1 and metal. The electrode that crosses the row electrode on the substrate where the transistor and pixel electrodes are formed is the source electrode or train electrode that overlaps the gate electrode of the transistor, and the source electrode is connected to the gate of the transistor of the adjacent pixel through a resistor. Since the pixel is connected to the row electrode that is connected to the row electrode, a point defect in one part of the transistor will not cause a line defect, and since the pixels are composed of almost symmetrical pairs, even if one has a defect, Both contribute to the display. Instead of attaching a resistor to the source electrode, a resistor may be attached between the row electrode and the gate electrode, and the pixel is configured so that the pixel electrodes (33) and (341) are integrated and have a pair of transistors, and a defective transistor is removed. It may be separated from the pixel electrode using a laser or the like.The semiconductor layer in the channel portion of the transistor is shielded from light by the gate electrode (38) and the black pattern (53) on the opposing substrate.

FIG. 8 is a block diagram of the image display device of the present invention, and FIG. 9 is a diagram of a potential selection circuit constituting a row side drive circuit. (75)
is a column side drive circuit, which includes a shift register (76) that transfers data Ds using a clock CL, and serial image data DI corresponding to each pixel of a liquid crystal display (82) having color filters for each of the three primary colors. D2.03 (7
6) each output o'Sf+).

t+2s(+l, D3s(+) ~D'5(N), D2
Sampled sequentially by S(N) and D3S(N),
In synchronization with the enable signal W, data D' (1), D2 (1
), D'(1) to D'(N), D2(Nl.

A sample-and-hold circuit (77
). (78) is a column-side drive circuit similar to (75), and the clock C1 is applied to the shift register.
,' and data Ds', image data D', D2. D'' and enable signal W
' has been input and the column where the lead electrode is located below (82)? Data D″l(+1. D″2(1
+, D' 3 (]) ~ D" (N), D"2fN),
D' (1) is supplied to the column electrode signal D (J) shown in FIG.
It corresponds to the relationship of (1=I~N, P=1~3), and D (
j) corresponds to D″p(11).

(79) is a drive circuit on the row side, which includes a shift register (BO) that transfers data DG using clock C146, and (
80) each output P(K-11,3(K-11,P(K)
(In the logical state of K=l-Mill, a potential selection circuit that creates a signal G (to) to turn on (v6G) and turn off (VEIll) the transistor following the data (vq) input to the pixel electrode of the adjacent pixel in (82) (81).The substrate (83) of the liquid crystal display (82) has (79)
The signals from the row electrodes are inputted to the counter substrate (84).
Column electrode signals are input from 751 and (78).

The power supply potential of Voo Vss is connected to (75) and (7B), and the power supply potential of Vaa Vllw is connected to (79). The potential selection circuit is P(K-++, 5(K-
When inputting 11, the output of Noah (85) becomes the control input,
an analog switch (88) that receives P (K) as an input;
The output of (85) is inverted by an inverter (86) and used as a control input, and the analog switch (87) uses vR as an input.
The output terminals are connected to each other, and a row signal of G (K) is output to the row electrode of the 1st row of the liquid crystal display.

P[K-1), 5 (at least one of K-11 is high (V6.), (87) is on, (88) is off, and v8
is selected as the signal of G (K), PfK~]), 5
fK-]) are all low (1I[l), (87) is off, (88) is on, and P (to) is selected as the signal for G (K). ■ 8 is the data to be input into the pixel electrode of the pixel in the (K-11th row), P (K) is the signal that turns on and off the transistor of the pixel in the 1st row. The row signal G ( +1 is P (01, S (01, P (+
1, but since G(1) does not need to output data to be input to the pixel electrode of an adjacent pixel, it only needs to output a signal to turn on and off the transistor (
87) input vR is Vl! It is possible to output P(1) as [1 or P(+)<, G(11).Also, since the liquid crystal display is composed of M rows of pixels, the Mth row The row electrode of the (M+1)th row adjacent to the pixel does not need to output a signal to turn the transistor on or off, and only needs to output data to be input to the adjacent pixel, so P (M), S (M ), P
+88 of a circuit consisting of (M+l) logic states
1(7) Input P(M+l) is V[lI! Alternatively, it may be configured to output vR as VR and C(V++).

[Operation] FIGS. 10 and 11 are timing charts showing the operation of the image display device of the present invention, and FIG. 10 shows the operation waveforms of the row side drive circuit. CLG transfers data D6 using a clock signal with a high fV and a period of 61 shorter than a period of low (V, ), and C166 is high at P (in) and low at S
The signal of fKl is changed, and P(K-11,5(
Following K-1+, P(K) and S(ni) become high. G (K) is P(K-11÷5(
OR of K-11 or high (v66) tevR10-(Vp
F) TP(K) signal, so V is followed by VR.
6a, V(1p,
+), turns on and off the transistor, and turns the transistor on and off (K-
The signals G [+1 and G [2) indicate that data is input from the row electrode of the 1st row to the pixel electrode of the pixel in the 11th row. Three primary color image data DI, D2.
D3 is sequentially sampled during the period shown by hatching on the lower left, and is supplied in parallel to each column electrode of the liquid crystal display when enable signals W and W' become high (VOO) during the sampling pause period shown by hatching on the lower right. ■ becomes high when indicated by a downward-sloping hatch to the left and updates the data of the column electrode opposite to the pixel electrode in an odd-numbered row; Change the data of the column electrode facing the . When the signal G of the row electrode of the 1st row becomes VGG and turns on the transistor, the signal G of the adjacent row (K++1 is ■8, or W' becomes high and the column electrode is updated. The data 8 applied to the row electrodes and guided to the pixel electrodes of the adjacent row is G(11°G(2)~G(M
) sequentially turns on a group of transistors for each row, and periodically inverts each frame in which data is determined for each pixel, and Vd
Alternatively, the potential is Vc (Vc-Vd·■), and the image data applied to the column electrodes is similarly inverted periodically every frame to become a signal with a potential of vb to Va or Va-Vb.

Assuming that the capacitance of the pixel's liquid crystal is CLc, and the capacitance between the transistor gate and the pixel electrode is Can, the data input to the pixel electrode when the transistor is turned on is ΔV= the pixel electrode height when the transistor is turned off. -CGD
By changing (VGG-V[III) / (CLC”Cao), the potential of the selected Vn is Vd= (
Va+Vb) /2-V/2-ΔV, Vc・(Va+
Vb) /2+V/2-ΔV, this effect can be made extremely small. This means (Va+Vb)/2=(V
c+Vd)/2+ΔV This means setting at a position shifted by Δ■ from the inversion center of image data or the inversion center of 8. The capacitance of a liquid crystal changes depending on the voltage applied to the liquid crystal, and CL is when the liquid crystal molecules are aligned parallel to the direction of the electric field.
c//, if it is CLC soil when it is arranged vertically,
In a liquid crystal with positive dielectric anisotropy, it is CLC//〉CLC soil, so if CLC is CLC//, CL, the transition in the case of soil is Δ■//, and on ΔC, then ΔV//〈Δ■ soil It is. Therefore, as Ct, C (Ctc// +CLCJL)
/2 neighborhood is selected on average to determine ΔV. The potential change of the column electrode when the transistor is off is within (Va-Vb1), which is smaller than (VaG-vgI), and is an alternating current component that changes symmetrically from frame to frame, which affects the gradation characteristics. Cao/e so as not to damage
The pixel design of tc is sufficiently small. The pixel electrode potentials of the 2nd row, J column, M row and j column follow the signal of the column electrode of the 5th column, and as shown in D(2゜j) and D(M, j), approximately Vd-Va+Vb. ~Vc+Va-vb. The voltage applied to the liquid crystal is D (j) −D (2
, j) , D (j) −(M, jl (like D,
As Vo= (Va-Vb+V)/2, Habo-vO~
vO range, and the liquid crystal is driven by alternating current. 2 lines j
Image data that arranges liquid crystal molecules parallel and perpendicular to the inter-electrode direction is added to the pixels in the column, M row and j column, respectively, and when the transistor changes from on to off, the potential of the pixel electrode is ΔV//, ΔV The potential of the heart change signal is l/BB<Vss≦Vb<Va≦Voo<
Vaa, VII[l< Vd-Va +vb<
Vd<Vc<Vaa, for example, Va-Vb=
5v, Vc-Vd=5v, Vaa-Vee=20v. CL, D,, W and ct', os', w' are W.

As shown in the timing waveform of W', in order to reduce the power consumption of the column side drive circuits arranged above and below in FIG. 8, the signals are differentiated according to the evenness of the rows. In other words, during the data sampling period of DI, D2 and D3 just before ■ becomes high, the driving circuit (
75) is in operation, the signals CL' and os' to the lower drive circuit (78) are static and at low (vssl potential), and just before W' goes high, CL', D
, ' signals are output, (78) is in operation state, (75)
The signals CL and D are at low potential. Of course CL,
Ds, W and CL'.

Ds' and W' are output signals regardless of row parity, and both (75) and (78) are activated, and W' is W'.
The same signal may be used.

[Embodiment] Fig. 12 is a block diagram of an embodiment of the image display device of the present invention, Fig. 13 is an image data selection circuit diagram, and Fig. 14 is a sample/hold circuit that sends data to column electrodes of a liquid crystal display. figure,
Figure 15 is a potential selection circuit diagram for sending signals to the row electrodes;
The figure is a timing chart of signals on the column side, and FIG. 17 is the timing chart of signals on the row side. (89) transfers the data D8 using the clock CL and transfers the data D8 to the liquid crystal display substrate (95).
) configured on the sample and hold circuit (90)
(90) is a shift register that sends signals 5(1) to S(N) to 5(1) to S(N), and (90) carries serial image data D', D2 corresponding to each pixel of a liquid crystal display (93) having color filters for each of the three primary colors. ．． D”, each output 5 (1
) to S tN), and D'(+1.D2fl), D''+1 in synchronization with the enable signal W.
1~ D゛(N), D2(N), o3fN)
(7) Data, D′M++ in synchronization with enable signal W′
, D'"f!1.D'3(1)~D' + (N1.
Send data D'2 (N), D'3 (Nl) to each column electrode on the color filter. (91) transfers data D6 with clock C146,
4) A signal T is sent to the potential selection circuit (92) configured above.
(]), T(1)-TfK), is a shift register that sends
.

Q3. Q-, Qa, mouth, Q, (7) signal or vll
Signals G(1) and G(2) select the R potential and send to the row electrodes.
1, G (3), G (4), G (51°6 (6) ~ G f
6K), and each row signal is configured so that, following the data input to the pixel electrodes of the adjacent row, a potential is output that turns on and off the transistors in the row. (93) is a liquid crystal display body, in which liquid crystal is sandwiched between a substrate (94) and a counter substrate (95). (92) is constructed around the substrate using the same type of transistor as the transistor for each pixel in (94), and (95) is an area that will become the screen after forming the transistors that constitute the circuit in (90) around the substrate. A color filter is formed on the substrate, and column electrodes connected to the outputs of transistors around the substrate are formed on the color filter to form the entire substrate. (90) , ('1
The peripheral circuit 21 has a structure in which it is formed around the screen in the area where the liquid crystal is sealed, or covered with opposing substrates (94) and (95), respectively, for surface preservation. It is said that

(89) D is connected to the power supply potential of VI, I, and Vss, and (91) is connected to the power supply potential of VPPVllll+. Image data DR, D' of each of the three primary colors transferred in series,
D8 has the enable signal W high fvon1. W'
is low (VSS), and φ1. becomes high sequentially. φ2. φ3
selection switch (96), (10
01, (through +041 ('18), +102),
(] (16), the buffer amplifier with a gain of 1 + 991° (1031, (1071
Image data D', D2. D3 is sent to the sample/halt circuit, and the enable signal W is low, W
' is high, the data of DR, D(, DB is φ1.φ2
．． Selection switch (9) that turns on sequentially in synchronization with the φ3 signal
71, (+011.(+051 through (9U, (
I[12+, (+[]61 capacitance sampled, buffer amplifier +991. (103), +1071
are output as image data of D', D'', and D''.

W goes high when the color filter configures data to be sent to pixels in odd rows arranged as shown in Figure 3, and W' goes high when data is sent to pixels in even rows. It's time to configure. Sample and hold circuit (90)
The part that constitutes the signal D' (X) (P・1゜2.3.
) Output 5 (X) is added to the gate through resistors (1081, (1101), and image data DPfP=1.2°3) is input to the source of the transistor (1091, (Il
l) and the transistors (+
131. resistor (1121) on the gate of fl+5).

(The enable signal W is input through +141, and D' (X) is output from the commonly connected drains, and the logic state determined by the two forces of S (X) and W, that is, S (X) , W are both high (vn
When nl, sample DP (vb ~ va), and S F
X), W is low (Vss, Vss≦vb<va<v
I, o) Hold the tesamp link stimulator. The part constituting the signal of adjacent D'P(X) is S (X
) are added to the gates through resistors (1171, (+191), and transistors (+22+, (+241) are connected in series with the transistors (+181, (1201), which input the image data DP to the sources, respectively). 123), input the enable signal W' through D
'pfX) is output. As seen in the circuit that outputs D' (X), (+091. (+13
1 (Ill),
(Since it is configured in duplicate with a pair of 1151 transistors, and the gate is connected to the signal line through a resistor, a point defect in one transistor will not affect other circuits, and the defective transistor connection can be removed with a laser.) etc., to ensure the operation of the circuit.The output Dp (Xl, D'' (X) to the column electrodes has one end fixed as f! 16), (+25+). A capacitor connected to the potential Vss is attached as necessary in parallel with the capacitor between the column electrode and the opposing substrate, so as to hold the sampled data for a scanning line period of two rows. 16th In the figure, data D5 is transferred to the shift register by clock CL, and changes when the clock is high (X-'/2
1 Bit shift output and X that changes when the clock is low
It is shown in S (11, S (2) that the AND with the bit shift output is output as S (X), and φ0.φ
2. Dl, D2 sampled sequentially when φ3 is high
, D2 hatching in the same direction is S(])
, 5 (21) are all aligned in the high period, and the 14th
This indicates that S (X) is sampled high by the circuit shown in the figure. w' is an inverted signal of W, and when W is high, data in odd rows is sampled, and when w' is high, data in even rows is sampled. Since the high periods of φ3 and S (X) are at the same time, (+041.
+105) selection switch should be turned on with w, w', omit the capacity of (+06), and data D from (]07)
It is also possible to have a configuration that outputs 3. In addition, the capacitance between the column electrodes and the row electrodes on the counter substrate is small because the liquid crystal is sandwiched between them.
In the pixel configuration shown in FIG. 4, the shape of the transparent column electrode (36) is changed to the shape of the pixel electrode (33),
(If the overlap between the electrode (291, +32) connecting the row electrode and the source of the transistor and the column metal electrode is made sufficiently small, or if they are arranged so that they do not overlap, the capacitance will be extremely small. becoming and the fourteenth
According to the arrangement in the figure, the DP data line has 5(1) to S.
Since a capacitance is added due to the intersection with the N shift register output lines of (N), the capacitance after the selection switch in Figure 13 is added to the wiring capacitance as necessary, and does not go through a buffer amplifier. D', D2. The configuration is such that the signal D3 is output, and the high period of S (X) can be one period of the clock CL. G (7(Z-) of the potential selection circuit (92)
1) +Y) (Y=] ~ 7. Z is 0. ~ 07) The part constituting the signal of the repetition number of the signal group applies a force T fX) to the shift register (q+1) + and resists (126).

(Transistor (+281, (+29
1 and T (X) as a resistance (+301. [
Transistor (+32), (133) which is added to the gate through 1311 and whose source potential is Vllll
The drains of the circuit are connected in common to output G(7(Z-11+Y).Similar to the circuit shown in FIG. 14, the gate is connected to the output of the shift register through a resistor, ) and T1291, +1321
(+331 has a double configuration by inputting the same signal and the same potential to the gate and source, so it is possible to isolate the transistor that is having trouble with operation and correct it so that it operates correctly.) Figure 17 shows the clock CI.
, 6, the data D6 is transferred to the shift register, and the clock changes when it is high (X-'/21 The logical sum of the bit shift output and the X bit shift output, which changes when the clock goes low, is output as T (X). T(11
,T(2), and one period of CI,6 is Q,,Q□
~Q, are sequentially VR (VR=VC or vR・Vd),
It corresponds to the period in which a signal that changes from VGa to Vall is output, and G(+1. G(21 to G(6) is T(
1) is high (Vpp, Vpp>VcG>Vc>
Vd>Vaa), outputs Q, , Q, ~q6 which change sequentially when T(1) is low (v*l), and T(
11 is low (v[l so T(11 is high (vpp)
When , V66 is output, and when ■ (2) is high, Q, , Q, , 02 to 0. is G (7), c
(a) is output as G(9) to Gf121. The circuit in Figure 15 has two logical states, T(X) and T(Xl).

or Vllll, and T fX) , T (
Since X) is a complementary signal, it does not involve DC current consumption, and the output potential is statically determined.
The OY signal, which changes as VR, V6a, and V□, takes Vc and Vd alternately as ■8 every frame, and as shown in FIG.
V G G + V HE or turn on the transistor,
The potential is turned off. G[+1. When the enable signal W is low, the row signals of odd-numbered rows from G(31 to VCa
The transistor is turned on at the potential of , and the potential of the pixel electrode is determined with respect to the column electrode whose potential has been determined by the previous W being high, and the row signals of even-numbered rows from G +21 to G f41 are as follows.
When the enable signal W' is low, the transistor is turned on to determine the potential of the pixel electrode. Since the source potential of the transistor whose gate is connected to T (X) is V□, we set the potential of the pi of (X) to VHII *Low potential, I!□, and the shift register (91) T
(x), T(x), and the potential is Vpp, VuH
(Vpe<VHs≦Vaa<Vpp) may be output.

18, 19, 20, 21, and 22 are sample-and-hold circuit diagrams of other embodiments of the image display device of the present invention, and FIG. 23 shows the operation of the circuit in FIG. 18. FIG. In each circuit diagram, the redundant configuration shown in FIG. 14 is omitted. The circuit in Figure 18 is 5(X) (
X=] ~n), RY (Y=I ~m)02 Transistors +1341° (+351,
(+361 are connected in series, DP is input to the source of (1341), and the signal D' is sent from the drain of fl 36 to the column electrode.
(X, Yl are output, and S (X
).

Both RY and W are high (Voo) to sample the image data DP, and S (X)-RY-W is low (vss
) sampled data D' (X, Yl (V
b ~ Va, Vss≦vb<Va<V. Hold 0. As shown in Figure 23.

RY + RY + 1 is a signal with overlapping high periods, Rm overlaps with R1, and 5 fl), 5 (2) 2 shows i: m5 (X), S (X + 1) are also partially high. The periods overlap.

During the period when Sfl) is high, R,, R2, R3 to Rm become high in sequence, DP is sampled, and Dp(1
,1),D'(1,2),D'fl,3) ~DPfl
, m-1) are determined, and Ilm, R, ~Rm-2 become high in sequence during the period when continuation<5(2) is high, and D' (2, m), DP (2, IlmDP(2
, m-21 signals are determined. D'(1,11~D'
(1, m-11, DP (2, m), D' (2, 1) ~
DP(2, m-2) is a signal fixed to the column electrodes of odd rows when W is high, and I~(m-l), m, respectively.
This is the column signal of the (m+l) to f2m-2)th column. The column electrode signals of the even rows are sampled by a circuit using an inverted signal W' of the gate signal of the transistor (+361), and are sequentially high during the period when 5(1) is high.
, Ra-, D'P(1,+1.D'P(+,2
), D” +1,31~ signals to even-numbered rows 1.2.3~
It is set for the column electrode of the column. The circuit of FIG. 19 has S(
XI, RY, Ry (y> Y, Y=m, y
The OP is sampled in the logic state determined by the three input signals of ≧1) and the W signal, and the transistor (
+37) and a transistor (+38) with Ry as the gate input and Vss as the source potential are connected to the gate, and a transistor (1
39), a transistor (+4
01 are connected in series, and D' (X, Y) is output from the train. S (X), W is pi, low is Von+Vss signal, RY, Ry is high, low is VCC (>Voo), V+, L (≦Vss)
With the signal of S (X
), and when RY is low, it is the potential of Vss led when Ry is high, so (+39) is RY, S (X
) are both turned on when they are high, and turned off when R and -3(X) are low, and the circuit of FIG. 19 functions similarly to that of FIG. 18. capacity f
fi (+411 is added as necessary, RY, R
When y is low, the gate potential of 1139) is dynamically set to VSS.
to hold. The circuit of FIG. 20 is S (X).

S (x) (x >
Corresponding to +411, (142) ~ +1451, (
+46) transistor and capacitor, Ry,
Ry, S (X) (7) Signal S (X), S
(X), M, l: Changed. RY, W is Voo
Signal between 4sg, S (X), S (x) is Vcc
It is a signal between -V+ and L, and the gate of (1441 is connected to S
TX) is the high TRy (7) potential, S (X) is Rome is the potential of vsa led by S (xl), and this circuit is
It functions in the same way as in Figure 8. The circuit in Figure 21 is S (Xl
DP is selected in the logical state determined by the two human signals of , RY and the signals of w and w', and a transistor (+50) is connected to the transistor (1471) with S (X) as the gate input and DP as the source signal. Connect in series,
Connect the drains of a transistor (+48) with the stomach as the gate input and Ry as the source potential, and a transistor (+49) with W' as the gate input and VSS as the source potential, and connect the drain of (+501 to the drain of D'
(It is configured to output X, Yl.

S (X), Rv is the signal between VDD and VSS, w
, w' is the signal between VCtVt, +1501
The gate of is set to RY when W is high, and VSS when W' is high, and this circuit functions in the same manner as in FIG. S (X)
Change the input position of R7 and connect R to the gate of (+4?)
The same thing happens if S (X) is input to the source of Y, (148). The circuit in FIG. 22 has circuits (1511, (152)) similar to those in FIGS. 14, 18 to 21,
Image data DP (+511 input side source, D2
Add the inverted signal y of (+521) to the input side source of (
1511, (+153 output side drain of +521)
, (connected to the gate of the transistor +541,
The source of (+53) is Va, the source of (154) is potential b, and the commonly connected train is D' (X,
It is configured to output Yl.

D', D' Va -V8 fV, o> Va >V
It is a signal between a>Vb≧VB≧Vss1, and S (
X) or S (X), RY is sampled high, and the capacitance between the gate of (+531 and Va (1551), the capacitance between the gate of Vb of (1541 (156
) is recorded. DP is high (Va), DP is o-(V
β), (+53) is on, (+54) is off, and D'
(X, Y) becomes the potential of Va, DP is low, Dp
is high, (1531 is off, (154) is on and 1
)p(X, Yl are at the potential of vb. Since both circuits are controlled by W or W', data is determined on the column electrodes for two scanning line periods after sampling the image data. However, in the circuit of Fig. 22, after sampling DP and DP, (153) or [+541 is turned on, and DP
It has the characteristic that (X, Y) are not dynamically determined but statically determined.

In the image display device of the present invention, the case of an N-channel transistor using Si as a semiconductor has been described above, but signal and potential relationships depending on conduction type can also be appropriately considered in the case of transistors using Te or CdSe as a semiconductor. Accordingly, the gist of the present invention can be applied.6 [Effects of the Invention] The image display device of the present invention is an electrode of a liquid crystal display.

A substrate having novel features in pixel configuration and driving, and on which row electrodes are formed for transmitting data to be input to the pixel electrodes and signals for turning on and off transistors connected to the pixel electrodes;
A liquid crystal is sandwiched between opposing substrates with column electrodes facing the pixel electrodes, and a transistor is used to drive the liquid crystal for each pixel.
It achieves 100% AC drive and improves display quality. In the image coating device of the present invention, the column electrodes and the row electrodes are formed on separate substrates, and the sample/hold circuit on the column side and the potential selection circuit on the row side are formed on each of the two substrates constituting the liquid crystal display. In addition, it can be integrated with transistors with suitable characteristics, and has excellent effects in terms of packaging and cost, as it can reduce the number of connection terminals and components for driving circuits such as shift registers outside the board.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a plan view of a liquid crystal display of an image display device of the present invention;
Figure 2 is a pixel configuration diagram, Figure 3 is a layout diagram of color filters for each pixel, Figure 4 is a plan view of the pixel, Figure 5 is a cross-sectional view of the pixel, and Figures 6 and 7 are pixel electrodes. 8 is a configuration diagram of an image display device, FIG. 9 is a potential selection circuit diagram constituting a row side drive circuit, and FIG.
FIG. 11 is a timing chart showing the operation of the image display device. FIG. 12 is a block diagram of an embodiment of the image display device of the present invention, FIG. 13 is an image data selection circuit diagram, and FIG. 14 is a sample/hold circuit diagram for sending data to column electrodes of a liquid crystal display.
Figure 15 is a potential selection circuit diagram for sending signals to the row electrodes;
The figure is a timing chart of signals on the column side, and FIG. 17 is the timing chart of signals on the row side. 18, 19, 20, 21, and 22 are sample-and-hold circuit diagrams of other embodiments of the image display device of the present invention, and FIG. 23 shows the operation of the circuit in FIG. 18. FIG. (1) Two substrates (2) Two pairs of white substrates (3), (4): Pixel electrode (5) (71, (61 (8): Column electrode f'l),
(10), [11): Row electrode (12) Nidoran sister (+31: Pixel electrode (14): Liquid crystal (15): Row electrode Dtj) D (j-N) Figure 2 $3 Figure 150 Figure 23 Procedural amendment December 22, 1986

Claims (1)

[Claims] (1) In an image display device that performs display using a liquid crystal sandwiched between a substrate on which pixel electrodes connected to transistors are formed and a counter substrate on which column electrodes are formed, the gates of the transistors of each pixel are connected to each other in common for each row. connected to the electrode,
The source is connected to the row electrode to which the gate of the transistor of the adjacent pixel is connected, and the drain is connected to the pixel electrode, and the row electrode is used to turn on and off the transistor following the data put into the pixel electrode of the adjacent pixel. An image display device characterized in that periodically inverted image data is applied to the column electrodes and the column electrodes, respectively.